JP3112277B2 - Memory card - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory card, and more particularly, to a memory card which operates upon receiving a chip select signal of a negative logic signal when the memory card is inserted into a main device. The present invention relates to a memory card capable of preventing a malfunction at the time of insertion of a memory card.

[Prior Art] and [Problem to be Solved] Generally, a memory card is equipped with a plurality of memory ICs (an integrated circuit or a memory element having a storage function, and in this specification, including a memory IC). The configuration is such that one of the memory ICs is selected by a decoder.

The chip select signal (▲) for this type of conventional memory card composed of a plurality of memory ICs depends on the configuration of the memory IC. In particular, this operates at a low level (hereinafter “L”) ( In such a memory card, there is a high risk that a writing malfunction may occur during a period in which the power supply voltage is unstable at the time of insertion of the memory card.

The reason is that a terminal receiving a control signal such as a chip select signal or a read / write signal is pulled up to an external power supply Vcc, and further, an enable signal output side for an internally generated decoder or the like is directly or indirectly. This is because pull-up is often performed, and when the power supply voltage becomes unstable, an enable signal, an external chip select signal, and the like are directly affected.

FIG. 6 is a timing chart for explaining the state, in which the memory card is inserted, the terminals of the connector start contacting each other, and then the connectors are completely inserted until they are completely connected. As shown in FIG. 3A, there is a period in which the power supply voltage causes chattering. The chattering of the power supply is carried out by the enable signal (significant by "L") to the decoder, the chip select signal from the outside, and the read / write signal as shown in (b), (c) and (d) of FIG. Gives chattering. Due to this chattering, a point occurs when the chip select signal is “L” and the read / write signal is “L”, whereby the write condition for the memory IC is satisfied and the stored internal data is rewritten. An accident occurs. In the drawing, t is a period from the start of power supply to the end of chattering.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory card that can prevent data destruction due to the above-described malfunction when a memory card is inserted.

[Means for Solving the Problems] A feature of the memory card of the first invention for achieving such an object is that a chip select signal terminal for receiving a chip select signal from an external device and a write from the external device are provided. A write control signal terminal for receiving a control signal, a power supply terminal for receiving a supply voltage from an external device, and a first detection signal when the power supply voltage supplied from the external device becomes equal to or higher than a predetermined voltage value, A voltage detection circuit for generating a second detection signal when a power supply voltage supplied from an external device falls below a predetermined voltage value; and a chattering state after receiving the first detection signal from the voltage detection circuit. HIGH or LO when the chip select signal and write control signal at
Generates and supplies a decoder enable signal after the time from one significant state of W level to the other insignificant state and before the chip select signal and write control signal completely enter the stable state, and detects the voltage. A decoder enable signal generating circuit for stopping transmission of a decoder enable signal when receiving a second detection signal from the circuit, and receiving a decoder enable signal and when a chip select signal is one of a high level and a low level which is significant An address decoder that decodes a part of an address signal input from an external device and selects one of a plurality of memory ICs, and a write control signal in a significant state and the address decoder selects one of the IC memories And a plurality of memory ICs in which writing to the IC memory is performed.

A second aspect of the present invention is characterized in that a plurality of memory ICs, a decoder for decoding a part of an address signal applied from the outside and generating a signal for selecting one of the plurality of memory ICs, A power supply circuit to be supplied, and a write control signal terminal receiving a LOW level write signal from the outside to write data to the memory IC. A voltage detection circuit for detecting whether or not the value has become greater than or equal to a value, a delay circuit for receiving a detection signal of the voltage detection circuit and generating an output after a predetermined time delay, and receiving an output of the delay circuit to provide an enable signal to a decoder And an enable signal generating circuit for generating a chip signal in a chattering state when a memory card is inserted when a memory card is inserted with reference to a point in time when a detection signal is generated. After the chip signal and the write control signal enter the stable state after the transition from the LOW level state to the high level state when the chip select signal and the write control signal enter the stable state from the chattering state and before the chip select signal and the write control signal completely enter the stable state. The delay time of the delay circuit is set so that

[Operation] As described above, according to the output of the voltage detection circuit, the timing is measured, and the enable signal is sent to the decoder when the write control signal shifts to an insignificant (for example, “H”) state or after the chattering occurrence period has elapsed. Since the signal is generated, when each signal is chattering, the memory IC is not selected because the decoder is not operating, and writing for chattering can be reliably prevented. In addition, the timing of generating the enable signal is earlier than when the chip select signal and the write control signal have completely entered the stable state. It can be shorter than before. Further, when the enable signal for the decoder is generated, the control signals including the decoder itself and the power supply voltage are in a stable state, so that other malfunctions are prevented, and the data stored in the memory IC is protected.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a memory card to which the present invention is applied, and FIG. 2 is an explanatory diagram of enable signal generation timing for the address decoder.

In FIG. 1, reference numeral 10 denotes a memory card, which includes four memory ICs (A), memory ICs (B), memory ICs (C),
It has a memory IC unit 1 composed of a memory IC (D), an address decoder 8, and a power supply circuit 9. Memory IC unit 1
The data, address, read / write, and read terminals of each of the memory ICs (A), (B), (C), and (D) have data bus 2, address bus 3, and read / write signal lines (R /) 4 and a corresponding terminal on the connector 11 (shown by a thick line in the drawing) side via a read signal line (▲ ▼) 5.

The address decoder 8 is connected to the upper two bits of the address bus 3, the negative logic chip select signal line (▲ ▼ ₁ ) 6 and the positive logic chip select signal line (CS ₂ ) 7, and receives these signals. The memory ICs (A), (B), (C), and (D) from the memory IC unit 1 are output to the output.
Is generated and sent to the memory IC selection line 8a.

The above-mentioned lines (including Vcc and GND described later) of the memory card 10 are connected to respective terminals of the connector 11 when the memory card 10 is inserted into an external device such as a host computer or a memory card reader / writer. Connected to the corresponding terminal of the external device via the external device. D _{0 to} D ₇ are sent from the external device to the data bus 2 or the memory card 10
After shows the data to be sent to an external device, A ₀ to A
₁₇ shows the address signal.

The power supply circuit 9 includes a voltage detection circuit 91, an enable signal generation circuit 92, a power supply switching circuit 93, and a backup battery 94.
Power supply line (Vcc) 9a and ground line (GND)
9b, these lines are connected to corresponding respective terminals of the connector 11. This circuit monitors the power supply voltage supplied from the outside, and determines from the voltage of the power supply line (Vcc) 9a whether the memory card 10 is connected to an external device by the voltage detection circuit 91. In this circuit, when the power is not connected to an external device, the power is switched by the power supply switching circuit 93 so that the power of the backup battery 94 is supplied to the memory IC unit 1, and the data stored in the memory IC unit 1 is lost. Protect them from being compromised. When the memory card 10 is inserted into an external device, the enable signal (e) is transmitted to the address decoder 8 at a predetermined timing in response to the detection output of the voltage detection circuit 91.

As shown in FIG. 2 (a), when the voltage of the power supply line 9a (Vcc) reaches the point A, the voltage detection circuit 91 generates a detection signal by detecting it, and outputs it to the enable signal. The signal is sent to the generation circuit 92 and the power supply switching circuit 93.

The enable signal generation circuit 92 generates an enable signal ("L" significant) with a delay of T after receiving the detection signal as shown in FIG.
To make the address decoder 8 operative. The generation timing of this enable signal exceeds the chattering period B, and as shown in (c) and (d) of the figure, a negative logic significant chip select signal (▲ ▼ ₁ ) supplied from the outside. ) And the read / write signal (R /) have already exceeded the respective “L” and “H” judgment levels TH ₁ and TH ₂ , and they have already stabilized and maintain “H”. ing. In other words, the period T based on the detection signal generation time point is selected as such a period.

By the way, as can be understood from the relationship between the waveforms (a) to (d) in FIG. 2, the period T is not a long period, and the chip select signal and the read / write signal have completely entered a stable state. The period before the time. As a result, the time from insertion of the memory card 10 until it becomes usable can be shorter than before.

The period T can be easily realized by, for example, receiving the detection signal of the voltage detection circuit 91 by an integration circuit having a capacitor and shaping the waveform by a waveform shaping circuit.

Upon receiving the detection signal from the voltage detection circuit 91, the power supply switching circuit 93 switches from the backup battery 94 to the supply power supplied from the external device to Vcc independently of the operation of the enable signal generation circuit 92, and internally. An output is generated on a power supply line (VDD) 9c as a power supply, and power is supplied to the address decoder 8 and the memory IC unit 1 via this line.

In the case of this embodiment, the period from the time when the memory card is inserted to prevent chattering until the operation is permitted is given as the total period of the detection point at which the power supply voltage becomes A + the period T. The period t (see FIG. 6) until the occurrence of the ring stops is selected to be larger than the maximum value. Moreover, in this case, although there is a variation in the period t, the power supply voltage is monitored and the voltage detection circuit detects that the voltage exceeds a predetermined constant voltage (point A).
Since the detection is made at 91 and the time is set from this time, the variation at the time of insertion can be absorbed, and the time period T does not need to have much margin. For example, about 100 msec is enough.

As a result, it is possible to use the memory card substantially without inserting or waiting for a long period of time after the operation of the memory card 10 starts.

As described above, when the address decoder 8 operates by receiving the enable signal from the power supply circuit 9,
Chattering of each control signal is completely eliminated, and the memory card can be operated in a state where writing malfunction does not occur.

Next, the time from insertion to use becomes the first.
Another embodiment of the present invention, which is shorter than the embodiment shown in FIG.
This will be described with reference to FIG. 4, FIG. 4 and FIG. FIG. 3 is a block diagram of the embodiment, in which R is a pull-up resistor, and a capacitor 13 having a capacitance Ci represents the input capacitance of the negative logic chip select signal line 6. Note that the read / write signal line 4 is similar, but is not shown.

The voltage detection circuit 91a not only generates a detection signal when the voltage of the power supply line 9a changes to a state higher than a predetermined value, but also stops the detection signal when the voltage changes from a high state to a low state. I do.

Enable signal generating circuit 92a, when the voltage of the power supply line 9a receives a detection signal when the change to higher than a predetermined value state from the voltage detecting circuit 91a is a switch circuit 921 after an elapse since then by the time T ₂ The signal is turned “OFF” to change the enable signal for the decoder from “H” to “L” to make the enable signal valid. When the voltage of the power supply line 9a changes to a state lower than a predetermined value and the detection signal from the voltage detection circuit 91a stops, the delay circuit is reset by the reset circuit. As a result, the switch 921 is turned "ON", and the enable signal generation circuit 92a immediately returns the enable signal to the decoder from "L" to "H". After the delay circuit 922 the voltage of the power supply line 9a generates a delay time T ₂ that is configured to change to the enable signal generating circuit 92a to higher than a predetermined value is started, in less elapsed time T ₂ When the voltage of power supply line 9a changes to a state lower than a predetermined value, enable signal generating circuit 92a resets internal delay circuit 922, and the enable signal for the decoder is maintained at "H".

Here, the delay time T ₂ are, based on the time at which the power supply voltage becomes higher than a predetermined value close to the power supply voltage side is set to be longer than the time when the write control signal becomes "H". As shown in FIG. 4, T ₁ a time from the sawtooth wave rising point of the voltage of the power supply line 9a to the point A ₁ exceeds a predetermined constant voltage, a chip select signal from the rise time of the sawtooth wave is TH Assuming that the time until exceeding ₁ is t ₁ and the time from the rising point of the sawtooth wave to the time when the read / write signal exceeds TH ₂ is t ₂ , the delay time T ₂ is T ₁ + T ₂ > t ₁ or
T ₁ + T ₂ > t ₂ holds.

When the voltage of the power supply line 9a changes to a state lower than a predetermined value and the detection signal from the voltage detection circuit 9a stops, the power supply switching circuit 93a switches the power supply to the backup battery 94.

Now, the state of occurrence of the chattering of the power supply is various as shown in FIG. 6, and this chattering is performed for two adjacent sawtooth waves of the chattering waveform.
And when the voltage of the previous sawtooth following sawtooth wave after a delay time T ₂ has elapsed from the time that is higher than a predetermined value occurs, the next sawtooth wave in less elapsed _second delay time T is caused Can be considered separately. Therefore, for the case of the two, it will be described in detail with reference to FIGS. 4 and 5 to prevent malfunction due to chattering is prevented by the delay time T ₂ of the set.

FIG. 4 is an enlarged view of two adjacent sawtooth waves generated during the chattering period, from the time when the voltage of the previous sawtooth wave becomes higher than a predetermined value. it represents the case where the sawtooth wave of the following has occurred after a delay time T ₂ has elapsed. In point A ₁ from the rising point of the sawtooth wave has elapsed by the time T _1, the voltage of the power supply line 9a exceeds the predetermined value. Therefore, a detection signal is sent from the voltage detection circuit 91a to the enable signal generation circuit 92a and the power supply switching circuit 93a. At this time, the power supply switching circuit 93a switches the power supply to the power supply supplied from the external device to VCC, and the enable signal generation circuit 92a starts the internal delay circuit 922. The decoder enable signal changes from “H” to “L” when the delay time T _{2 has} further elapsed. On the other hand, the chip select signal exceeds TH ₁ when the time t _{1 has} elapsed from the rise of the sawtooth wave, as shown in FIG.
The read / write signal becomes TH ₂ when the time t _{2 has} elapsed from the rise of the sawtooth wave as shown in FIG.
Beyond. In this _{case, T 1 + T 2> t} 1, or T ₁ + T _2> for T ₂ as the relationship t ₂ is satisfied is set, the decoder enable signal, are three chip select signal and the read / write signal At the same time, there is no occurrence of the timing of “L”. Therefore, the writing period B ₁ which has been a conventional problem does not occur, malfunction is prevented.

Here, the values of t ₁ , t ₂ and T ₁ vary depending on the state of insertion of the memory card, but the difference between t ₁ and T ₁ and the difference between t ₂ and T ₁
Since not much variation in the difference between, it is not necessary so to take the margin to the value of T _2. Specifically, the delay time T ₂ is 100
μsec or more is sufficient, preferably 100 μsec to 100 ms
The range of ec is more preferable, and the range of 100 μm to 10 msec is more preferable.

However, as can be understood from the waveform of the rising process of FIG. 4 (c) ~ (d), the period T ₂ are not a long period,
It is shorter than the next chattering occurrence period. By repeating this, an enable signal can be generated to the decoder at the time when the stable state is finally entered from the last chattering. In this case the period T ₂ corresponding to the generation of the enable signal is also a chip select signal and the read /
This is a period before the write signal completely enters a stable state. Thereby, the time from the insertion of the memory card 10 until it becomes usable can be further shortened than in the embodiment of FIG.

When the potential of the power supply line 9a drops and falls below a predetermined value
In A _2, the voltage detecting circuit 91a sends a detection signal to the enable signal generating circuit 92a and power supply switching circuit 93a. At this time, the power supply switching circuit 93a switches the power supply to the backup battery 94, and the enable signal generation circuit 92a immediately changes the decoder enable signal from "L" to "H". At this time,
The voltages of the chip select signal and the read / write signal have begun to drop, and both of them have their respective “L”,
"H" decision level TH _1, TH ₂ follows it by the time the changes from "L" to "H" of the decoder enable signal is later than the time to change to "H" to "L". This is because, for example, it takes some time to discharge the charge of the input capacitor 13 of the negative logic chip select signal line 6. Therefore, also at this time, the three signals of the decoder enable signal, the chip select signal, and the read / write signal do not become "L" at the same time, and the writing of the memory IC due to the malfunction is prevented.

It will now be described with reference to FIG. 5 for the case where the voltage of the previous sawtooth following sawtooth wave within the delay time from the time that higher T ₂ not passed than a predetermined value has occurred.

The power supply line 9a that started rising from the rising point of the sawtooth wave
The voltage, exceeds a predetermined value at A ₁ in the figure, as in the case the power supply switching circuit 93a described above switched to supply power supplied to the VCC power from an external device, the enable signal generating circuit 92a is The internal delay circuit 922 is started. Decoder enable signal at this time because it is kept to "H", the generation of the write period B _1, which has been a conventional problem can be avoided.

At time A ₂ becomes lower than a predetermined value down voltage of the power supply line 9a is within that from time A ₁ has not yet passed the delay time T _2,
The power supply switching circuit 93a switches the power supply to the backup battery 94, the enable signal generation circuit 92a resets the internal delay circuit 922 and stops its operation, and the decoder enable signal is maintained at "H". Here, the reset of the delay circuit 922 in the enable signal generation circuit 92a can be performed by, for example, setting the capacitor to a discharge state when the delay circuit 922 is configured by an integration circuit having a capacitor.

As a result, at the time that has elapsed from a time point A ₁ for the time T _2, without the decoder enable signal changes "H"
Is maintained, and there is no possibility that a writable period occurs at this time.

The following are the rising time of the sawtooth wave begins to rise the voltage of the power supply line 9a is again at the time point A ₃ becomes higher than a predetermined value, as in the case of point A _1, the power supply switching circuit 93a is external power Switching from the default value to the power supply supplied to VCC, the enable signal generation circuit 92a starts the internal delay circuit 922. Since the decoder enable signal does not become “L” unless the delay time T ₂ has elapsed, the occurrence of the writable period B ₂ which has conventionally been a problem is prevented.

Regarding the sawtooth wave of the chattering thereafter, the occurrence of the writable period is suppressed by the same operation in one of the above two relations.

As described above, in the case where with respect to two adjacent saw-tooth wave, before sawtooth following sawtooth voltage after the delay time T ₂ has elapsed from the time that is higher than the predetermined value has occurred, generating the write period is avoided for both the case where the sawtooth wave of the following has occurred in less delay time T ₂ has elapsed. Since the voltage waveform of the power supply line 9a during the general chattering period is a combination of the two cases, it is possible to avoid the occurrence of a writable period for an arbitrary voltage waveform in this memory card.

Further, since the end of the sawtooth wave of chatter regardless of the length of the chattering period memory card is operable after a delay time T ₂ has elapsed from the time that exceeds a predetermined voltage, what time the chattering period Even if there is a target variation, the memory card can be made operable within a short time after the end of chattering.

As described above, the voltage detection circuit and the enable signal generation circuit in the power supply circuit 9 of the embodiment of FIG. 1 may use an initial reset circuit, a simple reset circuit, or the like. The signal as it is or its inverted signal can be used as an enable signal for the decoder.

The logic signals “H” and “L” used in the embodiment can be determined depending on the relationship with a counterpart circuit or the like that receives the logic signal, and any of them may be adopted. , "L".

Further, in the embodiment, a memory card having two chip select signals is taken as an example, but this may be one, and the chip select signal is a signal called a chip enable signal, a memory request signal, or the like. May be. If the signal is substantially a chip select signal, it is not limited to that name. Note that these and the read / write signal are one of the write control signals.

[Effects of the Invention] As described above, in the invention shown in the embodiment of FIG. 1, the timing is measured in accordance with the output of the voltage detection circuit, and the enable signal is generated to the decoder after the chattering occurrence period is exceeded. Therefore, when each signal is chattering, the memory IC is not selected because the decoder does not operate, and writing for chattering can be reliably prevented. Moreover, the timing of generating the enable signal is before the chip select signal and the write control signal have completely entered the stable state, so the time from when the memory card is inserted to when it can be used is determined. It can be shorter than before. Further, when the enable signal for the decoder is generated, the control signals including the decoder itself and the power supply voltage are in a stable state, so that other malfunctions are prevented, and the data stored in the memory IC is protected.

Further, according to the invention shown in the embodiment of FIG. 3, malfunctions such as writing are prevented, and no matter what time variation occurs during the chattering period, the memory card is within a short time from the end of the chattering. Can be put into an operable state, so that the memory card can be used with almost no waiting after being inserted.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a memory card to which the present invention is applied, FIG. 2 is a diagram for explaining the timing of generation of an enable signal for the address decoder, and FIG.
FIG. 4 is a block diagram of another embodiment of the present invention, FIG. 4 is an explanatory diagram of an enable signal generation timing for the address decoder of the embodiment of FIG. 3, and FIG. 5 is a diagram of the embodiment of FIG. FIG. 6 is an explanatory diagram of an enable signal generation timing for an address decoder. FIG. 6 is an explanatory diagram of chattering of each control signal at the time of insertion in a conventional memory card. 1 ... Memory IC section, 2 ... Data bus, 3 ... Address bus, 4 ... Read / write signal line, 5 ... Read signal line, 6 ... Negative logic chip select signal line, 7 ... Positive logic Chip select signal line, 8 ... Address decoder, 8a ...
... memory IC selection line, 9 ... power supply circuit, 91 ... voltage detection circuit, 92 ... enable signal generation circuit, 93 ... power supply switching circuit, (A), (B), (C), (D) ... ... Memory IC.

──────────────────────────────────────────────────の Continuation of the front page (51) Int.Cl. ⁷ identification code FI G11C 7/00 315 G06F 1/00 334H G06K 19/00 J (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/16 G06F 1/26 G06F 1/28 G06F 3/00 G06K 19/00-19/07 G11C 7/00

Claims (3)

(57) [Claims] A chip select signal terminal for receiving a chip select signal from an external device; a write control signal terminal for receiving a write control signal from the external device; a power supply terminal for receiving a supply voltage from the external device; A first detection signal is generated when the power supply voltage supplied from the device is equal to or higher than a predetermined voltage value, and the first detection signal is generated when the power supply voltage supplied from the external device is equal to or lower than the predetermined voltage value. And a high level when the chip select signal and the write control signal in the chattering state enter the stable state from the chattering state after receiving the first detection signal from the voltage detection circuit. Or chip select signal and write after the time from one significant state of LOW level to the other insignificant state A decoder that generates and supplies a decoder enable signal before the control signal completely enters a stable state, and stops sending the decoder enable signal when receiving a second detection signal from the voltage detection circuit. An enable signal generating circuit, receiving the decoder enable signal and decoding a part of the address signal input from the external device when the chip select signal is one of a high level and a low level, and An address decoder for selecting one, and the plurality of memory ICs for writing to the IC memory when the write control signal is in a significant state and the address decoder has selected one of the IC memories. A memory card, comprising: 2. The memory card according to claim 1, wherein said second detection signal is a stop signal of said first detection signal. 3. A plurality of memory ICs, a decoder for decoding a part of an externally applied address signal to generate a signal for selecting one of the plurality of memory ICs, and a power supply to which power is externally supplied A write control signal terminal for receiving a write signal of a LOW level from the outside to the memory;
In a memory card in which data is written to an IC, the power supply circuit receives a detection signal from the voltage detection circuit for detecting whether or not a power supply voltage supplied from the outside has exceeded a predetermined value. A delay circuit that generates an output after a predetermined time delay; and an enable signal generation circuit that receives an output of the delay circuit and generates an enable signal to the decoder. The chip select signal in the chattering state and the write control signal in the chattering state at the time of inserting the memory card with respect to the time point after the time point of transition from the LOW level state to the HIGH level state when entering the stable state from the chattering state and the chip select signal And the delay circuit so that the write control signal comes before the stable state is completely entered. Memory card, wherein a length of time is set.