JP3108243B2 - Encoding and decoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoding and decoding apparatus for compressing and expanding digital data.

[0002]

2. Description of the Related Art In transmission of digital data such as facsimile data, digital data is encoded on a transmission side in accordance with a predetermined rule, and an obtained code word is transmitted to a reception side. On the receiving side, the transmitted codeword is decoded in a procedure reverse to that of the encoding process, and the first digital data is reproduced. As a result, the amount of information to be transmitted is greatly reduced, and the transmission time is shortened.

FIG. 3 is a block diagram of an apparatus for encoding and decoding image data (digital data) in a facsimile. The control circuit 1 causes the arithmetic circuit 3 to execute arithmetic processing according to the operation program supplied from the ROM 2,
Further, it controls the input and output of digital data and codewords to and from the arithmetic circuit 3. The control circuit 1 is connected with internal circuits such as an image reading unit and a reproducing unit, and receives digital data from the image reading unit and outputs digital data to the image reproducing unit. The data buffer 4 accumulates the code word by a fixed number of bits, sends the code word fetched from the control circuit 1 to the transmission line through the modem, and stores the code word fetched in a fixed bit unit from the transmission line into the control circuit 1. To supply.

In digital data input from an image reading unit, white and black information for each scanning line read by scanning a document is associated with data of 0 and 1, and the information of each scanning line is Is represented by an array of data.
The continuous length of the white information and black information on the scanning line corresponds to the number of consecutive bits of the same data (run length), and the run length is proved to be a terminating code or a makeup code by the arithmetic processing in the arithmetic circuit 3. Is converted to a code word. In the terminating code, a run length is set for each bit from 0 to 63 bits, and a maximum of 8 bits is assigned to white data and a maximum of 12 bits is assigned to black data. The makeup code is set every 64 bits, and a terminating code is added to data having a run length of 64 bits or more in combination. This makeup code has a maximum of 9 bits for white data and a maximum of 1 bit for black data.
Three bits are added. Therefore, if the run length is less than 64 bits, the data is encoded into a code word of 12 bits or less, and even if the run length is 64 bits or more, it is encoded into a code word of 25 bits or less.

On the other hand, codewords (terminating code and makeup code) which are taken into the data buffer 4 from the transmission line and input to the arithmetic circuit 3 are processed in units of one codeword, and run codes represented by the codewords are processed. The data is decoded into white data or black data having a length. Accordingly, white data and black data in which 0 or 1 continues for a predetermined number of bits are continuously obtained, and these data are output from the control circuit 1 to the image reproducing unit.

FIG. 4 is a diagram for explaining the operation of the data buffer 4 during the encoding process, and FIG. 5 is a diagram for explaining the operation of the data buffer 4 during the decoding process. The data buffer 4 is configured to have the number of bits capable of storing the longest code word (for example, 13 bits).
For the sake of simplicity, the description will be made with an 8-bit configuration assuming that the code word is a maximum of 8 bits.

First, a case will be described in which 4-bit, 6-bit, and 3-bit code words obtained by the encoding process of the arithmetic circuit 3 are sequentially transmitted. In step 1, when all bits of the data buffer 4 are empty, 4 bits d
When the code words 1 to d4 are output from the control circuit 1, they are taken into the first to fourth bits of the data buffer 4. In step 2, when the 6-bit code words d5 to d10 are output, the 4 bits d5 to d8 are fetched from the fifth bit to the eighth bit of the data buffer 4, and the 8 bits d1 to d8 in the data buffer 4 are read. Is transmitted to the transmission line so that all bits are empty, and the remaining two bits d9 and d10 are taken into the first and second bits of the data buffer 4. Here, the data buffer 4
Is configured so that when a code is taken in all bits, the code is sent out to the transmission line in units of 8 bits. The code of 8 bits d1 to d8 is transmitted to make all bits empty. Therefore, the two bits d9 and d10 that could not be captured can be captured in the first bit and the second bit. And step 3
When the 3-bit code words d11 to d13 are output, the data buffer 4 is fetched from the third bit to the fifth bit because the data buffer 4 is not less than three bits. As described above, if the number of bits of the input codeword is smaller than the number of empty bits in the data buffer 4, the codeword is directly taken into the empty bits, and if the number of bits of the codeword is larger, the empty After only the bits are fetched and the codewords of the data buffer 4 are sent out and all bits are empty, the remaining codewords are fetched in order from the first bit of the data buffer 4.

Second, the code sent from the transmission line is taken in units of 8 bits, and 4 bits, 6 bits and 3 bits are taken.
A case where bit code words are sequentially extracted will be described. First, the code words of 8 bits D1 to D8 are fetched into the data buffer 4, and in step 1, 4 bits D1 to
D4 is taken out as the first code word and supplied to the control circuit 1. By the way, regarding the number of bits of each codeword,
The determination is made at the time of the arithmetic processing in the arithmetic circuit 3, and the codeword is extracted from the data buffer 4 based on the determination. In step 2, the four bits D5 to D8 remaining in the data buffer 4 are first extracted, and all the bits of the data buffer 4 become empty. The data buffer 4 is configured to take in a new code after the codes of all the bits are taken out. When the remaining 4 bits D5 to D8 are taken out, the next 8 bits D9 to D1 are taken out.
The code 6 is newly taken into the data buffer 4 from the transmission line. Therefore, the newly captured 8-bit D
Two bits D9 and D10 of the codes 9 to D16 are extracted, and 6 bits D5 to D10 combined with the previously extracted 4 bits D5 to D8 are used as the second code word in the control circuit 1.
Supplied to Then, in step 3, the data buffer 4
3 bits D11 to D1 of the 6-bit code left in
3 is taken out as the third codeword. As mentioned above,
If the number of bits of the code word to be extracted is smaller than the number of bits of the code remaining in the data buffer 4, the code in the data buffer 4 is extracted as it is. If the number of bits of the extracted code word is large, the code word is first left in the data buffer 4. Then, a code word is obtained by combining some of the newly fetched codes.

[0009]

In the coding and decoding apparatus described above, a codeword may remain in the data buffer 4 even after each step, and it is necessary to continuously operate at least in units of scanning lines. Becomes In this case, simultaneous processing of encoding and decoding cannot be performed in the same apparatus, and for example, in a facsimile, an operation of reading a transmission original while image information is being received cannot be performed.

Accordingly, an object of the present invention is to provide an encoding and decoding apparatus which enables simultaneous processing of encoding and decoding.

[0011]

DISCLOSURE OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and the feature of the present invention is to encode continuous digital data into bits corresponding to data contents. An arithmetic circuit that obtains a number of codewords and sequentially decodes the codewords in units of one unit to obtain continuous digital data; And a second buffer for sequentially receiving codes sequentially input from an external circuit, accumulating a predetermined number of bits, and supplying the same to the arithmetic circuit in units of codewords. A control circuit for determining the number of bits of the code word and controlling the input and output of the code word of the first and second buffers in accordance with the arithmetic processing operation of the circuit.

[0012]

According to the present invention, by providing the first buffer for the encoding process and the second buffer for the decoding process, even if the codeword is left in one buffer, it is stored in the other buffer. The arithmetic circuit can execute encoding and decoding processing on the codeword to be taken. Therefore, simultaneous encoding and decoding can be performed using the same device.

[0013]

FIG. 1 is a block diagram of an encoding and decoding apparatus according to the present invention. The control circuit 10 receives the operation program stored in the ROM 11, causes the arithmetic circuit 12 to execute the arithmetic processing according to the instruction, and controls the input / output of the code word and the image data (digital data). Like the arithmetic circuit 3 shown in FIG. 3, the arithmetic circuit 12 performs an arithmetic process for encoding a terminating code and a makeup code from digital data and an arithmetic process for decoding to acquire digital data from those codewords. I do. Control circuit 10
Is connected in parallel with a data buffer 13 for encoding and a data buffer 14 for decoding, and fetches a code word from the control circuit 10 into the data buffer 13 at the time of encoding processing and at the time of decoding. The codeword is configured to be taken into the data buffer 14 from the transmission line. Registers 15 and 1 for storing data indicating the number of bits of the code word.
6 are connected to the control circuit 10 so as to correspond to the data buffers 13 and 14, respectively.
The transmission of the codeword from the data buffer 13 to the transmission line and the capture of the codeword from the data buffer 14 to the control circuit 10 are controlled in accordance with the data stored in the data buffer 6.

In this encoding and decoding apparatus, when only one of the encoding and decoding processes is performed, only one of the encoding data buffer 13 and the decoding data buffer 14 operates. That is, during the encoding process, the data buffer 13 for the encoding process is used.
Perform the same operation as the step shown in FIG. 4, and during the decoding process, the data buffer 14 for the decoding process performs the same operation as the step shown in FIG. Therefore, in each of the encoding and decoding processes, the control circuit 10 and the arithmetic circuit 12
Will repeat the same operation as that of the conventional operation circuit 1.

FIG. 2 is a diagram for explaining the operation of the data buffers 13 and 14 when the encoding process and the decoding process are performed simultaneously. Here, the case where the codeword sent from the transmission line is taken in and the 4-bit and 6-bit codewords are sequentially taken out, and simultaneously the 3-bit and 7-bit codeword obtained by the encoding process are sent out to the transmission line Will be described. Each of the data buffers 13 and 14 has an 8-bit configuration.

First, the data buffer 1 is transmitted from the transmission line.
4, the code of 8 bits D1 to D8 is taken in, and in step 1, the 4 bits D1 to D4 are taken out as the first code word and supplied to the control circuit 10. At this time, the control circuit 10 determines how many bits of the eight bits D1 to D8 taken into the data buffer 14 constitute the first codeword, and gives the number of bits to the register 16.
Thereby, the data buffer 14 stops outputting when the code word of the bit number (4 bits in step 1) is given to the control circuit 10. In step 2, when the code words of three bits d 1 to d 3 are obtained by the arithmetic processing in the arithmetic circuit 12, the code words are fetched from the first bit to the third bit of the data buffer 13. Here, the register 15 contains
Data indicating the number of bits of the codeword obtained by the arithmetic processing of the arithmetic circuit 12 is input from the control circuit 10 and indicates in which bit of the data buffer 13 the codeword should be taken. In step 3, the four bits D5 to D8 remaining in the data buffer 14 are taken out and the data buffer 1
When all four bits become empty, the control circuit 10 sends an enable signal for permitting code transmission to the transmission side, and the next eight bits D9 to D16 are newly transmitted to the data buffer 14 from the transmission line. It is captured. Then, the 8-bit data D9 to D9
Two bits D9 and D10 are extracted from the code of D16,
The 6 bits D5 to D10 combined with the previously extracted 4 bits D5 to D8 are supplied to the control circuit 10 as a second codeword. In step 4, 7 bits d from the arithmetic circuit 12
When code words 4 to d10 are output, first, 5 bits d4 to d8 are fetched from the fourth bit to the eighth bit of the empty data buffer 13. This 5 bits d4
When all the bits of the data buffer 13 are filled by taking in ~ d8, the data buffer 13 sends out the taken code to the transmission line to make all bits empty. Then, the remaining two bits d9 and d10 are taken into the first and second bits of the data buffer 13. When the remaining third to eighth bits of the data buffer 13 are filled in a later step, the two bits d9 and d10 are transmitted to the transmission line together with the code.

As described above, the encoding process and the decoding process are performed alternately at each step. In the encoding process, the code output from the control circuit 10 is stored in an empty bit of the data buffer 13. Words are sequentially fetched, and in the compounding process, the codes fetched from the transmission line into the data buffer 14 are sequentially fetched in code units, and the control circuit 10
Is input to In these processes, the position where the codeword is fetched into the data buffer 13 and the data buffer 14
The data indicating the extraction position of the code word from the data buffer 13 is provided in a register 1 provided for each of the data buffers 13 and 14.
5 and 16 respectively. Therefore, even if different processing is performed in the next step, after two steps, the codeword is fetched into the data buffer 13 according to the data in the registers 15 and 16 and the data buffer 14 is read.
The extraction of the codeword from the code can be performed accurately.

[0018]

According to the present invention, since the data buffer for the encoding process and the data buffer for the decoding process are separately provided, the encoding process and the decoding process are executed alternately in each step. You. For this reason, it is possible to simultaneously process the encoding from the digital data to the code word and the decoding from the code word to the digital data, while using a single arithmetic circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an encoding and decoding device according to the present invention.

FIG. 2 is a diagram illustrating an operation of a data buffer during simultaneous encoding and decoding processing.

FIG. 3 is a block diagram illustrating a configuration of a conventional encoding and decoding device.

FIG. 4 is a diagram illustrating an operation of a data buffer during encoding processing.

FIG. 5 is a diagram for explaining the operation of a data buffer during decoding processing.

[Explanation of symbols]

 1, 10 control circuit 2, 11 ROM 3, 12 arithmetic circuit 4, 13, 14 data buffer 15, 16 register

Claims (2)

(57) [Claims] An arithmetic circuit for encoding continuous digital data to obtain a code word having the number of bits corresponding to the data content and sequentially decoding the code words for each unit to obtain continuous digital data. And a first buffer for sequentially taking in coded code words from the arithmetic circuit and outputting the same for each fixed number of bits, and sequentially taking in codes inputted continuously from an external circuit and storing the same for a certain number of bits And
A second buffer that supplies the arithmetic circuit in units of one codeword, and the number of bits of the codeword is determined in accordance with the arithmetic processing operation of the arithmetic circuit to input the codewords of the first and second buffers. An encoding and decoding device, comprising: a control circuit for controlling an output. 2. The encoding and decoding apparatus according to claim 1, wherein the encoding from the digital data to the code word and the decoding from the code word to the digital data are alternately performed step by step.