JP3193462B2 - Driving method of active matrix type thin film transistor liquid crystal panel - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving an active matrix type thin film transistor liquid crystal panel.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, the Journal of the Institute of Television Engineers of Japan Vol. 42, no.
1, P. 10 to 16 and P.E. 23-29. Conventionally, active matrix type liquid crystal panels, especially those using thin film transistors (TFT-L
Although several different methods are used for driving the CD) depending on the AC conversion method, the concept of the voltage supply method is the same. Therefore, as a representative example, a driving method (hereinafter, referred to as a frame mode) for performing an alternating operation in each scanning cycle will be described.

FIG. 13 is a configuration diagram of such a conventional active matrix thin film transistor liquid crystal panel, and FIG. 14 is a driving timing chart thereof. As shown in the figure, the active matrix type thin film transistor liquid crystal panel
In general, a gate bus line 51 and a drain bus line 52 are orthogonally arranged on a rear substrate, and a thin film transistor (TFT) 53 is provided as a switching element corresponding to each pixel electrode at the intersection, and a transparent counter electrode is provided on the front substrate. 54, an alignment film oriented in an appropriate direction is provided on the surfaces of both substrates, and the alignment films of both substrates are arranged facing each other via a liquid crystal layer and bonded together, and on the back surfaces of the front substrate and the rear substrate, A polarizing film is attached so that their polarization axes are parallel or perpendicular to each other, and a portion sandwiched between the two electrodes due to the potential difference between the voltage of the pixel electrode supplied through the TFT 53 and the voltage of the counter electrode 54. The liquid crystal 55 is switched.

The switching means of the TFT 53 is
The scanning circuit 60 is connected to the gate bus line 51 by a drain.
The data circuit 70 is connected to the
As a gate selection signal of the TFT 53, the scanning circuit 60
N voltage V_{G (+)}, OFF voltage V _{G (-)}Is the drain of the TFT 53
As the in-selection and luminance data signals, the data circuit 70
Positive write voltage V_{D (+)}, Negative write voltage
V_{D (-)}Is supplied.

Further, as shown in FIG. 14, the voltage V _S of the pixel electrode written by the TFT 53 fluctuates twice in the voltage holding state. First, TFT
When the gate selection signal of 53 changes from the ON state to the OFF state, the voltage V _{S of the} pixel electrode connected to the TFT 53 to which the selection signal is supplied _varies by ΔV ₁ due to the parasitic capacitance C _gS of the _TFT 53. I do.

Second, when the data signal changes to a polarity opposite to the polarity at the time of writing, it changes by ΔV ₂ due to an electric field effect between the pixel electrode and the drain bus line 52.
For this reason, the potential difference between the pixel electrode and the counter electrode with respect to the fluctuation of the voltage V _S of the pixel electrode is made equal to the counter electrode so that the potential difference becomes equal between the time of writing the positive polarity and the time of writing the negative polarity. A voltage V _COM is provided.

FIG. 15 shows the electro-optical characteristics of the TN liquid crystal cell in the case where the two polarizing films are bonded so that the polarization axes are parallel. The TN liquid crystal cell used for the active matrix type thin film transistor liquid crystal panel is:
There is a threshold voltage V _{TH at} which the light transmittance sharply increases and a saturation voltage V _{SAT at} which the light transmittance does not fluctuate with respect to the potential difference between the pixel electrode and the counter electrode, and a voltage range ΔV of V _{TH to} V _SAT.
In, the voltage fluctuation indicates a change in light transmittance. Therefore, in order to achieve a complete ON state, V _SAT <V _S −V _COM for positive polarity and V _SAT <V for negative polarity.
Set voltage condition of _COM -V _S, to achieve complete OFF state, V _TH> V _S -V _COM in positive polarity, the voltage condition of V _TH> V _COM -V _S is in the negative polarity By setting, the liquid crystal cell can be switched.

[0008]

However, in the above-described conventional method of driving an active matrix type liquid crystal panel, the time from when a data signal is written to a pixel electrode to when the voltage polarity of a drain bus line is inverted. Are different, for example, the first gate bus line and the N-th gate bus line selected by the scanning circuit include:
The voltage V _{S of the} pixel electrode connected via each TFT
In comparison, the period during which the voltage fluctuates by ΔV ₂ is different due to the electric field effect between the pixel electrode and the drain bus line, so that the average effective voltage applied to the liquid crystal layer in each scanning cycle is different, and the difference in light transmittance is different. appear.

Further, it is sufficient to generate a voltage fluctuation of ΔV between the pixel electrode and the counter electrode for switching the liquid crystal layer. However, the voltage of the counter electrode is fixed and the voltage of the pixel electrode is changed to the positive polarity. And a switching voltage of V _SAT × 2 (equivalent to (V _TH + ΔV) × 2) is required for the driver of the drain bus line, and ΔV + V _TH ×
An extra switching voltage is required for the voltage of 2,
This was an obstacle to lowering the withstand voltage of the driver.

[0010] It is an object of the present invention to provide the above-described variation in the average effective voltage of the liquid crystal layer in each scanning cycle and the extra switching voltage V _TH × 2 + Δ applied to the drain bus line.
In order to reduce or eliminate V, pixel electrode groups connected to one gate bus line via TFTs are alternately arranged in a staggered manner in the gate bus line direction, and two pixel electrode groups arranged in the gate bus line direction are arranged in a staggered manner. In this configuration, the gate electrodes are controlled by the gate bus lines, and the opposite electrodes are provided in correspondence with each of the pixel electrode groups arranged in the gate bus line direction. By the alternating method, where the polarity of
Variations in the average effective voltage are eliminated, and a data configuration is provided in which positive and negative data supplied to each drain bus line is supplied as inverted voltage information, and each counter electrode has an equivalent voltage amplitude. It is another object of the present invention to provide an excellent driving method of an active matrix type thin film transistor liquid crystal panel in which a write voltage is supplemented by the voltage amplitude and a switching voltage of a drain bus line and a gate bus line is reduced.

Another object of the present invention is to provide a liquid crystal display device, comprising:
Extra switching voltage V applied to the drain bus line
To reduce or eliminate _TH × 2 + ΔV, a group of pixel electrodes connected to one gate bus line via a TFT is arranged in the line direction, and connected to two adjacent gate bus lines via the TFT. In the pixel electrode group, one corrugated counter electrode is provided for a pixel electrode group selected from two gate bus lines alternately in a staggered manner in the gate bus line direction. The alternating method of showing different polarities and inverting each polarity every scan line cycle eliminates the variation of the average effective voltage, and the positive and negative data supplied to each drain bus line are inverted with each other. The data configuration is supplied as voltage information, and each counter electrode has the same voltage amplitude, and the write voltage is supplemented by the voltage amplitude, and the drain bus line It is an object of the present invention to provide a method of driving an active matrix thin film transistor liquid crystal panel excellent in achieving a low breakdown voltage of the gate bus line and the gate bus line.

[0012]

In order to achieve the above object, the present invention provides a gate bus line and a drain bus line which are orthogonally arranged on a rear substrate, and at an intersection of the gate bus line and the drain bus line. A thin film transistor is provided for each pixel electrode, a transparent counter electrode is provided on the front substrate, and an alignment film that has been subjected to alignment processing in an appropriate direction is provided on the surfaces of the back substrate and the front substrate. In a driving method of an active matrix type thin film transistor liquid crystal panel in which a polarizing film is stuck on the back surface of the rear substrate and the back surface of the front substrate, and a thin film transistor is connected to one gate bus line through the thin film transistor. The pixel electrodes connected to each other are alternately arranged in a staggered manner in the gate bus line direction, and correspond to two adjacent gate bus lines. A pixel electrode group in the gate bus line direction is constituted by the pixel electrodes of the portions, one counter electrode is provided for the pixel electrode group arranged in the gate bus line direction, a circuit for switching each counter electrode is provided, and an adjacent drain bus is provided. The polarity of the voltage data of the lines is different, and the polarity of the voltage data is inverted every scanning line cycle, and a voltage signal indicating a voltage obtained by inverting the voltage data of the positive polarity and the voltage of the negative polarity is supplied to each drain bus line. At two adjacent gate bus lines connected via a thin film transistor to a pixel electrode corresponding to each counter electrode, and fluctuates in synchronization with the write timing of the previously selected gate bus line. A voltage signal including the polarity data of the pixel electrode group corresponding to the counter electrode, an offset voltage corresponding to the threshold voltage of the liquid crystal, and an effective voltage correction voltage. It is supplied to the counter electrodes, in which to perform the voltage written to each pixel electrode by supplying a selection signal to the gate bus line.

A pixel electrode group connected to one gate bus line via a thin film transistor is arranged in the gate bus line direction, and a pixel electrode group connected to two adjacent gate bus lines via a thin film transistor. , A corrugated counter electrode is provided for a pixel electrode group selected from two gate bus lines alternately in a staggered manner in the gate bus line direction, and a circuit for switching each corrugated counter electrode is provided. different polarity of voltage data <br/> other adjacent drain bus lines, one scanning line polarity of the voltage data is inverted every cycle, and the positive polarity and negative polarity of the voltage the voltage data is inverted with respect to each other Is supplied to each drain bus line, and the two gate bus lines adjacent to each other are connected to the pixel electrode corresponding to each counter electrode via a thin film transistor. And includes an offset voltage and an effective voltage correction voltage that fluctuates in synchronization with the write timing of the gate bus line selected earlier and that corresponds to the polarity data of the pixel electrode group corresponding to each counter electrode and the threshold voltage of the liquid crystal. A voltage signal is supplied to each counter electrode, and a selection signal is supplied to a gate bus line to write a voltage to each pixel electrode.

[0014]

According to the present invention, as described above, a group of pixel electrodes connected to one gate bus line via a TFT are alternately arranged in a staggered manner in the gate bus line direction. A configuration in which the pixel electrode groups arranged in a row is controlled by two gate bus lines, and each counter electrode is provided in correspondence with each pixel electrode group arranged in the gate bus line direction,
Adjacent drain bus lines have different polarities,
The alternating method in which each polarity is inverted every scanning line period eliminates variations in the average effective voltage applied to the liquid crystal layer, and the positive and negative data supplied to each drain bus line are inverted with each other. By providing a data configuration that is supplied as voltage information and having the same voltage amplitude on each counter electrode and supplementing the write voltage with the voltage amplitude, it is possible to eliminate an extra switching voltage applied to the drain bus line.

Alternatively, TF is connected to one gate bus line.
A pixel electrode group connected via T is arranged in the line direction, and pixels are alternately selected in a staggered manner in the gate bus line direction from the pixel electrode group connected via TFT to two adjacent gate bus lines. A configuration in which one corrugated counter electrode is provided for the electrode group, and adjacent drain bus lines have different polarities, and are applied to the liquid crystal layer by an alternating method in which each polarity is inverted every scanning line period. Variations in the average effective voltage are eliminated, and the data structure is such that the positive and negative data supplied to each drain bus line are supplied as inverted voltage information, and each counter electrode has the same voltage amplitude. However, by supplementing the write voltage with the voltage amplitude, an extra switching voltage applied to the drain bus line can be eliminated.

Therefore, the average applied voltage of the liquid crystal cell can be made uniform, and the withstand voltage of the switching driver for the gate bus line and the drain bus line can be reduced. In addition, since this driving method can provide the same effect even when an analog voltage is input to the drain bus line, it can be sufficiently applied to gradation driving of an active matrix thin film transistor liquid crystal panel.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic perspective view of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention. As shown in this figure, a gate bus line 11 and a drain bus line 12 are provided on a transparent rear substrate.
Are arranged orthogonally, and a TFT 13 is provided at the intersection,
It is connected to a transparent pixel electrode 14 corresponding to each display cell. Then, pixel electrodes connected to one gate bus line 11 via the TFT 13 are alternately arranged in a staggered manner in the gate bus line direction, and two adjacent gate bus lines 11 form a line in the gate bus line direction. A configuration is adopted in which the pixel electrode groups arranged in a line are switched. Further, an alignment film that has been subjected to an alignment treatment in an appropriate direction is provided on the back substrate.

On the other hand, on a transparent front substrate, a transparent counter electrode 1 divided into a line shape in the same number as the number of lines of the pixel electrode group is provided.
5 to provide an alignment film that has been subjected to an alignment treatment in an appropriate direction. The alignment films of the rear substrate and the front substrate face each other, are aligned so that a pixel electrode group arranged in a line and one counter electrode are arranged to face each other, and an appropriate gap is provided between both substrates. After injecting the liquid crystal, the liquid crystal is sealed, and a polarizing film is attached to the exposed surfaces of both substrates so that their polarizing axes are parallel or perpendicular to each other. In addition, 15a is a portion facing the pixel electrode.

FIG. 2 is a schematic configuration diagram of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention.
FIG. 3 is a schematic block diagram of a data circuit of an active matrix type thin film transistor liquid crystal panel according to an embodiment of the present invention. FIG. 4 is a diagram of voltage data supplied to a drain bus of the active matrix type thin film transistor liquid crystal panel according to the embodiment of the present invention. FIG. 4 is a diagram showing timing, and FIG.
(A) is a voltage waveform diagram of the odd drain bus, FIG.
(B) is a voltage waveform diagram of the even drain bus. FIG. 5 is a schematic block diagram of a common variation circuit of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention.

As shown in these figures, the number of gate bus line <br/> emissions 11 N + 1, the number of drain bus lines 12 M
When the scanning circuit 20 is connected to the N + 1 pieces of gate bus lines 11, temporally sequentially supplies t _on time corresponding ON voltage V _G of ₍₊₎ 'in one scanning period from the first gate bus line 11 , And a data circuit 30 including a data generation unit 31, a data inversion unit A32, a data inversion unit B33, a data output unit A34, and a data output unit B35 are connected to the M drain bus lines 12, and luminance data and polarity data are transmitted. Is supplied to the N opposing electrode groups, two shift register units A41, a shift register unit B44, voltage amplifying units 42 and 45, a driver unit A43, and a driver unit B.
And a voltage signal including a polarity data corresponding to the voltage data supplied to the drain bus line 12, an offset voltage corresponding to a threshold voltage of the liquid crystal 16, and an effective voltage correction voltage. I do.

As shown in FIG. 4, in this embodiment, a single gate bus line 11 switches pixel electrodes 14 arranged in a staggered manner in the gate bus line direction. In the line 11 and the (N + 1) th gate bus line 11, the T connected to the even-numbered pixel electrode in the gate bus line direction is
Only the FT and the TFT connected to the odd-numbered pixel electrode are switched. Therefore, when writing one frame of image data, the odd-numbered pixel electrode groups in the gate bus line direction are written at the write timing from the second gate bus line to the (N + 1) th gate bus line.
For even-numbered pixel electrode groups in the gate bus line direction, voltage data must be supplied from the drain bus lines at the write timing from the first gate bus line to the Nth gate bus line.

Therefore, the data generator 3 of the data circuit 30
1, the luminance data of one line is divided into odd-numbered display cell data and even-numbered display cell data in the gate bus line direction, and the first gate data is divided into odd-numbered display cell data in the gate bus line direction. Dummy data d _D as data corresponding to the bus line, data d ₁ of the first line as data corresponding to the second gate bus line, and data d ₂ of the second line as data corresponding to the third gate bus line. ,..., As the data corresponding to the (N + 1) th gate bus, the data d _N on the Nth line are sequentially supplied as data 1.

Further, as data of an even-numbered display cell in the gate bus line direction, data d ₁ of the first line as data corresponding to the first gate bus line, and two lines of data as data corresponding to the second gate bus line. eye data d _2, ... data d _N of the N-th line as data corresponding to the N gate bus lines, as data corresponding to the first N + 1 gate bus line, the data 2 supplies dummy data d _D sequentially create.

In the data generator 31, the odd-numbered drain bus and the even-numbered drain bus have different write polarities and correspond to the odd-numbered drain bus as an alternating signal whose polarity is inverted for each scanning line. An AC signal 1 and an AC signal 2 corresponding to an even-numbered drain bus are created. The data 1 and the AC signal 1 are operated by a data inverting unit A32 to create voltage data including luminance data and polarity data, data 3, and a data output unit A3.
4, the odd-numbered drain buses D ₁ , D ₃ ,.
Output to _DM-1 . Similarly, data 2 and alternating signal 2 are
The data inverting unit B33 calculates the voltage data including the luminance data and the polarity data, the data 4, and the data output unit B35 generates the even-numbered drain buses D ₂ ,
Output to D ₄ ,..., D _M.

The voltage data setting condition of each drain bus output from the data circuit 30 is such that, in the writing of the positive polarity, the ON voltage V _{D (+)} ′, the OFF voltage V _{D (−)} ′, and the negative voltage ON voltage V when writing
_{D (−)} ′ and OFF voltage V _{D (+)} ′, the voltage amplitude can be set to be equal to ΔV shown in FIG. 15, and V _{D (+)} ′ −V
_{D (-)} '= V _SAT -V _TH = ΔV
Compared to the conventional example of FIG. 14, the amplitude of the drain voltage is V _TH
It can be reduced by (× 2 + ΔV).

FIG. 6 shows an operation timing chart 1 of a common variation circuit of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention, and FIG. 7 shows an operation timing chart 2 of the common variation circuit. In the present invention, instead of setting the amplitude of the drain voltage to be equal to ΔV, a voltage such as an offset voltage of the liquid crystal is supplied by a voltage signal of the counter electrode. Therefore, an offset voltage of the write polarity of the even-numbered drain bus line is written to the first counter electrode at the write timing of the first gate bus line, and the odd-numbered drain bus is written to the first gate bus line at the write timing of the second gate bus line. A voltage signal for replenishing the offset voltage or the like of the write polarity is supplied to the second counter electrode. At the write timing of the second gate bus line, the offset voltage or the like of the write polarity of the even drain bus is supplied to the second counter electrode. At the write timing of the third gate bus line, a voltage signal for supplementing an offset voltage or the like of the write polarity of the odd drain bus is supplied, and similarly, a voltage signal is supplied to the Nth counter electrode.

Also, since the polarities of the odd drain bus and the even drain bus at the same write timing are different, and the polarities are inverted at the next write timing, each counter electrode has a corresponding pixel electrode. Are supplied to the even-numbered drain buses, a voltage signal that fluctuates in synchronization with the writing timing of the pixel electrode connected via the TFT.

Therefore, of the two-system circuit configuration, the shift register section A41 changes immediately before the application of the ON voltage to the first gate bus line as shown in FIG. a signal DF1 having polarity data of the even-numbered pixel electrodes in the line direction, and a clock [Phi _C having a period of t _on time synchronization with the rising of the oN voltage application of each of the gate bus line, and corresponds to one scan time The waveform D that is supplied and sequentially delayed by two clocks from _DC1
C3 , D _C5 ,..., D _CN-1 are created and supplied to the voltage amplifying unit, and R ₂ / R _{1 is set} by the operational amplifier and the resistors R ₁ and R _2.
Inverted amplified doubles, creates a voltage signal having a predetermined voltage amplitude, including polarity correction voltage of the time offset voltage and the gate bus select, via a protection resistor R ₃ and the driver unit A43, the first opposing The voltage signal V _COM1 is supplied to the electrode, the voltage signal V _COM3 is supplied to the third counter electrode, and the voltage signal V _COMN-1 is supplied to the (N−1) th counter electrode.

As shown in FIG. 7, the shift register B44 has an even-numbered pixel in the second gate bus line which fluctuates immediately before the application of the ON voltage to the first gate bus line and which is in the line direction. a signal DF2 having polarity data electrode in synchronization with the rising of the oN voltage application of each of the gate bus line, and supplies a clock [Phi _C having a synchronous t _on time, one clock later than the D _C1 in FIG. 6 create a waveform D _C2 was further D _C2 than sequentially delayed waveform by two clocks min D _C4, D _C6 ..., create a D _CN, which was supplied to the voltage amplifier, an operational amplifier and resistors R _1, R ₂ By R ₂
/ Inverted amplified R to _1x, the offset voltage, to create a voltage signal having a predetermined voltage amplitude, including polarity correction voltage of the time gate bus selection, protection resistor R ₃ and the driver unit B46
Through, a voltage signal V _COM1 to the second counter electrode, a voltage signal V _{CO M4} in the fourth counter electrode, respectively supply voltage signal V _COMN to the N-th counter electrode.

Note that V _COM1 , V _COM2 ,
, V _COMN may supply a voltage signal having the same voltage amplitude, so that a binary output drain driver can be applied to the common variation circuit. FIG. 8 is an equivalent circuit diagram of a liquid crystal cell showing an embodiment of the present invention. In the case of the above-described driving method, the fluctuation of the pixel voltage in the charge holding state of the liquid crystal cell occurs under at least three conditions.

Firstly, immediately after writing of the TFT connected to the pixel electrode, the parasitic capacitance C _gs of the TFT, [Delta] V ₁ '=
[C _gs / (C _gs + C _LC + C _DP1 + C _DP2 )] × (V
_{G (+)} ′ ₋ V _{G (−)} ′), and then the two drain bus lines 12 sandwiching the pixel electrode deviate from the writing voltage by ΔV
_{When D1} 'and [Delta] V _D2' only varies, [Delta] V ₂ by the capacitance C _DP1 and C _DP2 between the drain bus line 12 of the pixel electrode and two '= _{[C DP1 / (C gs + C} LC + C DP1 + C
_DP2 )] × ΔV _D1 '- [ C _DP2 / (C _gs + C _LC + C _DP1
+ C _DP2)] × [Delta] V _D2 ', further, when the voltage of the common electrode to perform charge accumulation between the pixel electrode is varied only [Delta] V _COM, a liquid crystal of the capacitance C _LC, ΔV _3' = [C _LC / ( C
_gs is a _{+ C LC + C DP1 + C} DP2) ] × [Delta] V _COM.

If the same TFT is formed in all the pixel electrodes, the potential fluctuation ΔV ₁ ′ has the same polarity and the same potential regardless of the writing voltage and the writing timing. In the setting of the voltage to be set, the voltage between the pixel electrode and the counter electrode ( hereinafter, referred to as “V”) is set in all the liquid crystal cells by shifting the voltage by ΔV ₁ ′.
Lower effective voltage) can be maintained in an equivalent state .

Further, the potential fluctuations ΔV ₂ ′ and ΔV ₃ ′ differ in the polarity of the pixel voltage fluctuation depending on the polarity at the time of writing. The amount of the fluctuation depends on the polarities of the two drain buses and the counter electrode sandwiching the pixel electrode. It shows the largest voltage fluctuation at the time of writing and when it changes. Therefore, in each pixel electrode, if there is a short period and a long period during which both polarities are changed with respect to the polarity at the time of writing, the average effective voltage differs, and display unevenness occurs.

FIG. 10 is a timing chart showing a drive voltage and a pixel voltage change of a TFT connected to an odd-numbered drain bus line according to the embodiment of the present invention. FIG. 11 is a timing chart showing an embodiment of the present invention. 6 is a timing chart showing a driving voltage of a TFT and a pixel voltage change. Therefore, in this embodiment, the voltage signals V _COM1 , V _COM2 ,..., V _COMN supplied to the counter electrode are set by _shifting the voltage variation ΔV ₁ ′, and the polarity of each drain bus line is set to 1 Since the alternating drive is performed in which the polarity is inverted in the line cycle, the period during which the polarity of the two drain buses sandwiching the pixel electrode is changed from that at the time of writing is the same for all the pixel electrodes, and the average effective voltage Is uniform.

The polarity of the counter electrode with respect to each pixel electrode is different from that of the pixel electrode connected to the odd-numbered drain bus line via the TFT during the period during which writing is being performed.
Since it occurs at most T × (1 / N + 1) and does not occur on the pixel electrode connected to the even-numbered drain bus line via the TFT, the fluctuation of the average effective voltage due to the influence of ΔV ₃ ′ is ignored. To a good degree.

Further, in consideration of the above, the voltage signals of V _COM1 , V _COM2 ,..., V _COMN supplied to the counter electrode are _{added to} the voltage signals of all the pixel electrodes calculated from the display data.
V _COM1, V _COM2 to supply 'average voltage variation of Δ V _2' V ₂ ^* a is added as the effective voltage loss in caused by the voltage fluctuation of the [Delta] V ₂ ', ..., the voltage waveform of the V _COMN positive At the time of writing, V _{D (+)} ′ − ΔV−V _TH −Δ
At the time of writing the negative polarity to the voltage level of V ₁ ′ − ( ΔV ₂ ′ ^* ), V _{D (−)} ′ + ΔV + V _TH −ΔV ₁ ′ + (Δ
ΔV + 2V _TH +2 set to the voltage level of V ₂ ′ ^* )
× ( ΔV ₂ ′ ^* ), the average effective voltage of all the pixels is ΔV + V _TH even when the amplitude of the voltage data output from the data circuit is set to ΔV. It can be about the same. Similarly, as the amplitude of the drain voltage decreases, the amplitude of the gate voltage can be reduced to the same extent.

FIG. 9 is an equivalent circuit diagram of an active matrix type thin film transistor liquid crystal panel according to an embodiment of the present invention. As shown in FIG. 1 and FIG. 2, since a large number of electrical wirings are provided in the active matrix type thin film transistor liquid crystal panel, a wiring capacitance exists as a constituent condition of the liquid crystal panel. Generates loss current when writing to _LC . Each time the voltage of the drain bus line fluctuates, the capacitance C _GD created by the intersection of the drain bus line 12 and the gate bus line 11 is equal to the voltage fluctuation amount of the drain bus line 12 in the gate bus line 11 and the drain bus line 12. And a capacitance C _DC generated between the drain bus line 12 and the counter electrode 15 via the liquid crystal layer.
Similarly, every time the voltage of the drain bus line 12 fluctuates, a loss current proportional to the voltage fluctuation amount of the drain bus 12 is generated in the drain bus line 12 and the counter electrode 15.

The C shown in each display cell unit shown here
Without large so much amount of current generated by _GD and C _DC, for considering the whole wire is fairly large current, short duration loss current, in order to release, for example, in line periods outside the panel, the drain bus The resistance of the line 12, the gate bus line 11, and the counter electrode 15 must be reduced, and the current capacity of the external driver connected to each wiring must be increased.

In the embodiment of the present invention, the polarities of adjacent drain buses are different, and when the polarities fluctuate, the adjacent drain buses always have voltage fluctuations of different polarities, for example,
When one changes from positive to negative, the other changes from negative to positive. Therefore, since the loss currents generated by the adjacent capacitances C _GD or by the adjacent capacitances C _DC on one counter electrode divided for each line are currents flowing in opposite directions, the loss currents Shows a tendency to offset.

For this reason, the loss current flowing through one gate bus line and drain bus line and the counter electrode divided for each line is extremely small, and the resistance of each wiring is reduced and the connection to each wiring is reduced. In addition to providing a liquid crystal panel that does not require an increase in the capacity of an external driver, it is suitable for increasing the capacity and definition of the liquid crystal panel. FIG.
FIG. 2 is a schematic configuration diagram of an active matrix type thin film transistor liquid crystal panel showing a modified embodiment of the present invention. Note that the same parts as those in the above embodiment are denoted by the same reference numerals, and description thereof will be omitted.

In this embodiment, the liquid crystal capacitance _CLC between each pixel electrode and the counter electrode of the active matrix type thin film transistor liquid crystal panel having the structure described in detail with reference to FIGS. In parallel, the auxiliary capacitance C _s 17
And connected to the common variation circuit 40 by the auxiliary capacitance line 18, and the image in the charge holding state of the liquid crystal cell is provided.
The variation of the elementary voltage is represented by ΔV ₁ ″ = [C _gs / (C _gs
+ C _LC + C _s + C _DP1 + C _DP2 )] × (V _{G (+)} ′ − V
_{G (-) '), ΔV} 2 "= _{[C DP1 / (C gs + C} LC + C s
+ C _DP1 + C _DP2 ) ] × ΔV _D1 '- [ C _DP2 / ( C _gs +
C _LC + C _s + C _DP1 + C _DP2 ) ] × ΔV _D2 ′, ΔV ₃ ″
= _{[(C LC + C s) /} (C gs + C LC + C s + C DP1 + C
_DP2)] for the the canceller × [Delta] V _COM fluctuations in the effective voltage
It can be reduced . By this effect, the voltage amplitude supplied to the gate bus line can be easily reduced by reducing the correction voltage and voltage amplitude of V _COM1 , V _COM2 ,..., V _{COMN supplied} to the _common electrode.

FIG. 16 is a schematic perspective view of an active matrix type thin film transistor liquid crystal panel showing another embodiment of the present invention. As shown in this figure, a gate bus line 11 and a drain bus line 12 are arranged orthogonally on a transparent back substrate, and a TFT 13 is provided at the intersection between the gate bus line 11 and the drain bus line 12, so that transparent pixel electrodes corresponding to individual display cells are provided. Connect to 14,
A pixel electrode group connected to one gate bus line via the TFT 13 is arranged in the line direction, and an alignment film that has been subjected to an alignment process in an appropriate direction is provided. In addition, 19 is a gap.

On the other hand, from a group of pixel electrodes connected to two adjacent gate bus lines on the transparent front substrate via the TFT 13, a group of pixel electrodes selected alternately in a staggered manner in the gate bus line direction. A transparent corrugated counter electrode 15 is provided, a plurality of corrugated counter electrodes are provided, and an alignment film that has been subjected to an alignment treatment in an appropriate direction is provided. The alignment films of the rear substrate and the front substrate face each other, are aligned, provide an appropriate gap between the two substrates, inject liquid crystal, seal, and the polarization axes are parallel to each other on the exposed surfaces of the two substrates. A polarizing film is stuck so as to be vertical. FIG. 17 is a diagram showing a configuration of a counter electrode of an active matrix type thin film transistor liquid crystal panel according to an embodiment of the present invention.

As shown in the figure, a corrugated counter electrode is a pixel electrode group selected from a group of pixel electrodes connected to two adjacent gate bus lines via a TFT 13 alternately in a staggered manner in the gate bus line direction. In order to provide one transparent counter electrode for the group, the pattern configuration 1 shown in FIG.
As shown in FIG. 1, the gate bus line is formed over two adjacent gate bus lines. For this reason, in the pattern configuration 1, when the pixel pitch is reduced, the junction between the two gate bus lines becomes thinner, the electrical resistance increases, and a potential difference is generated to the extent that display unevenness can be recognized. there's a possibility that. In the pattern configuration 2 of FIG. 17B, the opposing electrode junction 15b is formed of aluminum or the like having a low electric resistance value so as to be able to cope with a fine pixel pitch. Here, 15a is a portion facing the pixel electrode.

FIG. 18 is a schematic structural view of an active matrix type thin film transistor liquid crystal panel according to another embodiment of the present invention. The data circuit of the active matrix type thin film transistor liquid crystal panel is similar to that of FIG. 3 and is not shown here. FIG. 19 is a diagram showing the timing of voltage data supplied to the drain bus of an active matrix thin film transistor liquid crystal panel according to another embodiment of the present invention, and FIG. 19 (a) is a voltage data waveform diagram of the odd-numbered drain bus line. FIG. 19B is a voltage data waveform diagram of the even drain bus line. FIG. 20 is a diagram showing a common variation circuit of an active matrix type thin film transistor liquid crystal panel according to an embodiment of the present invention.

As shown in these figures, the gate line 1
Assuming that the number of 1s is N and the number of drain bus lines 12 is M, the scanning circuit 20 is connected to the N gate bus lines 11 and sequentially turned on sequentially from the first gate bus lines 11.
Supplying t _on time corresponding to the voltage V _{G (+)} 'to one scan time,
A data circuit 30 including a data generation unit 31, a data inversion unit A32, a data inversion unit B33, a data output unit A34, and a data output unit B35 is connected to the M drain bus lines 12, and includes luminance data and polarity data. Voltage data is supplied, and two systems of a shift register unit A41 and a shift register unit B44 are provided to the N + 1 divided counter electrode group.
And a voltage amplifying unit 42, 45 and a common variation circuit 40 including a driver unit A43 and a driver unit B46.
A voltage signal including polarity data corresponding to the voltage data supplied to the drain bus line 12, an offset voltage corresponding to the threshold voltage of the liquid crystal 16, and an effective voltage correction voltage is supplied.

As shown in FIG. 19, in this embodiment, in the data generating section 31 of the data circuit 30, the luminance data of one line of the drain bus is divided in the line direction into the data of the odd-numbered display cells and the even-numbered display cells. The data is divided into display cell data, data 1 and data 2 are created, and the polarity of the writing of the odd drain bus line and that of the even drain bus line are different, and the polarity is inverted for each drain bus line. An alternating signal 1 corresponding to the odd-numbered drain bus and an alternating signal 2 corresponding to the even-numbered drain bus are created.

The data 1 and the alternating signal 1 are transmitted to the data inverting section A
32, voltage data including luminance data and polarity data, data 3 are generated, and output to the odd-numbered drain buses D ₁ , D _3, ..., D _M-1 by the data output unit A34. Similarly, the data 2 and the alternating signal 2 are operated by the data inverting section B33 to generate voltage data and data 4 including luminance data and polarity data, and the data output section B35 to generate even-numbered drain buses D ₂ and D ₂ . ₄ ..., and outputs it to the D _M.

The condition for setting the voltage data of each drain bus output from the data circuit 30 is as follows: in the writing of the positive polarity, the ON voltage V _{D (+)} ′, the OFF voltage V _{D (−)} ′, and the negative voltage. In the write operation, the ON voltage VD _(-) 'and the OFF voltage VD ₍₊₎ ', the voltage amplitude can be set to be equal to ΔV shown in FIG. 15, and VD ₍₊₎ '-V
_{D (-)} '= V _SAT -V _TH = ΔV
Compared to the conventional example of FIG. 14, the amplitude of the drain voltage is V _TH ×
It can be reduced by 2 + ΔV.

FIG. 21 is a first timing chart of a common variation circuit of an active matrix type thin film transistor liquid crystal panel showing another embodiment of the present invention, and FIG. 22 is an active matrix type thin film transistor showing another embodiment of the present invention. 4 shows a second timing chart of a common variation circuit of a liquid crystal panel. In this embodiment, instead of setting the amplitude of the drain voltage to be equal to ΔV, a voltage such as an offset voltage of the liquid crystal is supplied by a voltage signal of the counter electrode. Since each counter electrode is arranged as described in detail with reference to FIGS. 16, 17 and 18, at the write timing of the first gate bus line, the offset of the write polarity of the odd drain bus is applied to the first counter electrode. A voltage signal such as a voltage is supplied, and a voltage signal such as an offset voltage of a write polarity of the even drain bus is supplied to the second counter electrode.

At the write timing of the second gate bus line, a voltage signal such as an offset voltage of the write polarity of the odd drain bus is supplied to the second counter electrode, and the even drain bus is supplied to the third counter electrode. And a voltage signal such as an offset voltage of the write polarity. Thereafter, a voltage signal is supplied in the same manner, and at the write timing of the N-th gate bus line, a voltage signal such as an offset voltage of the write polarity of the odd drain bus is supplied to the N-th counter electrode, and the voltage signal is supplied to the (N + 1) -th counter electrode. By supplying a voltage signal such as an offset voltage of the write polarity of the even drain bus, writing of one screen is completed.

At this time, at the same gate bus line write timing, the odd drain bus and the even drain bus have different polarities, and at the next gate bus line write timing, their polarities are inverted. Therefore, a voltage signal that fluctuates in synchronization with the writing timing of the pixel electrode connected to the even-numbered drain bus via the TFT, except for the first counter electrode among the corresponding pixel electrodes, is applied to each counter electrode. Will be supplied.

Therefore, as shown in FIG. 21, the shift register section A41 of the two systems has the first circuit structure.
Fluctuate ON voltage application just before the gate bus line, and a signal DF with odd polarity data in the line direction of the first line in synchronization with the rising of the ON voltage application of each of the gate bus lines, and the t _on time A clock Φ _C having a period is supplied to generate D _C1 , a waveform D _C3 delayed by one clock from D _C1 indicating even-numbered polarity data of the second gate bus line is generated, and a fourth gate is generated. A waveform D _C3 that is delayed by one clock from D _C1 indicating even-numbered polarity data of the bus line is created, and a waveform D _C5 that is delayed by two clocks from D _C3 that indicates even-numbered polarity data of the fourth line is created. , waveform D _C7 was similarly delayed by 2 clock minutes or less, ...,
Create a D _{CN + 1,} which was supplied to the voltage amplifier, and the inverting amplifier to the R ₂ / R ₁ times by an operational amplifier and resistors R _1, R _2,
Create a voltage signal having a predetermined voltage amplitude, including polarity correction voltage of when the liquid crystal is offset voltage and the gate bus select, via a protection resistor R ₃ and the driver unit A43, the voltage signal to the first counter electrode V _COM1 , a voltage signal V _COM3 to the third counter electrode, and a voltage signal V _{COMN + 1} to the (N + 1) th counter electrode.

Further, the shift register section B44 has the configuration shown in FIG.
2, a signal -DF2 which varies immediately before the application of the ON voltage to the first gate bus line and has even-numbered polarity data in the line direction of the first gate bus line, and a clock Φ _C are supplied; DC _C2 is generated, and a waveform D _C4 delayed by two clocks from D _C2 indicating even-numbered polarity data of the third gate bus line is generated. Similarly, waveforms D _{C6,. A CN} is created and supplied to a voltage amplifying unit, and R _{2 is connected} by an operational amplifier and resistors R ₁ and R _2.
/ R ₁ times by the inverting amplifier, to create a voltage signal having a predetermined voltage amplitude, including polarity correction voltage of the time offset voltage and the gate bus select, via a protection resistor R ₃ and the driver unit B46, second The voltage signal V _COM2 is applied to the
The voltage signal V _COM4 is supplied to the N-th counter electrode, and the voltage signal V _COMN is supplied to the N-th counter electrode. Since V _COM1 , V _COM2 ,..., V _{COMN + 1} output here may supply voltage signals having the same voltage amplitude, it is necessary to apply a binary output drain driver to the common variation circuit. Can also.

The equivalent circuit of the liquid crystal cell is the same as that of FIG.
In the case of the above-described driving method, the fluctuation of the pixel voltage in the charge holding state of the liquid crystal cell occurs under at least three conditions. First, [Delta] V ₁ immediately after writing TFT connected to the pixel electrode, the parasitic capacitance C _gs of the TFT '= [C
_gs / (C _gs + C _LC + C _DP1 + C _DP2 )] × (V _{G (+)} ′
−V _{G (−)} ′), and when the two drain buses sandwiching the pixel electrode fluctuate from the voltage at the time of writing by ΔV _D1 ′ and ΔV _D2 ′, the voltage between the pixel electrode and the two drain buses The capacitances C _DP1 and C _DP2 of ΔV ₂ ′ = [ C _DP1 / (C
_{gs + C LC + C DP1 +} C DP2) ] × ΔV _D1 '- [C _DP2 /
(C _gs + C _LC + C _DP1 + C _DP2 )] × ΔV _D2 ′
When the voltage of the counter electrode that accumulates electric charge between the
When only fluctuates V _COM, a liquid crystal of the capacitance C _LC, [Delta] V
₃ '= [C _LC / (C _gs + C _LC + C _DP1 + C _DP2 )] × Δ
V _COM .

The potential fluctuation ΔV ₁ ′ is a fluctuation of the same polarity and the same potential irrespective of the writing voltage and the writing timing if the same TFT is formed in all the pixel electrodes. In the setting of Δ
By setting the shift by V ₁ ′, the effective voltage can be maintained in the same state in all the liquid crystal cells.

The potential fluctuations ΔV ₂ ′ and ΔV ₃ ′ differ in the polarity of the pixel voltage fluctuation depending on the polarity at the time of writing. The amount of the fluctuation depends on the polarity of the two drain bus lines and the counter electrode sandwiching the pixel electrode. Shows the largest voltage fluctuation when it changes. Therefore, in each pixel electrode, if there is a short period and a long period during which both polarities are changed with respect to the polarity at the time of writing, the average effective voltage differs, and display unevenness occurs.

FIG. 23 is a timing chart showing the drive voltage and pixel voltage change of the TFT connected to the odd drain bus of another embodiment of the present invention, and FIG. 24 shows the even drain bus of another embodiment of the present invention. 3 is a timing chart showing changes in the drive voltage and the pixel voltage of the TFT connected to the TFT. Therefore, in this embodiment, the voltage signals V _COM1 , V _COM2 ,..., V _{COMN + 1} to be _{supplied to the common} electrode are set by _{shifting the} voltage variation ΔV ₁ ′, and the polarity of each drain bus line is changed. Since the alternating drive is performed in which the polarity is inverted in one line cycle of the drain bus, the period in which the polarities of the two drain bus lines sandwiching the pixel electrode are changed during writing is the same as for all the pixel electrodes And the average effective voltage becomes uniform.

The polarity of the counter electrode with respect to each pixel electrode is changed only for the pixel electrodes arranged in the second to Nth drain bus lines connected to the odd drain bus lines via the TFTs during the period during which the writing is changed. Exists, and for that period,
Since the period is T × 1 / N = t _on , which is much shorter than the charge holding period T of each pixel electrode, the variation of the average effective voltage due to the influence of ΔV ₃ ′ is negligible. Become.

Further, in consideration of the above, the voltage signals of V _COM1 , V _COM2 ,... V _{COMN + 1} supplied to the counter electrodes are _{added to} the voltage signals of all the pixel electrodes calculated from the display data.
The V ₂ 'average voltage variation delta V ₂ of' ^*, as the effective voltage loss in caused by the voltage fluctuation of the [Delta] V ₂ ', in order to supply added, V _COM1, V _COM2, ..., the V _{COMN + 1} When writing the voltage waveform to the positive polarity, V _{D (+)} ′ − ΔV−V
_TH - [Delta] V ₁ - the voltage level of the ^{_{'(Δ V 2' *)}} , the time of writing of the negative _{polarity, V D (-) '+} ΔV + V TH -ΔV 1'
+ Delta V ₂ 'is set to the voltage level of ^{* ΔV} + 2V _TH +2
× ( ΔV ₂ ′ ^* ), the amplitude of the voltage data output from the data circuit becomes Δ
Even when it is set to V, the average effective voltage of all the pixels can be made approximately equal to ΔV + V _TH . Similarly, the amplitude of the gate voltage can be reduced to the same extent as the amplitude of the drain voltage decreases.

The equivalent circuit of the liquid crystal panel is the same as that shown in FIG. 9, and as shown in FIGS. 16, 17, and 18, the active matrix thin film transistor liquid crystal panel is provided with a large number of electrical wirings. Wiring capacitance exists as a component condition of the liquid crystal panel, and the liquid crystal capacitance C _{LC of} each display cell
When writing data into the memory, a loss current is generated. The capacitance C _GD created by the intersection of the drain bus and the gate bus generates a loss current in the gate bus and the drain bus in proportion to the amount of voltage change of the drain bus every time the voltage of the drain bus changes, Similarly, the capacitance C _DC created between the drain bus and the counter electrode via the layer has a loss current proportional to the amount of voltage change of the drain bus flowing to the drain bus and the counter electrode every time the voltage of the drain bus changes. Generate.

The C existing in each display cell unit shown here
Without large so much amount of current generated by _GD and C _DC, for considering the whole wire is fairly large current, short duration loss current, in order to release, for example, in line periods outside the panel, the drain bus In addition, the resistance of the gate bus and the counter electrode must be reduced, and the current capacity of the external driver connected to each wiring must be increased.

In this embodiment, the adjacent drain buses have different polarities, and when the polarity fluctuates, the adjacent drain buses necessarily have voltage fluctuations of different polarities. For example, when one of the two fluctuates from positive to negative, The other will change from negative polarity to positive polarity. Therefore, the loss currents generated by adjacent capacitances C _GD on one gate bus line or adjacent capacitances C _DC on one divided counter electrode are currents flowing in opposite directions. And the loss currents tend to cancel each other.

For this reason, the loss current flowing through one gate line, drain bus line, and each counter electrode is extremely small, and the resistance of each wiring is reduced and the capacity of an external driver connected to each wiring is increased. It can provide a liquid crystal panel that does not need to be measured, and is suitable for increasing the capacity and definition of the liquid crystal panel. It should be noted that the present invention is not limited to the above embodiment, and various modifications can be made based on the gist of the present invention, and these are not excluded from the scope of the present invention.

[0065]

As described in detail above, the present invention
According to one gate bus line, a thin film transistor
The pixel electrodes connected through the gate bus line direction
Are arranged alternately in a zigzag pattern, and each counter electrode is
A gate is provided corresponding to each pixel electrode group arranged in the in-direction.
The pixel electrode group arranged in the bus line direction is connected to two gate bars.
The configuration is controlled by a line and one counter electrode.
V supplied to the counter electrode _COMTime to switch voltage
Voltage data supplied to the drain bus line
With different polarity on adjacent drain bus lines
The polarity is reversed every test line cycle, and the positive and negative polarities
The voltage data is supplied as mutually inverted voltage information
And a voltage signal supplied to each counter electrode is applied to each counter electrode.
Two gates connected to corresponding pixel electrodes via TFTs
Gate bus line selected first
Fluctuates in synchronization with the write timing of
Corresponds to the polarity data of the corresponding pixel electrode group and the liquid crystal threshold
Offset voltage and effective voltage correction voltage
The average effective voltage of the liquid crystal cell.
And switch of gate bus line and drain bus line
Low withstand voltage of the switching driver
You.

Further, this driving method is suitable for a large-capacity, high-definition display because the loss current generated by the wiring capacitance in the liquid crystal panel can be reduced. Furthermore,
This driving method has the same effect even when an analog voltage is input to the drain bus line, and therefore can be sufficiently applied to the gradation driving of the active matrix type thin film transistor liquid crystal panel.

Further, according to the present invention, a pixel electrode group connected to one gate bus line via a thin film transistor is arranged in the gate bus line direction, and two adjacent gate bus lines are connected via the TFT. In the pixel electrode group connected in a staggered manner alternately in the gate bus line direction.
A configuration in which one corrugated counter electrode is provided for a pixel electrode group selected from the gate bus lines, a circuit for switching the _VCOM voltage supplied to each corrugated counter electrode is provided, and a drain bus line is provided. The supplied voltage data is
The polarity is different between adjacent drain buses, the polarity is inverted every scan line cycle, and the positive and negative voltage data are supplied as mutually inverted voltage information, and the voltage signal supplied to each counter electrode is Of the two gate bus lines connected via a TFT to the pixel electrode corresponding to each counter electrode, the pixel voltage varies in synchronization with the write timing of the gate bus line selected first and corresponds to the pixel corresponding to each counter electrode. By supplying as a voltage signal including the polarity data of the electrode group and the offset voltage and the effective voltage correction voltage corresponding to the threshold voltage of the liquid crystal, the average effective voltage of the liquid crystal cell is made uniform and the switching driver for the gate bus line and the drain bus line is provided. Can achieve a low withstand voltage.

[Brief description of the drawings]

FIG. 1 is a schematic perspective view of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention.

FIG. 3 is a schematic block diagram of a data circuit of an active matrix thin film transistor liquid crystal panel according to an embodiment of the present invention.

FIG. 4 is a diagram showing timing of voltage data supplied to a drain bus of an active matrix type thin film transistor liquid crystal panel according to the embodiment of the present invention.

FIG. 5 is a schematic block diagram of a common variation circuit of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention.

FIG. 6 is a first operation timing chart of a common variation circuit of an active matrix type thin film transistor liquid crystal panel according to an embodiment of the present invention.

FIG. 7 is a second operation timing chart of the common variation circuit of the active matrix thin film transistor liquid crystal panel according to the embodiment of the present invention.

FIG. 8 is an equivalent circuit diagram of a liquid crystal cell of an active matrix thin film transistor liquid crystal panel according to an embodiment of the present invention.

FIG. 9 is an equivalent circuit diagram of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention.

FIG. 10 is a timing chart showing a drive voltage and a pixel voltage change of a thin film transistor connected to an odd drain bus according to the embodiment of the present invention.

FIG. 11 is a timing chart showing a driving voltage and a pixel voltage change of a thin film transistor connected to an even drain bus according to the embodiment of the present invention.

FIG. 12 is a schematic configuration diagram of an active matrix type thin film transistor liquid crystal panel showing another embodiment of the present invention.

FIG. 13 is a configuration diagram of a conventional active matrix type thin film transistor liquid crystal panel.

FIG. 14 is a diagram showing a drive timing chart of a conventional active matrix type thin film transistor liquid crystal panel.

FIG. 15 is a diagram showing electro-optical characteristics of a conventional TN liquid crystal cell.

FIG. 16 is a schematic perspective view of an active matrix type thin film transistor liquid crystal panel showing another embodiment of the present invention.

FIG. 17 is a diagram showing a configuration of a counter electrode of an active matrix thin film transistor liquid crystal panel according to an embodiment of the present invention.

FIG. 18 is a schematic configuration diagram of an active matrix thin film transistor liquid crystal panel according to another embodiment of the present invention.

FIG. 19 is a diagram showing timing of voltage data supplied to a drain bus of an active matrix thin film transistor liquid crystal panel according to another embodiment of the present invention.

FIG. 20 is a diagram showing a common variation circuit of an active matrix thin film transistor liquid crystal panel according to an embodiment of the present invention.

FIG. 21 is a diagram showing a first timing chart of a common variation circuit of an active matrix type thin film transistor liquid crystal panel according to another embodiment of the present invention.

FIG. 22 is a diagram showing a second timing chart of a common variation circuit of an active matrix thin film transistor liquid crystal panel according to another embodiment of the present invention.

FIG. 23 is a diagram showing a timing chart showing a drive voltage and a pixel voltage change of a TFT connected to an odd drain bus according to another embodiment of the present invention.

FIG. 24 is a diagram showing a timing chart showing changes in a drive voltage and a pixel voltage of a TFT connected to an even drain bus according to another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Gate bus line 12 Drain bus line 13 TFT 14 Pixel electrode 15 Counter electrode 15a Portion facing pixel electrode 15b Counter electrode junction 16 Liquid crystal 17 Auxiliary capacitance 18 Auxiliary capacitance line 19 Gap 20 Scanning circuit 30 Data circuit 31 Data generation unit 32 Data inverting section A 33 Data inverting section B 34 Data output section A 35 Data output section B 40 Common variation circuit 41 Shift register section A 42, 45 Voltage amplifying section 43 Driver section A 44 Shift register section B 46 Driver section B

────────────────────────────────────────────────── ─── Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI G09G 3/20 624 G09G 3/20 624C (72) Inventor Atsushi Takahashi 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Inside (72) Inventor Mio Chiba 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (56) References JP-A-2-7780 (JP, A) JP-A-5- 134629 (JP, A) JP-A-4-309926 (JP, A) JP-A-61-173290 (JP, A) JP-A-4-124616 (JP, A) JP-A-5-27710 (JP, A) JP-A-5-341729 (JP, A) JP-A-5-341730 (JP, A) JP-A-56-91275 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 3/00-3/38 G02F 1/133 505-580

Claims (5)

(57) [Claims] A gate bus line and a drain bus line which are orthogonally arranged on a rear substrate; a thin film transistor corresponding to each pixel electrode is provided at an intersection of the gate bus line and the drain bus line; Provided on the surfaces of the rear substrate and the front substrate, an alignment film oriented in an appropriate direction is provided, and the alignment films of both substrates are attached to each other via a liquid crystal layer so as to be bonded to each other. In a method of driving an active matrix type thin film transistor liquid crystal panel in which a polarizing film is attached to a back surface of a substrate and a front substrate, pixel electrodes connected to one gate bus line via a thin film transistor are alternately staggered in the gate bus line direction. Pixel electrodes in the gate bus line direction by a portion of the pixel electrodes corresponding to two adjacent gate bus lines. A group is formed, one counter electrode is provided for the pixel electrode group arranged in the gate bus line direction, a circuit for switching each counter electrode is provided, and the polarity of voltage data of adjacent drain bus lines is different, and one scanning line is provided. A voltage signal indicating a voltage in which the polarity of the voltage data is inverted in each cycle and the voltage data of the positive polarity and the negative polarity is inverted to each other is supplied to each drain bus line, and a pixel electrode corresponding to each counter electrode is provided. Fluctuates in synchronism with the write timing of the previously selected gate bus line in two adjacent gate bus lines connected via a thin film transistor to
And supplying a voltage signal including a polarity data of a pixel electrode group corresponding to each counter electrode, an offset voltage corresponding to a threshold voltage of the liquid crystal, and an effective voltage correction voltage to each counter electrode, and a selection signal to a gate bus line. A method for driving an active matrix type thin film transistor liquid crystal panel, wherein voltage writing is performed on each pixel electrode by the following method. 2. The active matrix type thin film transistor according to claim 1, wherein impedance components including capacitances C _DP1 and C _DP2 existing between said pixel electrode and an adjacent drain bus line are made equal to operate. How to drive a liquid crystal panel. 3. The active matrix thin film transistor according to claim 1, wherein an auxiliary capacitor _CS is provided electrically in parallel with the liquid crystal capacitor _CLC between the pixel electrode and the counter electrode to operate. How to drive a liquid crystal panel. 4. A gate bus line and a drain bus line which are orthogonally arranged on a rear substrate, thin film transistors are provided corresponding to respective pixel electrodes at intersections of the gate bus lines and the drain bus lines, and transparent on the front substrate. Provided on the surface of the rear substrate and the front substrate, an alignment film oriented in an appropriate direction is provided on the surfaces of the rear substrate and the front substrate, and the alignment films of the two substrates are arranged so as to face each other via a liquid crystal layer and bonded to each other. And a method of driving an active matrix type thin film transistor liquid crystal panel having a polarizing film attached to the back surface of the front substrate, wherein a group of pixel electrodes connected to one gate bus line via the thin film transistor is arranged in the gate bus line direction,
In a pixel electrode group connected to two adjacent gate bus lines via a thin film transistor, one wave shape is selected for a pixel electrode group selected from two lines alternately in a staggered manner in the gate bus line direction. the counter electrode is provided, each corrugated counter electrode provided a circuit for switching, different polarities of voltage data of adjacent drain bus lines, 1 inverts the polarity of the voltage data to the scan lines for each cycle, and the positive polarity and A voltage signal indicating a voltage obtained by inverting the voltage data of the negative polarity is supplied to each drain bus line, and two adjacent gate bus lines connected to a pixel electrode corresponding to each counter electrode via a thin film transistor. , The polarity data of the pixel electrode group corresponding to each counter electrode and the liquid crystal data which fluctuates in synchronization with the write timing of the gate bus line selected earlier. An active matrix, wherein a voltage signal including an offset voltage corresponding to a value voltage and an effective voltage correction voltage is supplied to each counter electrode, and a selection signal is supplied to a gate bus line to write a voltage to each pixel electrode. Method of driving a thin film transistor liquid crystal panel. 5. The active matrix type thin film transistor according to claim 4, wherein impedance components including capacitances C _DP1 and C _DP2 existing between said pixel electrode and an adjacent drain bus line are equalized and operated. How to drive a liquid crystal panel.