JP3185866B2 - Connectionless gateway device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a connectionless gateway device, and particularly to a large-scale ATM (Asyn) ATM device.
In a mode in which connectionless data communication such as the Internet is performed via a (Transfer Mode) backbone network, a user LAN (Local)
The present invention relates to a connectionless gateway device having a function of interconnecting an area network (Area Network) and an ATM backbone network.

[0002]

2. Description of the Related Art As a conventional method for interconnecting an existing LAN with an ATM network, an IPOA is used in an ATM forum.
(Internet Protocol Over AT
M) and LANE (LAN Emulation) have been proposed. The former (IPOA) is a method in which the network layer directly uses ATM, and the latter (LANE) is
This is a method in which the data link layer uses ATM. A method combining this conventional method is disclosed in, for example, JP-A-09-00.
No. 8838. The method and apparatus described in this publication interconnect an existing LAN with an ATM network via an ATM router or server.

FIG. 13 is a block diagram showing a configuration of a conventional server device 1001 for interconnecting a LAN and an ATM network. The configuration and operation of the conventional server device 1001 will be described with reference to FIG.

A conventional server device 1001 comprises a central processing unit (CPU) 1002, an interface port 10
03, a data bus 1004, and a memory 1005. The CPU 1002 is a server device 1001
It has all the computational capabilities necessary for the control processing.
The data bus 1004 exchanges data between blocks in the server device 1001. The interface port 1003 is connected to a client device via a high-speed backbone link 1008, and performs transmission / reception processing of packet data by a built-in data transceiver. The memory 1005 includes a code unit 1006, which is a program area used by the CPU 1002 for server control, and a data memory unit 1007 including an address table and the like required for performing a server device specific function. . The standard packet transfer operation in the conventional method is performed in the following procedure. (1) Packet data is received by a data transceiver mounted in the interface port 1003. (2) The packet data is transferred to the data memory unit 1007, which is the main storage memory of the CPU 1002. (3) The CPU 1002 performs a read / write process on the memory 1005 to search the address table (interpret the message). (4) The packet data is transferred to the data transceiver mounted in the interface port 1003.

[0005] Using this conventional server device 1001, L
The first problem when the AN and the ATM network are interconnected is that the architecture of the existing interconnecting device is based on the following three schemes. (1) Shared-bus method (2) Maintenance of cache-base table (3) Centralized processing by a single CPU The architecture of existing interconnection devices sharing bus capacity, cache capacity, CPU resources, etc. is simple. In a stable network environment, the performance can be kept constant. However, under a large-scale network having a wide address space, it is expected that the ratio of the cache hit rate held as a routing table will decrease. As a result, there is a risk that the bus capacity or the CPU capacity is wasted and the performance is degraded.

In the conventional method as described above, when a datagram from a user LAN is transferred to an ATM backbone network, the datagram is once assembled into packets and search processing is performed by software. There is a disadvantage that can not respond to.

A second problem of the conventional method shown in FIG. 13 is that it becomes a bus neck in the apparatus. In the above-described conventional data transfer procedure, packet data passes twice on the data bus in one data transfer. For example, if the capacity of one interface port is 10
Assuming that there are 0 Mbps × 4 ports, the bus bandwidth required for data transfer is 100 Mbps for both uplink and downlink.
s × 2 (direction) × 4 (port) = 800 Mbps,
800 Mbps × 2 = 1.6 G because the data bus is used twice in writing / reading to / from the data memory.
A bps band is required. A general-purpose peripheral interconnect bus (PCI bus) as a high-speed bus is 32 (or 64)
It is a local bus system that can transfer bits at a rate of 33 MHz (or 66 MHz).
The capacity of the PCI bus of (bit × 33 MHz = 1.56 Gbps) is exceeded, so that the bus speed required for packet transfer cannot be obtained and the throughput is reduced.

FIG. 14 is an operation conceptual diagram showing a packet transfer process of an existing IP router.

The connectionless network shown in FIG. 14 has a routing information collection system 1407 and a main signal data transfer system 14.
06 will be described separately. In this connectionless network, a plurality of IP routers 1401 are provided to establish a connection with the user LAN 205. User LAN2
05 is connected to a connectionless network via an IP router 1401, and is connected to another user LAN 205 via a plurality of IP routers 1401.
Exchanges data with the user terminal 208 connected to the.

[0010] As shown in FIG.
Since the different layers of the routing information collection system 1407 and the main signal data transfer system 1406 are simultaneously performed by software processing, speeding up and capacity increase are limited, and the present invention can be directly applied to a large-scale backbone network. Have difficulty.

[0011]

The above-mentioned conventional connectionless gateway apparatus has the following problems. (1) When transferring from the user LAN to the ATM backbone network, high-speed transfer cannot be performed because the packet is once assembled and the search processing is performed by software. (2) Since the packet data passes twice on the data bus in one data transfer, the capacity of the bus is exceeded and the bus becomes a bottleneck, and the throughput is reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a connectionless gateway device capable of greatly reducing the transfer processing time and enabling effective use of the internal bus bandwidth.

[0013]

In order to achieve the above object, a connectionless gateway device according to the present invention comprises:
An ATM connectionless data communication network for transferring data in a connectionless manner via a TM network and a user L
In a connectionless gateway device for interconnecting an AN, a plurality of interface units for controlling a packet input / output interface with the user LAN, and a cell received from each of the interface units,
/ VCI for switching according to VCI;
Collecting reachability information in the connectionless network,
A connectionless control unit having a function of downloading to each of the interface units; and a plurality of transmission / reception units for controlling an input / output interface with the connectionless network.

According to the present invention, since the connectionless control unit, which is a server, is provided in the connectionless gateway device, it is possible to suppress an address resolution packet inquiry / response to a transfer delay in the device.

Further, connectionless gateway device of the present invention, each interface unit, SAR performing cell reduction and disassembling processing for the connectionless network
A processing circuit; a main CPU connected to the first PCI bus for performing layer 3 protocol processing required for data transfer in the connectionless network;
A sub CPU that is connected to a bus and controls the SAR processing circuit; and is connected to the first PCI bus and the second PCI bus, respectively, and stores a head address and packet length information for writing packet data as a command. Dual port memory, the main CPU and the sub C
An interrupt generating means for notifying the other party of the completion of the processing between the PUs by an interrupt, and a layer 2 without intervening the processing by the main CPU.
A bridge processing circuit that performs a bridge transfer in which only an address is referred to, a memory for storing an address resolution table, and a connection from the user LAN to the connectionless network using the address resolution table stored in the memory. CLARP processing for resolving a CL address from an IPv4 address when performing data transfer, and I for resolving a MAC address from an IPv4 address when performing data transfer from the connectionless network to the user LAN.
An address search circuit for performing P-ARP processing.

The present invention provides processing of the layer 3 protocol and S
AR control processing is divided and each processing is performed by two independent CPUs.
And an interrupt generating means for notifying the completion of the process by an interrupt between the main CPU and the sub CPU, and the respective CPUs are connected by the first and second PCI buses via the dual port memory. It is something to do.

Therefore, it is possible to avoid using the bus twice in one packet transfer procedure, and it is possible to effectively use the bus bandwidth in the device.

According to an embodiment of the present invention, an ATM is provided.
The connectionless gateway device is configured by mounting the connectionless control unit and the interface unit separately on the interface board of the cross-connect device as in-device servers.

According to the present invention, a connectionless gateway device is configured by mounting a connection control unit and an interface unit in the form of an interface board in an ATM cross-connect device.

Therefore, versatility to a large-scale switch is expected, and this switch resource can be used and add-on can be performed at low cost.

According to another embodiment of the present invention, the dual port memory defines a command definition area for defining commands from the main CPU to the sub CPU and a command definition area for defining commands from the sub CPU to the main CPU. The area is divided into four areas, a command definition area for storing the data packet in the CLA processing direction, and an area for storing the data packet in the CLD processing direction. There is further provided means for writing a packet in each area.

According to another embodiment of the present invention, the address resolution table stored in the memory uses a node number as index information, and stores a flag corresponding to an address to be resolved and a resolution address entry. Path table having pointers of C and C as a component, a CL address table, and a C managing the correspondence between the actual CL address and the VPI value.
It comprises an L / VPI correspondence table and an IP-ARP table for storing a MAC address.

Further, according to another embodiment of the present invention, the interrupt generation means determines that the main CPU and the sub CPU turn on an arbitrary bit to notify each other that the processing has been completed. This is an I / O register that generates an interrupt for notification.

[0024]

FIG. 1 is a system diagram showing a configuration of a connectionless network having a connectionless gateway device according to an embodiment of the present invention.

A feature of the connectionless network in this embodiment is that the processing of the main signal data transfer system 206 and the processing of the routing information collection system 207 are performed independently. The connectionless network is interconnected with, for example, a user LAN 205 represented by an existing Ethernet, and a CLAD that accommodates user packets in ATM cells.
(Cell Assembly and Disassembly
The network includes a connectionless gateway device 201 which is an edge device that performs an EMBLY process, and a connectionless conversion node 202 that is a network device that performs a relay transfer process in the network at an ATM cell level. Permanent connection (PVC: Perman) between the adjacent connectionless conversion node 202 and the connectionless gateway device 210 and between the connectionless conversion nodes 202.
ent Virtual Connection).

Destination IP (Internet Proto)
col) address to the destination CL (Connection)
Less) In order to resolve the address, an address resolution server 203 (ARS: Add) is provided in the connectionless network.
less Resolution Server). Further, a connectionless control unit 204 for functioning as an address resolution server is provided in the connectionless gateway device 201. Each connectionless gateway device 201
Is not only the IP address of the user LAN 205 connected to itself, but also the IP address of the user LAN 205 connected to another connectionless gateway apparatus 201.
Since it is necessary to know the P address, a plurality of address resolution servers 203 are installed in the connectionless network.
Between the address resolution servers 203 or between the address resolution server 203 and the connectionless control unit 20
Exchange reachability information between the four.

Connectionless control unit 204
Has a function of periodically downloading the collected reachability information to the connectionless gateway device 201, and has a function of maintaining and managing an address table of the connectionless gateway device 201. When a new packet arrives from the user LAN 205 connected to the connectionless gateway apparatus 201, the connectionless gateway apparatus 201 closes the CL corresponding to the destination IP address of the packet.
The address is resolved by referring to the address resolution table of the connectionless gateway device 201 itself. If the connection cannot be resolved, an inquiry about address resolution is made to the connectionless control unit 204 functioning as an address resolution server in the connectionless gateway device 201. Upon receiving this inquiry, the connectionless control unit 204 responds with the result of address resolution according to the request from the connectionless gateway device 201. By providing the connectionless control unit 204, which is a server, in the connectionless gateway device 201, it is possible to suppress an address resolution packet inquiry / response to a transfer delay in the device.

FIG. 2 is a block diagram showing the configuration of the connectionless gateway device 201 in FIG.

This connectionless gateway device 2
01 are interface units 301a to 301a functioning as a packet input / output interface unit with the user LAN 205.
301c, a cell switch unit 302 for switching cells received from the interface units 301a to 301c in accordance with the VPI / VCI, and collecting reachability information in the connectionless network, creating a routing table, and forming each of the interface units 301a to 301c. Connectionless control unit 20 having the function of downloading to
4 and transmission / reception units 304a to 304c functioning as input / output interface units for connectionless networks.

The connection between the interface units 301a to 301c and the connectionless control unit 204
Fixed VP (Virtual Path) in the device
(PVC) connection. Also, the interface unit 301a
The connectionless gateway device can be configured by mounting the .about.310c and the connectionless control unit 204 on the ATM cross-connect device in the form of an interface board. By configuring the connectionless gateway device in this manner, versatility to a large-scale switch is expected, and this switch resource can be used and add-on can be performed at low cost.

Next, the interface units 301a-301
The configuration of c will be described. FIG. 3 is a block diagram showing a configuration of the interface units 301a to 301c.

Interface faces 301a-30
1c denotes an IF (Interface) port 101a, 101b and a bridge processing circuit 102, respectively.
, Bus bridge circuits 103 and 112, and main CPU
104, an I / O register 105, an address search circuit 106, and a dual port memory (DPM: DualP
ort Memory) 107 and memories 108 and 11
0, the sub CPU 111, and the SAR (Segmenta
Tion And Reassembly) Processing Circuit 1
13a and 113b and a cell multiplexing / demultiplexing circuit 114.

The interface units 301a to 301c
A CPU (upper instruction unit) that controls the entire system based on a program is composed of a main CPU 104 and a sub CPU
There are 11 systems. The main CPU 104
Layer 3 protocol processing mainly required for connectionless intra-network transfer and MAC (Media Accesses)
s Control) Frame termination processing is performed. On the other hand, the sub CPU 111 includes SAR processing circuits 113a and 113
b is controlled. These two CPUs 104, 111
This is a connection via the DPM 107, and stores a start address of the DPM 107 to which packet data is written and packet length information as a command at the time of packet data transfer. In addition, both CPUs 104 and 111 have a procedure of notifying the completion of the processing by an interrupt signal.

The bridge processing circuit 102 and the SAR processing circuits 113a and 113b
5, 116. PCI bus 115, 11
6 each have a bus capacity of 32 bits × 33 MHz,
The host bus 1 via the bus bridge circuits 103 and 112
17 and 118 are connected. Here, the bus bridge circuits 103 and 112 have a function of converting data formats between the host buses 117 and 118 and the PCI buses 115 and 116. The two IF ports 101a and 101b function as a packet transmission / reception interface from the user LAN. Each of the IF ports 101a and 101b is connected to the bridge processing circuit 1.
02 is connected. The bridge processing circuit 102
It has a function of performing bridge transfer by referring only to the layer 2 address between NIs (User Network Interfaces). SAR processing circuit 113a,
113b is an NNI (Network-to-Network)
or a cell multiplexing / demultiplexing circuit 114.
Is connected to

The role sharing between the CPUs 104 and 111 and each functional block will be described below. Main C
The bridge processing circuit 102 is connected to the PCI bus 115 on the PU 104 side. Bridge processing circuit 102
Temporarily stores the MAC frame received from the user LAN 205, extracts the MAC address inside the bridge processing circuit 102 during that time, and stores the source MAC address (SA
MAC) as a key to store an output interface port number, and an autonomous address learning function, and a function to acquire an output interface port number using a destination MAC address (DA MAC) as a key and transfer it to the corresponding interface. . As described above, the bridge transfer performed by referring only to the layer 2 address is as follows.
Bridge processing circuit 102 without CPU processing
Only processed within. On the other hand, the transmission processing to the connectionless network side requiring the layer 3 processing is transferred to the DPM 107 on the host bus 117 via the bus bridge circuit 103, and the intermediate frame is constructed by the address resolution processing performed by the main CPU 104 thereafter. .

The SAR processing circuits 113a and 113b are connected to the PCI bus 116 on the sub CPU 111 side. The SAR processing circuits 113a and 113b
It has a function to convert the intermediate frame constructed by U104 into a cell and decelerate it by AAL-type 5. DPM
A segmentation function of accommodating packet data (intermediate frame) stored in the ATM cell 107 in a 48-byte fixed-length ATM cell payload portion, and an AT received from the network side.
It has a reassembling function of identifying the same packet by the cell label (VPI / VCI) of the M cell and reconstructing it into the original packet data (intermediate frame).

Each of the CPUs 104 and 111 generates an interrupt signal for notifying that the processing is completed.
By turning on any bit of.

The feature of the main signal data transfer system 206 in the connectionless network of this embodiment is that the protocol processing required for the transfer within the connectionless network is integrated in the connectionless gateway device 201 and the processing load of the connectionless conversion node 202 is processed. Is significantly reduced. The main signal transfer operation in this connectionless network will be described with reference to FIG.

FIG. 4 is an operation conceptual diagram for explaining a main signal transfer operation of a connectionless network using the connectionless gateway device 201 of the present embodiment.

In the connectionless intra-network transfer operation in the present embodiment shown in FIG.
The connectionless gateway device 201, which is considered to be smaller in size than that of the second embodiment, concentrates the protocol processing, and the connectionless conversion node 202 does not perform software processing. Connect dynamically. As a result,
As compared with FIG. 14, the transfer operation in the connectionless network is performed cell-by-byte from the head cell regardless of the flow type.
Cell transfer (so-called cut-through transfer) can be performed, and high speed and large capacity can be achieved.

FIG. 5 shows an encapsulation process when the connectionless gateway device 201 transmits to the connectionless network.

The connectionless gateway device 201
Now, the IPv4 frame 6 received from the user LAN 205
01 is an IPv6 frame 602 which is an intermediate frame.
Housed in The header portion of the IPv6 frame 602 includes a source connectionless gateway device number (SACL) and a destination connectionless gateway device number (DACL) used as transfer information in the connectionless network. Further, by adding an AAL type 5 header and trailer to the IPv6 frame 602, C
PCS-PDU (Common Part Conver
gence Sublayer-Protocol D
ata Unit) frame 603 is generated. Furthermore, AAL's SAR (Segmentation an
d Reassembly sublayer) processing to convert the CPCS-PDU frame 603 into the ATM cell 6
04. Same CPCS-PDU frame 603
Are assigned to the same virtual channel identifier VCI (Virtual Channel).
Identifier), and transfer to the connectionless network side without disrupting the cell order. In the case where the header of the IPv6 frame 602 is a normal 40 byte and is cellized by AAL type 5, the source connectionless gateway device number (SACL) used as the transfer information in the connectionless network and the destination connectionless gateway The device number (DACL) is the first (BO
M: Beginning Of Memory). Similarly, the COM cell and the EOM cell respectively indicate an intermediate (Center Of Memory) cell and an end (End Of Memory) cell.

Connectionless gateway device 201
In the packet transmission / reception flow, there are two types of address resolution processing in the above. One is a CLARP (Connection Less Ad) for resolving a CL address from an IPv4 address in a connectionless gateway device provided at an entrance to a connectionless network.
dress Resolution Protocol
l) Processing, and the other is IP-ARP (IP-Mac Address Res) for resolving a MAC address from an IPv4 address in a connectionless gateway device provided at an exit from a connectionless network.
solution processing). Both address resolution tables are collectively stored in the memory 108 directly connected to the address search circuit 106.

Next, the relationship between the address resolution tables will be described with reference to FIG.

The address resolution table is a route table 1
101, CL address table 1102, CL · V
PI correspondence table 1103 and IP-ARP table 1
104.

The route table 1101 is a tree table created by using the minimum tree algorithm. The node table is used as index information, and the address to be solved is CL.
Address or next hop (N (Next) HO
P) An address or a MAC address is identified by a flag, and a table for actually managing the address to be solved is accessed using a pointer.

Next, the components of each table will be described. The route table 1101 has, as constituent elements, a flag corresponding to the address to be resolved and a pointer to the address entry to be resolved. If the flag of the routing table 1101 is a CL address, the routing table 1101
Pointer indicates the storage location of the CL address table 1102, and the V
By using the PI pointer, the CL / VPI correspondence table 1103 for managing the correspondence between the actual CL address and the VPI value is accessed, and the CL address and the VPI to be solved are acquired. At this time, if the CL address cannot be obtained, the CL address request packet is transmitted to the connectionless control unit 204 with the CL address and the VPI value indicated as the default path.

When the flag of the routing table 1101 is a MAC address, the pointer of the routing table 1101 points to the storage location of the MAC address in the IP-ARP table 1104 and directly obtains the real MAC address. If the flag of the route table 1101 is the NHOP address, the pointer of the route table 1101 points to the pointer position of the MAC route entry in the route table 1101, and the actual MAC address is acquired by referring to the chained pointer thereafter. CL / VPI correspondence table 1103 in which actual entries are stored, and IP-ARP table 110
No. 4 has a link pointer for each entry, and the position of the next entry is indicated in the form of a linked list by the link pointer.

Next, the operation of the present embodiment will be described in detail with reference to the drawings.

FIG. 7 illustrates the operation of the interface units 301a to 301c in FIG. 3 for each block in order to explain the operation of the connectionless gateway device 201 of the present embodiment. FIG. 8 shows packet processing (hereinafter CLA processing: CellA) when the connectionless gateway device 201 transmits to the connectionless network.
FIG. 9 is a flowchart showing a packet processing (hereinafter, CLD processing: Cell DeathMbly) process when the connectionless gateway device receives data from the connectionless network. FIG.
9 is a flowchart illustrating the operation of the address search circuit 106 when an RP packet is received.

Referring to FIGS. 7, 8, 9 and 10, bridge processing circuit 102 and SAR processing circuit 113
The processing flow at the time of packet transmission / reception between a and 113b will be described in detail.

The connectionless gateway device 201
The packets handled by are for main signal packet and address resolution
(ARP) packets are roughly classified into two types. The frame data transfer direction is classified into the CLA side and the CLD side. In the address search circuit 106, the process branches depending on the determination of the solution / unsolved. Therefore, the following eight combinations are conceivable as transfer flow combinations. (1) CLA side main signal processing flow (CL address resolution) (2) CLA side main signal processing flow (CL address unresolved) (3) CLD side main signal processing flow (MAC address resolution) (4) CLD Side main signal processing flow (when MAC address is unresolved) (5) IP-ARP packet reception flow (when holding packet MAC address is resolved) (6) IP-ARP packet reception flow (request M
(7) IP-ARP packet reception flow (when holding packet is unresolved and replay packet is not generated) (8) CLARP packet (replay) reception flow For the above processing flow, refer to FIG. Will be explained. First, the process (CLA process flow) of receiving a MAC frame, passing through an intermediate frame construction process, and converting it into a cell will be described.

Here, the MAC frame terminator 402, I
The Pv4 frame termination unit 403, the IPv6 frame generation unit 404, the IPv6 frame termination unit 410, the IPv4 frame reconstruction unit 411, and the MAC frame generation unit 412
The processing in the main CPU 104 or the sub CPU 111 is shown as a block.

The cell processing section 407 and the decell processing section 408 include SAR processing sections 113a and 113b, respectively.
Is a block diagram of the processing in FIG.

Upon receiving the MAC frame from the bridge processing circuit 102, the main CPU 104 checks the type field in the MAC frame terminating unit 402,
It identifies whether the received data packet is a main signal packet, an address resolution packet, or an invalid packet.
If the received packet is a main signal IPv4 frame, the IP
After the normality of the frame is checked by the v4 frame termination unit 403, the frame is passed to the IPv6 frame generation unit 404. In the IPv6 frame generation unit 404, the IPv4
The destination IP address in the frame header is transferred to the address search circuit 106, and the address search circuit 106 searches the address resolution table stored in the memory 108, thereby obtaining the destination CL address from the transferred destination IPv4 address. get. Thereafter, in the IPv6 frame generation unit 404, the acquired CL address is
The sub CPU 111 is accommodated in the header of the Pv6 frame, and
To the effect that processing has been completed. In this address resolution process, if the CL address is
If it does not exist in the entry of the address resolution table stored in 08 (case 2), the unresolved frame is held, and the address search circuit 106 causes the CLARP
A request (address resolution request) packet is created and transmitted to the CL address resolution unit in the device.

Next, a process (CLD process flow) for receiving an ATM cell from the connectionless network side, constructing a MAC frame through a decellularization process, and an IPv6 frame termination process will be described.

In the decellularization processing unit 408, one C
When the PCS-PDU frame restructuring process is completed, the sub CPU 111 notifies the main CPU 104 of the process completion by interruption. By this notification, the main CP
U104 learns that it has received an IPv6 frame,
Whether the received data packet is a main signal packet, an address resolution packet,
Alternatively, it identifies an unknown packet that is neither of them.

When the received packet is a main signal frame,
After the IPv4 header is reconstructed by the IPv4 frame reconstruction unit 411, the IPv4 header is passed to the MAC frame generation unit 412. The MAC frame generation unit 412 transfers the destination IPv4 address to the address search circuit 106, and in the address search circuit 106, searches the address resolution table using the destination IP address as a key to obtain the MAC address to be the next-stage transfer destination I do. Then, the MAC frame generation unit 412 constructs a MAC frame having the obtained MAC address as a header, transfers the MAC frame to the bridge processing unit circuit 102, and notifies the sub CPU 111 of the completion of the transfer process by interruption. I do. In this address resolution process, if the MAC address does not exist in the entry of the address resolution table (Case 4), the unresolved frame is held, and the IP-ARP request (address resolution request) packet is stored in the address search circuit 106. And broadcast-transfer it in the bridge processing unit.

FIGS. 8, 9 and 10 show flowcharts for processing data packets in the system shown in FIG. FIGS. 8, 9, and 10 include a process of performing address resolution and a process of transferring a data packet to a designated address in the present embodiment.

First, the CLA processing flow will be described with reference to FIG. The CLA processing is started from the bridge processing in the bridge processing circuit 102 (step 701). When the MAC frame is received (step 702), the type field is determined, and it is determined whether the received MAC frame is a packet for address resolution, a main signal packet, or an unknown packet. (Step 705). Step 705
If it is determined that the received packet is an IP-ARP (address resolution) packet, after receiving the IP-ARP packet (step 707), the process proceeds to a process described later with reference to FIG. If the result of the determination in step 705 indicates that the packet is a main signal IP packet, CL
The processing is passed to the address resolution processing (step 718). If it is determined in step 705 that the packet is an unknown packet, the packet is discarded (step 706), the DPM 107 is released (step 704), and the process ends.

CL address resolution processing step (718)
Is composed of steps 709 to 713. First, DA IP (Destination IPv4)
Address) is extracted (step 709), and an address resolution (ARP) table is searched (step 710).
DACL (Destinati) corresponding to DA IP
on CLAddress) is registered in the address resolution table (step 71).
1). If the determination result in step 711 is affirmative, the CPU exits the CL address resolution processing (step 718) and executes the IPv6 frame construction processing (step 714). If the determination result in step 711 is negative and “the packet is unresolved” is indicated, the unresolved packet is held (step 71).
2) Generate and transfer a CL address resolution request (step 713).

When the intermediate frame construction processing in step 714 is completed, the sub CPU
Passed to 19. After transmitting the interrupt notification to the sub CPU 111 (step 715), under the control of the sub CPU 111, the SAR processing circuits 113a and 113b perform cell processing (step 717), and transmit a packet processing completion notification (step 716). After the memory release processing, the process ends (step 704).

Next, the CLD processing flow will be described with reference to FIG. The basic CLD processing flow is the same as the CLA flow in FIG. The only difference between the two processing flows is that in the CLA processing flow, the address to be solved is the CL address, whereas the address to be solved in the CLD processing flow is the MAC address.

In the CLD processing, first, the SAR processing circuits 113a and 113b use the SAR processing circuits 113a and 113b as triggers when the main CPU 104 receives an interrupt notification from the sub CPU 111.
The AR processing is started (step 801). And I
A Pv6 frame is received (step 802), the type field is checked, and the received IPv6 frame is checked.
It is determined whether the frame is a packet for address resolution, a main signal packet, or an unknown packet (step 804). In the connectionless gateway device 201, since the CL address resolution request is not transferred from the connectionless network side,
ARP replay reception, address resolution waiting packet
The process is performed by determining the presence / absence of (hold packet). If the result of the determination in step 804 indicates that the packet is a main signal IP packet, it is passed to the MAC address resolution processing (step 817). If it is determined in step 804 that the packet is an unknown packet, the packet is discarded (step 805), and the DPM 107
Is released, the process ends (step 803).

MAC address resolution processing (step 81)
7) is composed of steps 808 to 812.
First, DA IP (Destination IPv4)
Address) is extracted (step 808), and an address resolution (ARP) table is searched (step 8).
09) As a result, it is determined whether or not the MAC address corresponding to the DA IP is registered in the address table (step 810). If the determination result in step 810 is affirmative, the process exits the MAC address solution processing step 817 and the MAC frame construction processing is performed (step 813). If the determination result in step 810 is negative and the packet indicates that the address is unresolved, the unresolved packet is held (step 811), and a MAC address resolution request is generated.
Transfer (step 812).

When the MAC frame construction processing in step 813 is completed, the processing shifts to the processing for exchange with the bridge processing circuit 102 (step 818). Then, a packet processing completion notification is sent to the bridge processing circuit 102, and after releasing the memory (step 803),
The process ends.

Next, a process of processing a received address resolution packet will be described with reference to FIG. First. When an address resolution packet is received (step 901), it is determined whether or not the address resolution packet is invalid (step 902). If the determination result in step 902 is an error, the packet is discarded, and the process ends (step 903). If the determination result in step 902 is normal, regardless of whether the address resolution packet is a request or a replay,
A search is made as to whether a set of the source IP address and the source MAC address exists as an entry in the address resolution table (step 904). If the search result in step 904 is positive (hit), the aging timer is reset and the expiration date for the entry is updated (step 907). If the search result in step 904 is negative (no hit), it is determined whether the target IP address to be addressed is its own IP address (step 905). If the result is affirmative, the address resolution table is determined. Is newly registered (step 906).

After the processing of steps 906 and 907, it is determined whether or not there is a held packet (step 908).
If there is a held packet in the waiting state for address resolution, the held packet is transferred (step 90).
9). If the result is negative in step 908, it is determined whether the received address resolution packet is an ARP request packet (step 910). If the determination in step 910 is negative, the packet is discarded, and the process ends (step 911). If the determination result in step 910 is affirmative, it is determined whether or not the packet whose address is to be resolved is its own IP address (step 912).
If it is an address, an ARP replay packet is generated (step 915), the memory of the ARP packet is released (step 917), and the packet is transferred to the user network (step 918).

If the packet whose address is to be resolved is not its own IP address in step 912, the ARP table is searched with the target IP (step 91).
3) If the search result is negative (no hit), the packet is discarded and the process ends (step 914).
If the search result in step 913 is positive (hit), an ARP replay packet is created (step 91).
6) After releasing the memory of the ARP packet (step 917), the packet is transferred to the user network (step 9).
18).

Next, referring to FIG. 11 and FIG. 12, the CPU in the connectionless gateway device of the present embodiment will be described.
The inter-communication processing flow will be described. FIG. 11 shows the DPM
FIG. 1 is an explanatory diagram showing the configuration of FIG.
2 is a flowchart showing a communication process between CPUs.

The connectionless gateway device 201
As shown in FIG. 3, the main CPU 104, which is a master CPU for performing basic processing, and the SAR processing circuits 113a, 113a,
And a sub CPU 111 that performs only the control processing of the sub-CPU 13b. The interface between the two CPUs 104 and 111 includes an interrupt line 1201 and a DPM 107.
And the master CPU 104 as a master.
Thus, the sub CPU 111 performing the control processing of the SAR processing circuits 113a and 113b appears as a kind of communication device.

The inside of the DPM 107 includes the following 4
Is divided into two areas. (1) Command definition area from the main CPU 104 to the sub CPU 111 (1202) (2) Command definition area from the sub CPU 111 to the main CPU 104 (1203) (3) Area for storing data packets in the CLA processing direction (1204) (4) CLD Area for storing data packets in the processing direction (1205) This command definition area 1202 is
, A command storage area for the sub CPU 111 and a reply command area for the main CPU 104 from the sub CPU 111. Similarly, the command definition area 1203 indicates that the sub CPU 111
Command storage area for U104 and main CPU
An area from 104 for a reply command to the sub CPU 111 is included.

Next, referring to FIG.
A communication procedure between the CPU 04 and the sub CPU 111 will be described.

Here, the sub CPU C
Description will be made using a case where a command is issued to the PU 111.

First, the main CPU 1 on the command issuing side
04 writes information such as the start address indicating the packet head position and the packet length in the command definition area 1202 of the DPM 107 (step 1301). Next, the main CPU 1
04 activates an interrupt by setting an arbitrary bit of the I / O register 105 (step 1302),
At the same time, timeout monitoring is performed for a period until a response interrupt is received from the sub CPU 111 on the command receiving side (step 1303). Main CPU 104
For commands that do not have a reply within a predetermined time,
The processing related to the command is invalidated, and the data packet stored in the packet storage area (CLA side) 1204 is discarded.

Then, upon receiving the interrupt from the main CPU 104, the sub CPU 111 jumps to interrupt processing (step 1304), and the command definition area 120
The packet in the packet storage area (CLA side) 1204 is read based on the start address and the packet length written in 2 (step 1305). After that, the sub CPU 111
An instruction is given to the SAR processing circuits 113a and 113b to frame the AAL type 5 and to transfer the data to a cell on the specified VPI of the specified port (step 130).
6). One packet is written in a continuous area in the DPM 107. When the transfer processing for one packet is completed, the reply content indicating that the packet storage area (CLA side) 1204 is released is written in the command definition area 1202 (step 1307). And the sub CPU
The 111 activates an interrupt by setting an arbitrary bit of the I / O register 105 (step 130).
8).

Then, the main CPU 104 sets the sub CP
Upon receiving an interrupt from U111 (step 130)
9) Jump to interrupt processing (step 131)
0), the reply command of the DPM 107 is read, and the packet storage area (CLA side) 1204 is released (step 1311).

In step 1303, if there is no reply and time-out occurs, no interrupt is received (step 1312), and the main CPU 104 determines that the packet is abnormal and performs processing for canceling the processing for the command (step 1313).

[0079]

As described above, the present invention has the following effects. (1) Since the connectionless control unit, which is a server, is provided in the connectionless gateway device, it is possible to suppress an address resolution packet inquiry / response to a transfer delay in the device. (2) In a connectionless network that is overlaid on an ATM-VP network, versatility to a large-scale switch is expected by mounting it in the form of an interface board on an ATM cross-connect device, and this switch resource can be used. It can be added at low cost. (3) Layer 3 processing and SAR control processing are divided, each processing is executed by two independent CPUs, each has a sequence of notifying by an interrupt, and both CPUs are connected via a dual port memory. (1) It is possible to avoid using the bus twice in one packet transfer procedure, and it is possible to effectively use the bus bandwidth in the device.

[Brief description of the drawings]

FIG. 1 is a system diagram showing a configuration of a connectionless network having a connectionless gateway device according to an embodiment of the present invention.

FIG. 2 is a connectionless gateway device 2 in FIG.
FIG. 1 is a block diagram showing a configuration of the first embodiment.

FIG. 3 shows interface units 301a to 301c in FIG.
FIG. 2 is a block diagram showing the configuration of FIG.

FIG. 4 is an operation conceptual diagram showing a transfer process by a connectionless gateway device 201 and a connectionless conversion node 202;

FIG. 5 shows an encapsulation process when the connectionless gateway device 201 transmits to a connectionless network.

FIG. 6 is a diagram showing a structure of an address resolution table.

FIG. 7 is a functional block diagram for explaining an operation of the interface unit of FIG. 1;

FIG. 8 is a flowchart for explaining a CLA process;

FIG. 9 is a flowchart illustrating a CLD process.

FIG. 10 is a flowchart showing an operation of the address search circuit 106 when receiving an ARP packet.

FIG. 11 is a diagram showing a configuration of the DPM 107 and a region division.

FIG. 12 is a flowchart illustrating a communication process between CPUs.

FIG. 13 is a block diagram showing a configuration of a conventional connectionless gateway device.

FIG. 14 is an operation conceptual diagram showing a packet transfer process of an existing IP router.

[Explanation of symbols]

 101a, 101b Interface (IF) port 102 Bridge processing circuit 103 Bus bridge circuit 104 Main CPU 105 I / O register 106 Address search circuit 107 Dual port memory (DPM) 108, 110 Memory 111 Sub CPU 112 Bus bridge circuit 113a, 113b SAR Processing circuit 114 Cell multiplexing / demultiplexing circuit 201 Connectionless gateway device 202 Connectionless conversion node 203 Address resolution server 204 Connectionless control unit 205 User LAN 206 Main signal data transfer system 207 Routing information collection system 208 User terminals 301a to 301c Interface unit 302 Cell switch unit 304a-304c Transmission / reception unit 402 MAC frame termination unit 403 IPv 4 frame termination unit 404 IPv6 frame generation unit 407 cell processing unit 408 decell processing unit 410 IPv6 frame termination unit 411 IPv4 frame restructuring unit 412 MAC frame generation unit 413 in-device interface unit 601 IPv4 frame 602 IPv6 frame 603 CPCS-PDU Frame 604 ATM cell 701 to 719 Step 801 to 816 Step 901 to 918 Step 1001 Server device 1002 CPU 1003 Interface port 1004 Data bus 1005 Memory 1006 Code section 1007 Data memory section 1008 Backbone link 1101 Route table 1102 CL address table 1103 CL / VPI Correspondence table 1104 IP-ARP table 1201 Interrupt 1202 and 1203 the command definition area 1204 packet storage area (CLA side) 1205 packet storage area (CLD side) 1301 to 1313 step 1401 IP router 1406 main signal data transfer system 1407 routing information acquisition system

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 12/28 H04L 12/46 H04L 12/56 H04L 12/66

Claims (4)

(57) [Claims] 1. A connectionless gateway device for interconnecting an ATM connectionless data communication network for performing data transfer by a connectionless method via an ATM network and a user LAN, wherein a packet input / output interface with the user LAN is provided. A plurality of interface units to be controlled, and a cell received from each of the interface units being VPI / V
A cell switch unit that switches according to CI, and collects reachability information in the connectionless network;
A connectionless control unit having a function of downloading the each interface unit, have a plurality of transmitting and receiving unit for controlling the input and output interface with the connectionless network, input and output interface to the packet with the user LAN
A plurality of interface units for controlling the connectionless network into a cell / decell process
A SAR processing circuit for performing the connection and the connectionless network connected to a first PCI bus.
Layer 3 protocol required for data transfer in a network
A main CPU that performs processing, and a SAR processing circuit connected to the second PCI bus.
And a sub CPU for controlling the first PCI bus and the second PCI bus.
Is connected, and the start address for writing packet data is
Dual port that stores packet length information as a command
Memory between the main CPU and the sub CPU.
Notification of completion of processing to the other party by interruption
Interrupt generation means for intervening, and without intervening the processing by the main CPU.
The bridge transfer that refers to only the
Using a bridge processing circuit, a memory for storing an address resolution table, an address resolution table stored in the memory
Te, to the user LAN or we said connectionless network
CL address from IPv4 address when performing data transfer
Processing to solve the problem and the connectionless network
When transferring data from the network to the user LAN
IP-ARP to resolve MAC address from 4 addresses
A connectionless gateway device having an address search circuit for performing processing . 2. A command definition area for defining a command from the main CPU to the sub CPU, a command definition area for defining a command from the sub CPU to the main CPU, and data in a CLA processing direction. It is further divided into four areas, an area for storing a packet and an area for storing a data packet in the CLD processing direction, and further includes means for writing information such as a start address indicating a packet head position and a packet length to each area as a packet. The connectionless gateway device according to claim 1 . 3. An address resolution table stored in the memory includes a node number as index information, a flag corresponding to an address to be resolved, a path table having a pointer to a target address entry as a component, 3. The connectionless gateway device according to claim 1, comprising a CL address table, a CL / VPI correspondence table for managing correspondence between an actual CL address and a VPI value, and an IP-ARP table for storing a MAC address. 4. An apparatus according to claim 1, wherein said interrupt generating means includes a main CPU.
U and the sub CPU can be any one of claims 1 to 3, respectively an I / O register to generate an interrupt to notify the fact of the process completion to the counterpart by turning on an arbitrary bit The connectionless gateway device as described.