JP3170312B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus capable of performing image editing processing based on image compression-encoded data.

[0002]

2. Description of the Related Art In image recording apparatuses such as thermal printers, ink jet printers, and laser beam printers, a white / black printer having a bitmap memory has been mainly used as a conventional recording terminal. However, in recent years, the capacity of semiconductor memories has increased, the development of high-performance LSIs,
Advances in computer technology have increased the use of full color images for high definition recording.

On the other hand, there is an increasing demand for taking color natural image data into a computer and performing various processing and image communication, and a compression coding method for a color natural image called JPEG in the International Standards Organization (ISO) has been increasing. The standardization study committee is discussing the compression method of image data. This coding method is a variable-length coding method called ADCT method. 1
8, No. 6, pp 398-407 (Reference (1))
Is described in detail. When this ADCT method is applied to the image memory of the above-described image recording apparatus, a full-color natural image is usually provided in the form of original data (uncompressed data), so that the memory capacity is 1/10 to 1/20 of the conventional memory capacity. Thus, the total cost of the recording apparatus can be significantly reduced, which is extremely useful.

On the other hand, when an image recording apparatus is used as a recording apparatus connected to an ordinary computer, it is common to use a standardized page description language (PDL) to provide data compatibility between different recording apparatuses. It is. This aims to make printers or computers of different specifications of different companies compatible with a common language, and to eliminate the drawback that a specific computer cannot be connected to a specific printer. As such a description language, for example, Po
st Script (registered trademark) and the like. For details of the contents, for example, a page description language Post Script
Reference Manual (Adobe System)
s Author: Haruhisa Ishida, Translated by Kunihito Matsumura, ASCII Publishing Bureau, 1
988)), Page Description Language PostScript Tutorial & Cookbook (Adobe Sys)
tems: Translated by Koichi Nonaka, supervised by the ASCII Publishing Technology Department, ASCII Publishing Bureau, 1989)).

[0005]

SUMMARY OF THE INVENTION Such a PDL
Is created with the concept of overwriting (that is, the concept of overwriting new dot data on the underlying data that has already been developed as dot data in the memory), and the PDL is stored in the above-described compressed memory. Used in
When correcting image data, there are problems in the following points.

[0006] 1) A block in which an image is combined in an ADCT 8 × 8 pixel block needs to be updated with new code data.

2) Since the compression method is variable-length encoding, when another image data is to be overlaid on a certain portion of the background image, the overlapping address is not constant.

3) The total code length of the synthesized new image data changes depending on the image quality.

From these, it has been considered difficult to correct the variable-length coded image data on the compression memory in accordance with the change of the pixel-form image data.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and in an apparatus for synthesizing a decompressed image of a PDL command and a compressed image, it is possible to change the content of a variable-length encoded compressed image as much as possible. It is an object of the present invention to execute the process while minimizing deterioration. Further, in the present invention, considering that the deterioration of the image quality of the compressed image increases as the number of times of decoding and re-encoding of the compressed image increases, the number of times of the decoding and re-encoding is further reduced as much as possible. Features.

[0011]

In order to achieve such an object, the invention according to claim 1 comprises a P command including a plurality of commands.
In an image processing apparatus that synthesizes a decompressed image of a DL command and a compressed image, the image is divided into a plurality of small areas, and the compressed image data obtained by performing variable-length encoding for each of the divided small areas is divided into the divided images. Storage means for storing the PDL command in correspondence with the small area, a development means for developing the PDL command, and a part in the compressed image data stored in the storage means to be changed by a plurality of PDL commands. Decoding means for judging the judgment part, and rewriting means for rewriting a decoded image obtained by the decoding means based on a result of expansion processing of the plurality of PDL commands, A compression method for performing variable length encoding on an image rewritten by rewriting means and storing the obtained compressed image based on the data of the determination part in the storage means. Comprising the door, the determining, decoding of the decision parts, each of rewriting of the decoded image, and characterized in that together PDL command of the plurality component units in such performed at a time.

[0012]

[0013]

[0014]

According to the present invention, an image is divided into a plurality of small areas, and compressed image data obtained by performing variable length coding for each of the divided small areas is stored in the storage means in correspondence with the divided small areas. In addition, a part in the compressed image data stored in the storage means to be changed by a plurality of PDL commands is determined, and the data of the determined part is decoded. After rewriting based on the PDL command expansion processing result, variable-length encoding is performed, and the obtained compressed image is rewritten and stored in the storage unit as the data of the determination part. As a result, it is possible to change the content of the compressed image that has been subjected to the variable-length encoding while suppressing the deterioration of the image quality as much as possible. Furthermore, according to the present invention, the above determination,
Since the decoding of the determination portion and the rewriting of the decoded image are collectively performed at once by using the plurality of PDL commands as a unit, the number of times of encoding / re-encoding the compressed image can be reduced. As a result, it is possible to suppress the deterioration of the image quality of the compressed image finally stored in the storage unit.

Further, by automatically setting the address of the small area including the pixel position on the storage means corresponding to the pixel position, the image data in the form of pixels arranged in series is compressed, It can be stored in the storage means in a specific order. It is also possible to read compressed area data of a small area at a specific position for the purpose of correction. Further, in the present invention, the compressed image data read for the purpose of correction is decoded into image data in pixel form by the decoding means, converted into image data to be corrected, and the converted decoded data is input to the compression means. The compressed image data after the image correction is written into the storage means.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Basic Configuration of First Embodiment) FIG. 1 shows a basic circuit configuration of a first embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a host computer that outputs a PDL language command sequence, and 2 denotes an interpreter (hereinafter, a PDL interpreter) that receives, resolves, and executes the command sequence output from the host computer 1.

Reference numeral 3 denotes a synthesizer for synthesizing background data and image data newly generated by the PDL interpreter 2 (conversion means of the present invention), and reference numeral 4 denotes a compressor (also referred to as compression means and encoder of the present invention). ). Reference numeral 5 denotes a compressed data memory (which constitutes the storage means of the present invention) which is used by being divided into blocks each having a sufficient memory amount.

Reference numeral 6 denotes a decoder (decoding means of the present invention), and reference numeral 7 denotes a multiplexer for switching whether to output the output of the decoder 6 to the synthesizer 3 or to another device.

8 controls read / write of compressed data,
An address controller (address setting means of the present invention) for setting an address for the compression memory 5 for reading and writing. Reference numeral 9 denotes an empty buffer area management circuit used by the address controller 8 to manage an empty area in the compression memory 5.

In such a circuit, upon receiving a PDL command from the host computer 1, the PDL interpreter 2 determines an image part to be changed by the command, and sequentially reads block raster data including the relevant part from the compression memory 5. The decoders of the address controllers 8 and 6 are controlled so as to read, decode and output.

At the same time, the PDL interpreter 2 controls the multiplexer 7 to output the data decoded by the decoder 6 to the synthesizer 3. The PDL interpreter 2 also controls the synthesizer 3 and inputs the decoded data output from the decoder 6 so as to store it in a buffer.

The PDL interpreter 2 adds new data generated by the above command to an area corresponding to the pixel position of the block raster (small area of the present invention) for which the capture of decoded data has been completed. The new data is converted by overwriting. When the data corresponding to the block raster area has been written by the PDL interpreter 2, the block raster area is compressed again by the compressor 4 and stored again in the corresponding location of the compression memory 5 so that the block raster area is stored again. 4 and the address controller 8. The above procedure is repeatedly executed over all necessary block rasters.

When one screen is divided into n (main scanning direction) × m (sub scanning direction) blocks, n blocks along the main scanning direction are called one block raster. In this embodiment, one block raster is treated as one small area of the present invention.

FIG. 2 shows an example of a circuit configuration of the synthesizer 3 shown in FIG.

In the figure, reference numerals 21, 22, and 23 each consist of (raster) buffers of eight lines (lines), each of which has a capacity to hold decoded data of one block raster.

Numeral 24 denotes a selector, which is the output data 27 from the PDL interpreter 2 and the signal data 2 which has been decoded by the decoder 6 and input via the selector 7.
8 are independently connected to any of the different eight line buffers among the eight line buffers 21, 22, and 23 based on the signal output from the selector controller 26. The selector controller 26 is controlled by a signal 29 output from the PDL interpreter 2. A selector 25 also selects and outputs one of the eight line buffers 21, 22, and 23.

The selector controller 26 communicates with the PDL interpreter 2 when to switch the buffer. That is, when the PDL interpreter 2 issues a request signal to write data to a new buffer, the selector controller 2
6 is 21 → 22 of the 8-line buffer 21 → 2
The 8 line buffers are switched in the order of 2 → 23 → 21 →... And connected to the signal line group 27.

At the same time, the eight line buffers are switched in the order of 22 → 23 → 21 → 22 →... To connect to the signal line group 28, and then the base data of the block raster overwritten by the PDL interpreter 2 is decoded. store.
At the same time, the selector 25 is controlled so that 23 → 21 → 2
The 8-line buffer is switched in the order of 2 → 23 →..., And the overwritten data from the PDL interpreter 2 is output to the encoder (compressor) 4 on the base data.

Reference numeral 30 denotes an address controller, which is a scanning line synchronization signal (HSYNC) from the decoder 6, a pixel synchronization (PXCLK), a data output address from the PDL interpreter 2, a scanning line synchronization signal from the encoder 4,
The pixel synchronizing signal is input, and the output address of the pixel data decoded by the decoder 6 on the 8-line buffer, the output address of the pixel data to be overwritten with the data from the PDL interpreter on the 8-line buffer, and the code, respectively. An output address on the 8-line buffer of the pixel data output to be encoded to the unit 4 is generated. The generated output addresses are output to different ones of the three sets of 8-line buffers in accordance with the selector signal from the selector controller 26.

FIG. 3 shows the address controller 30 of FIG.
2 shows a circuit configuration example. In the figure, 31 is a counter for counting the scanning synchronization signal (HSYNC) from the decoder 6, and 32 is a pixel synchronization signal (PXCLK) from the decoder 6.
Is a counter that counts

The counter 32 outputs the count result as an address corresponding to a position in one scanning line in the main scanning direction. The counter 31 outputs the counting result to the first pixel of each scanning line in one raster block. By outputting the upper bits of the address and outputting the output of the counter 31 as the upper bits and using the output of the counter 32 as the address signal line of the subsequent lower bits, the output data from the decoder 6 is stored in the 8-line buffer. The storage address is being generated.
Further, the counter 32 is reset by the scanning synchronization signal (HSYNC).

Similarly, counters 33 and 34 receive a synchronization signal from encoder 4. The counter 33 counts the scan synchronization signal (HSYNC) from the encoder 4, and the counter 34 counts the pixel synchronization signal (PXCLK) from the encoder and outputs the same to the encoder 4 as the counters 31 and 32. The storage address of the data on the corresponding 8-line buffer is generated.

The selectors 35, 36 and 37 are respectively
A selector for selectively outputting the address generated by the counters 31 and 32 to the eight line buffer selected by the selector 24, and selecting the address generated by the counters 33 and 34 to the eight line buffer selected by the selector 25. The selector outputs the address signal output from the PDL interpreter 2 and outputs the address signal to an 8-line buffer that holds the base data to be overwritten and selected by the selector 24.

Thus, the data overwritten on the base data is transferred again to the encoder 4 and compressed. The compressed data is output from the encoder 4 to the compression memory 5 and stored.

FIG. 4 shows storage locations of compressed data corresponding to each block raster on the compression memory 5. As an example, it is assumed that an image composed of a maximum of 4096 × 4096 pixels and 3 bytes per pixel (1 byte / color) is handled.

This maximum image is 48 megabytes (MByt
e) capacity. It is assumed that the compression by the encoder 4 is set to 1/12. In the block raster, each block is compressed in units of 8 × 8 pixels as described in the above-mentioned reference (1). Therefore, the maximum size image is 5
It is composed of 12 × 512 blocks. The largest image is compressed to a capacity of about 4 megabytes and the average code length per block raster is 8 kilobytes (KB).
Becomes In this embodiment, assuming a data amount of an average code length as a memory capacity per block raster, the compression memory 5 sets a compression memory area for each block raster every 8 kilobytes as shown in FIG.

FIG. 5 shows the state of data actually held in the compression memory shown in FIG. Each block in FIG. 5 is the same as the data area of each block raster in FIG. 4, and expressly expresses that a compression memory area for each block raster is set for each average code length.

The shaded portions indicate the areas where the codes for each block raster are actually stored.

In FIG. 5, the second block raster, the fourth block raster, the seventh block raster,
The 10th block raster,..., The 506th block raster, and the 510th block raster have a code amount longer than the average code length, and the block raster compression memory area set for each data amount of the average code length. The data is not stored in a single file, and is stored using a plurality of areas. In particular, in the case of the seventh block raster, the data is not stored using the second area, but is stored using three areas.

FIG. 6 shows a circuit configuration of the address controller 8 and the empty buffer area management circuit 9 shown in FIG.

In FIG. 6, reference numeral 61 denotes a counter for counting the synchronization signal of the block raster.
The count value indicates the number of the block raster area to be accessed. A value corresponding to the block address rewritten by the PDL interpreter 2 is set via a signal line 62 as an initial value of a counter 61, and the counter 6
1 counts the block raster synchronization signal 63 from the encoder 4.

Reference numeral 64 denotes a counter for counting the transfer clock of the block data. The counter 64 counts the transfer clock 65 for each byte from the encoder 4, and indicates at which position in the block raster data the count value is stored. ing. The counter 64 is reset by the encoder's block raster synchronization signal. When data cannot be stored in the corresponding block raster memory area in the compression memory 5, the counter 64 generates a count-up (carry) signal 76 and resets itself. In this case, the count-up signal 76 activates the empty buffer area management circuit 9 in FIG. 1 to obtain the position of the block raster memory area on the compression memory where the remaining data is to be stored continuously.

Numeral 66 denotes a counter which, like the counter 61, counts the synchronizing signal of the block raster. The counter 66 is set with the first block raster number in the block raster including the pixel position overwritten by the PDL interpreter 2 as an initial count. Or later,
The counter 66 counts the block raster synchronization signal 67 from the decoder 6 and indicates which block raster area in the compression memory 5 is to be accessed based on the count value.

Reference numeral 68 denotes a counter for counting the data transfer clock, similar to the counter 64.
Numeral 8 indicates the transfer clock for each byte from the decoder 6 and indicates which position in the block raster data is to be read by the count value. The counter 68 is reset by the raster synchronization signal of the decoder 6. The counter 68 also generates a count-up (carry) signal 73 if all data of the block raster has not been read even if the data has been read to fill the memory area for the corresponding block raster in the compression memory 5. And reset itself. In this case, the empty buffer management circuit 9 shown in FIG. 1 is activated by the count-up signal 73, and the position of the block raster memory area on the compression memory from which the remaining data is to be continuously read is obtained.

When the free buffer area management circuit 9 is activated by a count-up (carry) signal 76 from the counter 64 that counts the transfer clock of the block data, the block raster for writing in the image memory of the block raster being written is expanded. The address of the memory area is output to a signal line 80. At the same time, the selection switching signal 74 of the selector 78 and the latch timing signal 7 of the
5 is output. The block raster memory position for the extended area output to the signal line 80 is selected and output by the selector 78 at the timing of the signal 74, is held in the latch 79 at the timing of the signal line 75, and is used as the upper address of the storage address of the subsequent image data. Used.

Similarly, the empty buffer management circuit 9 includes a counter 68 for counting the transfer clock of the block data.
When the start is carried out by the count-up (carry) signal 73, the address of the block raster memory area for expansion in the image memory of the block raster being read is output to the signal line 81, and at the same time, the selection switching signal 87 of the selector 83 and Latch timing signal 8 of latch 84
8 is output. The block raster memory position for the extended area output to the signal line 81 is selected and output by the selector 83 at the timing of the signal 87, is held in the latch 84 at the timing of the signal line 88, and is used as the upper address of the read address of the subsequent image data. Used.

FIG. 7 shows the empty buffer area management circuit 9 of FIG.
3 shows a detailed circuit configuration.

In FIG. 7, the buffer read / write control circuit 9
When the signal 0 is input, the signal 102 outputs the signal 102 to the flag buffer 91. The flag buffer 91 is a buffer for several extended free area block rasters as shown in FIG. 8, and in FIG.
The flag buffer 91 is composed of the cells. Each cell corresponds to the 0th extension (block raster) area to the 511st extension (block raster) area of the image memory shown in FIG. 4, and the corresponding extension area with bit "1" is a free area. The bit "0" indicates that the area is already in use.

When buffer 91 receives signal 102, it stores the 512-bit information held therein from 98-0 to 98-51, respectively.
1 to a signal 98. Sorter 92 is signal 98
From the signals 98-0 to 98-511, and selects and outputs the signal with the lowest order among the signals of bit "1". Only the signal in that order is set to bit "1", and the others are set to bit "1". 512-input and 512-output as 0 "
Output circuit.

FIG. 9 shows a configuration example of the sorter 92. The output 99 of the sorter 92 is converted into a 9-bit signal 80 by the encoder 93 by encoding the order of the signal line of bit “1” into a 9-bit binary number. The signal 80 output by the encoder 93 indicates the position of the extension area in binary notation, and is taken into the extension block address buffer 94.

The buffer table 94 shown in FIG. 7 is configured as a table as shown in FIG. The block address before expansion input by the signal 86 is converted by the buffer read / write control circuit 90 into a signal 101 indicating the access position of the buffer table 94.
01 is received by the extension block address buffer 94, and the content of the signal 80 is fetched at the corresponding position.

The buffer read / write control circuit 90 outputs the signal 73
, The block number being read at that time is input by a signal 82, and the block number is output to the extended block address buffer 94 by a signal 101. The extension block address buffer 94 outputs the signal 10
The content at the position designated by 1 is output to the signal line 81.

The signal line 81 outputs the number of the block raster buffer in which the data subsequent to the block raster being read input by the signal 82 is stored.
This signal 81 is also output to the decoder 96 at the same time.
The decoder 96 generates a signal 10 on 512 signal lines 100 based on the signal 81 represented by a 9-bit binary number.
Only signals in the order of numbers indicating a 9-bit binary number among 0-0 to 100-511 are set as bit "1", and other signals are output as bit "0". The flag buffer updating circuit 95 outputs signals 98, 99 and 100, and sets the flag of the position of the extended block used for writing to "0" and the flag of the position of the extended block to be read to "1". It updates the use state of the empty buffer area of the memory, and FIG. 10 shows the details.

Referring back to FIG. 6, the latch 79 and the counter 6
4 is used as the write data address of the compression memory by combining the output of the latch 79 with the upper address signal and the count value of 64 as the lower address signal. Similarly, the latch 84 and the counter 68 output the upper address signal of the latch 84. , 68 are combined as a lower address signal and used as a read data address from the compression memory. Read / write control circuit 70
Inputs the write data address, the read data address, the data transfer clock 65 from the encoder 4, and the data transfer clock 69 from the decoder 6, and sets the address and timing for reading and writing data from the compression memory 5. Control.

The encoder 4 and the decoder 6 shown in FIG. 1 can be easily provided by adding a circuit for adjusting a synchronization signal and the like as necessary by using an LSI such as CL550 manufactured by C-Cube, USA. Configuration is possible.

The delimitation of the block raster is controlled using a marker code, and by using this marker code, encoding and decoding are executed independently for each block raster. This marker code is described in detail in, for example, the aforementioned reference (1).

The encoding system used in this embodiment will be described below.

FIG. 18 is a diagram for explaining the entire encoding system used in this embodiment along the processing flow.

First, the process proceeds with the original image as a block for each square area of 8 × 8 pixels. As shown in FIG. 180, the original manuscript has data prepared for each of the three color components of R, G, and B. For a square block of 8 × 8 pixels of a certain original image, a 64-pixel data block of only R is provided. , G only 6
A 4-pixel data block and a 64-pixel data block of only B are processed, and then the R data, G data, and B data of the 8 × 8 pixel block on the right of the square block of 8 × 8 pixels of the original image are processed in that order. When the processing is advanced and the processing of the block raster is completed, the processing of the next block raster is also performed sequentially from left to right in units of 8 × 8 pixel blocks. In the order of 181, 8 × 8
Each color component of the pixel is a known DC with a size of 8 × 8.
T (Discrete Cosine Transfo
rm) operation, and each value of the obtained result (also represented by a matrix having an 8 × 8 size) is converted into a predetermined quantization step value 183 (also a 8 × 8 matrix). In 182, linear quantization is performed for each of the 8 × 8 terms with 64 constant groups corresponding to each term. As the quantization matrix, it is preferable to use a value optimized so as to maximize the coding efficiency for the color component to be used, but it can basically be arbitrarily set. FIG. 21 shows an example used in this embodiment.

As shown in FIG. 20, the 8 × 8 DCT coefficients 184 after linear quantization obtained from the horizontal position i are from 0 to 7 from left to right, and the vertical position j is also When the position of each item is represented by coordinates (i, j) from 0 to 7 below, the position of (0, 0) represents a direct current (DC) component, and the spatial frequency in the horizontal direction increases as i increases. It represents a high component, and as j increases, the spatial frequency in the vertical direction represents a high component.

Each term of the 8 × 8 quantized DCT coefficient is
A direct current (DC) component at the (0,0) position and an alternating current (AC) component consisting of other terms are separately coded.

At 185, one-dimensional prediction is performed between neighboring blocks only for the direct current (DC) component to generate a prediction error. That is, the direct current (DC) of the previous block
The component DC (0,0) _k-1 is converted to the direct current (D
C) The value Delta _k subtracted from the component DC (0,0) _{K is used as} the prediction error of the block (Delta _k
= DC (0,0) _k- DC (0,0) _k-1 ). The prediction between the blocks is performed between the block and the previous block for each color component as shown in FIG.

At 186, the prediction error is coded according to the correspondence shown in FIG. 22, and the value of the code SSSS is Huffman coded. The value of SSSS not only indicates the group of the prediction error, but also indicates the number of bits required to specify which value in the group. For example,
SSSS = 2 group members are -3, -2,
That is, there are four, two and three, and two bits are required to identify which one of them. After the value of SSSS is Huffman-coded, additional bits of SSSS bits are subsequently added. The Huffman code is used to reduce the code length to 188 for frequently occurring codes.
Set in advance.

As shown in FIG. 20, the alternating current (AC) component is zigzag scanned from a low frequency component to a high frequency component in an 8 × 8 coefficient matrix. As shown in FIG. 23, a coefficient that is not 0 is classified into one of the 15 groups whose value is YRO. The identification code is SSSS (1 to 15
Integers up to). On the other hand, the number of zeros sandwiched between the immediately preceding non-zero coefficient is NNNN. The coefficient matrix is 8 ×
8, including 63 AC coefficients, but NNNN is 16
If it becomes more than the above, FIG.
31. By repeatedly generating the code of R16 in FIG. 31, the NNNN is reduced to 15 or less after all. These SSSS and NNNN values are not separate, but are Huffman-encoded as a set as shown in FIG. This Huffman code is an SSS that occurs frequently.
The combination of S and NNNN is preset to 188 so as to have a shorter code length. At the end of the code for the block for each color component, EOB (En
d of Block) code is added. 24 to 31 show examples of the Huffman code table used in the present embodiment. In the present embodiment, since the R, G, and B signals are 8 bits long, the DCT coefficient does not exceed 10 bits. For this reason, it is sufficient to consider SSSS from 0 to 10, so that FIG.
12 or more (for DC component) and 11 of SSS shown in 3
The above (for the AC component) is not described in the code table.

The above description has been given of the operation in units of one block raster. However, the operation in units of two blocks, four blocks, or half block raster can be realized in the same manner. .

[0068]

(First Embodiment) In the basic configuration described above, when the PDL interpreter 2 receives a PDL command from the host computer 1, the PDL interpreter 2 sequentially determines an image part to be changed by this command, and In the present invention, decoding, rewriting, and re-encoding are performed as follows.
That is, as shown in FIG.
, An image buffer 71 and a command buffer 72 are additionally connected, and several buffers of the PDL command and data received from the host computer 1 are temporarily stored in the buffers 71 and 72. Next, a part to be changed by each command is determined by the PDL interpreter 2 for each of a certain number of commands, and rewriting of the same block raster is performed at once. That is,
Decoding → Rewriting of the block raster is performed for a plurality of commands at once. In other words, decoding can be performed in the order of decoding → all rewriting relating to the block raster → recoding.

(Basic Configuration of Second Embodiment) The compression memory 5 of FIG. 1 may be configured as follows. In other words, a configuration may be adopted in which the compression memory is divided into blocks for each sufficient capacity compared to the average code length of each block raster and used.

FIG. 13 shows an overall circuit configuration diagram in this case. Parts having the same functions as in FIG. 1 are given the same numbers as in FIG. Hereinafter, description will be made with reference to the drawings. In FIG. 1, reference numeral 1 denotes a host computer that outputs a command sequence in the PDL language, and 2 denotes a PDL interpreter that receives, interprets, and executes the command sequence output from the host computer 1. 3 is the background data,
A synthesizer with image data newly generated by the PDL interpreter 2, a compressor 4, a compressed data memory 5 ', and a compressed data memory 5' which is used after being blocked every sufficient amount of memory. Reference numeral 6 denotes a decoder, and reference numeral 7 denotes a multiplexer for switching between outputting the output of the decoder 6 to the synthesizer 3 and outputting the output to the image forming unit of the recording device (not shown). 8 '
Is an address controller of a compression memory for controlling reading and writing of compressed data. When a PDL command is received from the host computer 1, the PDL interpreter 2
Determines the image part to be changed by the command, controls the decoders of the address controllers 8 'and 6 so as to sequentially read the block raster data including the relevant part from the compression memory 5' and decode and output the decoded data. At the same time, the multiplexer 7 is controlled, and the data decoded by the decoder 6 is output to the synthesizer 3.

The PDL interpreter 2 is additionally provided with a synthesizer 3
Is set, so that the decoded data from the decoder 6 is input and stored in the buffer. The PDL interpreter 2 overwrites the area corresponding to the pixel position of this block raster with the new data generated by the above-mentioned command on the block raster in which the capture of the decoded data has been completed.

After the data corresponding to the block raster area has been written, the block raster area is compressed again by the compressor 4 and stored again in the corresponding position of the compression memory 5 by the synthesizer 3, compressor 4 and It controls the address controller 8 '. The above procedure is repeatedly executed over all necessary block rasters.

Synthesizer 3 and Address Controller 30
Is exactly the same as the basic configuration applied to the first embodiment, and the respective circuit configurations are as shown in FIGS.

FIG. 14 shows the storage position of the compressed data corresponding to each block raster on the compression memory 5 '. As an example, a maximum of 4096 × 4096 pixels, one pixel 3
It is assumed that an image consisting of bytes (1 byte / color) is handled.
This maximum image has a capacity of 48 MBytes. Encoder 4
Is set to 1/12. In the block raster, each block is compressed in units of 8 × 8 pixels as described in the above-mentioned reference (1). Therefore, the image of the maximum size is composed of 512 × 512 blocks. The largest image is compressed to approximately 4 megabytes, and the average code length per block raster is
8 kilobytes. In the present embodiment, four times the average code length is assumed as a sufficient memory capacity for each block raster. As shown in FIG. 14, the compression memory 5 'sets a compression memory area for each block raster every 32 kilobytes. .

FIG. 15 shows the state of data actually held in the compression memory shown in FIG. Each block in FIG. 15 is the same as the data area of each block raster in FIG. 14, and expresses explicitly that a compression memory area for each block raster is set every four times the average code length. is there. The shaded portions indicate the areas where the codes for the respective block rasters are actually stored.

FIG. 16 shows the structure of the address controller 8 shown in FIG.

In FIG. 16, reference numeral 61 denotes a counter for counting the synchronization signal of the block raster. The counter 61 indicates which block raster area in the compression memory is to be accessed. The value corresponding to the block address rewritten by the PDL interpreter 2 is set as the initial value of the counter 61 via the signal line 62, and the block raster synchronization signal from the encoder is counted.

Reference numeral 64 denotes a counter for counting a data transfer clock. The counter 64 counts the transfer clock for each byte from the encoder 4 and indicates at which position in the block raster data the count value is stored. Also,
The counter 64 is reset by the encoder's raster synchronization signal. A counter 66 counts the synchronization signal of the block raster, similarly to the counter 61. The counter 66 is set as an initial count of the first block raster number in the block raster including the pixel position overwritten by the PDL interpreter 62. The block raster synchronization signal 67 is counted, and the count value indicates which block raster area in the compression memory is to be accessed.

Reference numeral 68 denotes a counter for counting the transfer clock of data, similarly to the counter 64. The counter 68 counts the transfer clock of each byte from the decoder, and indicates which position in the block raster data is read by the count value. ing. 68 is reset by the raster synchronization signal of the decoder 6. The count value of the counter 61 is combined with the upper address signal and the count value of the counter 64 as the lower address signal to be used as the write data address of the compression memory. Similarly, the count value of the counter 66 is used as the upper address signal and the count value of the counter 68. Are combined as a lower address signal and used as a data address read from the compression memory.

The read / write control circuit 70 receives the write data address, the read data address, the data transfer clock 65 from the encoder 4, and the data transfer clock 69 from the decoder 6, and reads data from the compression memory. And the write address and timing.

The encoder 4 and the decoder 6 are exactly the same as in the first embodiment. In addition, the division of the block raster is exactly the same as in the first embodiment.

(Second Embodiment) Also in the description of the basic configuration, when the PDL interpreter 2 receives a PDL command from the host computer 1, it sequentially determines an image part to be changed by this command and decodes the relevant part. In the second embodiment, the PDL received from the host computer 1 by using the image buffer 71 and the command buffer 72 as shown in FIG.
A command and data are temporarily stored in a buffer, and a part to be changed by each command is determined for each of a set number of commands, and rewriting for the same block raster is performed at once. That is, the decoding can be performed in the order of decoding → rewriting of the block raster at all → re-encoding. "

By performing processing for each of a number of commands once stored in the buffer as described above, the number of times of decoding and re-encoding can be reduced, and the degree of deterioration of image quality accompanying the processing can be reduced. Create an effect. In addition, there is an effect that a waiting time caused by executing a command to the host computer 1 can be reduced.

[0085]

As described above, according to the present invention, an image is divided into a plurality of small regions, and the compressed image data obtained by performing variable length coding for each of the divided small regions is divided into the divided image data. Stored in the storage means in correspondence with the small area
A portion in the compressed image data stored in the storage means to be changed by a plurality of PDL commands is determined, and the data of the determined portion is decoded. Is rewritten based on the result of the decompression processing, and then variable-length coded, and the obtained compressed image is rewritten and stored in the storage means as the data of the determination part. As a result, it is possible to change the content of the compressed image that has been subjected to the variable-length encoding while suppressing the deterioration of the image quality as much as possible. Further, according to the present invention, each of the determination, the decoding of the determination portion, and the rewriting of the decoded image are collectively performed in units of the plurality of PDL commands, so that the coding / reproduction of the compressed image is performed. The number of times of encoding can be reduced, and as a result, it is possible to suppress the deterioration of the image quality of the compressed image finally stored in the storage unit .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a circuit configuration of the synthesizer shown in FIG.

FIG. 3 is a block diagram illustrating a circuit configuration of the address controller of FIG. 2;

FIG. 4 is an explanatory diagram showing a data area corresponding to each block raster on the compression memory of FIG. 1;

FIG. 5 is an explanatory diagram showing a state of data held on a compression memory of FIG. 1;

FIG. 6 is a block diagram illustrating a circuit configuration of the address controller of FIG. 1;

FIG. 7 is a block diagram showing a circuit configuration of an empty buffer area management circuit of FIG. 1;

FIG. 8 is an explanatory diagram showing the contents of a flag buffer in FIG. 7;

FIG. 9 is an explanatory diagram showing the contents of the sorter of FIG. 7;

FIG. 10 is a circuit diagram of a flag buffer updating circuit of FIG. 7;

FIG. 11 is an explanatory diagram showing contents of an extended block address buffer of FIG. 7;

FIG. 12 is a block diagram showing a circuit configuration of a second embodiment of the present invention.

FIG. 13 is a block diagram showing a circuit configuration of a third embodiment of the present invention.

FIG. 14 is an explanatory diagram showing a data area corresponding to each butto cluster on a compression memory according to a third embodiment of the present invention.

FIG. 15 is an explanatory diagram showing a state of data held in a compression memory according to a third embodiment of the present invention.

FIG. 16 is a block diagram illustrating a circuit configuration of an address controller according to a third embodiment of the present invention.

FIG. 17 is a block diagram showing a circuit configuration of a fourth embodiment of the present invention.

FIG. 18 is an explanatory diagram showing a processing procedure of an encoding method according to the embodiment of the present invention.

FIG. 19 is an explanatory diagram for describing an inter-block prediction process according to the embodiment of the present invention.

FIG. 20 is an explanatory diagram for explaining a quantization matrix and DCT coefficients according to the embodiment of the present invention.

FIG. 21 is an explanatory diagram illustrating an example of a quantization matrix according to an embodiment of the present invention.

FIG. 22 is an explanatory diagram for describing encoding of DCT coefficients.

FIG. 23 is an explanatory diagram for describing encoding of AC coefficients.

FIG. 24 is an explanatory diagram showing an example of a Huffman code table.

FIG. 25 is an explanatory diagram showing an example of a Huffman code table.

FIG. 26 is an explanatory diagram showing an example of a Huffman code table.

FIG. 27 is an explanatory diagram showing an example of a Huffman code table.

FIG. 28 is an explanatory diagram showing an example of a Huffman code table.

FIG. 29 is an explanatory diagram showing an example of a Huffman code table.

FIG. 30 is an explanatory diagram showing an example of a Huffman code table.

FIG. 31 is an explanatory diagram showing an example of a Huffman code table.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Host computer 2 PDL interpreter 3 Synthesizer 4 Compression (coding) unit 5, 5 'compression memory 6 Decoder 7 Multiplexer 8 Address controller 9 Empty buffer area management circuit

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 1/41-1/419 B41J 2/485 G06F 12/04 G06T 9/00

Claims (1)

(57) [Claims] An image processing apparatus for synthesizing a decompressed image of a PDL command including a plurality of commands and a compressed image, divides the image into a plurality of small areas, and performs variable-length coding for each of the divided small areas. Storage means for storing the obtained compressed image data in association with the divided small areas; decompression means for decompressing the PDL command; and storage means to be changed by a plurality of the PDL commands. Decoding means for judging a part in the compressed image data stored in the means, and decoding the judged part; converting the decoded image obtained by the decoding means into a plurality of PDL command decompression processing results; Rewriting means for rewriting based on a variable-length code of the image rewritten by the rewriting means, and determining the obtained compressed image in the storage means Compression means for storing the data based on the position data, wherein each of the determination, the decoding of the determination part, and the rewriting of the decoded image are collectively performed at once by using the plurality of PDL commands as a unit. An image processing apparatus characterized in that: