JP3164815B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exposure technique, for example, a technique effective when applied to a photolithography process of a semiconductor integrated circuit device.

[Conventional technology]

As the degree of integration of semiconductor integrated circuits has increased and the design rules for circuit elements and wiring have reached the submicron order, g-lines,
In a photolithography process in which a circuit pattern on a mask is transferred onto a semiconductor wafer using light such as i-line, a serious problem arises in that the accuracy of the circuit pattern transferred on the wafer is reduced. For example, the transmission regions P ₁ and P ₂ and the light shielding region N formed in the mask 20 as shown in FIG.
When the circuit pattern composed of is transmitted onto the wafer, the phase of the light L immediately after passing through each of the pair of transmission regions P ₁ and P ₂ sandwiching the light shielding region N is in the same phase as shown in FIG. Therefore, two light beams interfere with each other at a portion of the wafer which is originally a light-shielding region and reinforce each other (FIG. 3C). As a result, as shown in FIG. And the depth of focus becomes shallower, resulting in a significant decrease in pattern transfer accuracy.

As means for solving such a problem, a phase shift technique has been proposed in which the phase of light transmitted through a mask is changed to prevent a decrease in contrast of a projected image.
For example, Japanese Patent Publication No. 62-59296 discloses that a transparent film is provided on one of a pair of transmission regions sandwiching a light shielding region, and a phase difference is generated between light transmitted through the two transmission regions during exposure. There is disclosed a phase shift technique in which the interference light is weakened at a place on the wafer which is originally a light shielding area. That is, a mask as shown in FIG.
When transferring the circuit pattern formed on 21 onto the wafer,
A transparent film 22 having a predetermined refractive index is provided on _{one of the} pair of transmission regions P ₁ and P ₂ sandwiching the light shielding region N. By adjusting the thickness of the transparent film 52 appropriately, the light immediately after passing through each of the transmission regions P ₁ and P ₂ is shown in FIG.
As shown in (1), these lights interfere with each other and weaken each other in the light shielding area N on the wafer (FIG. 3 (c)). As a result, as shown in FIG. 3D, the contrast of the projected image on the wafer is improved, the resolution and the depth of focus are improved, and the transfer accuracy of the circuit pattern formed on the mask 21 is improved.

Japanese Patent Application Laid-Open No. 62-67514 discloses that a fine opening pattern is formed by removing a part of a light-shielding region of a mask, and then the opening pattern or a transmission region existing in the vicinity of the opening pattern is formed. By providing a transparent film, a phase difference is generated between the light transmitted through the transmission area and the light transmitted through the aperture pattern, thereby preventing the amplitude distribution of the light transmitted through the transmission area from spreading in the horizontal direction. Techniques are disclosed.

In this specification, a phase shift method in which a normal pattern (main pattern) and a shifter pattern (accompanying pattern, complementary pattern) for providing a phase inverted to the normal pattern are provided on one mask is referred to as “on-mask phase shift”. Law "
Sometimes, when the phase shift amount is (2n + 1) π; (where n is an integer), it is referred to as “on-mask phase inversion shift method”.

Further, Japanese Patent Application Laid-Open No. 60-109228 discloses a method of simultaneously illuminating two masks to improve the throughput of projection exposure, thereby simultaneously exposing portions corresponding to different chips of one wafer. Have been. In addition,
Japanese Patent Application Laid-Open No. 60-107835 discloses a method in which one exposure light is divided into two parts, thereby illuminating the same part of two masks having the same pattern, combining them and exposing the wafer. A technique for exposing without any problem even if one of the defects is present.

However, these two methods are effective in preventing defects on the mask pattern from being transferred onto the wafer and improving throughput, but have no effect on improving resolution.

[Problems to be solved by the invention]

According to the study of the present inventor, a transparent film is provided in a part of the transmission area of the mask, and the above-described conventional phase which causes a phase difference between the light passing therethrough and the light passing through the transmission area in the vicinity thereof. The shift technique has a problem that a great deal of time and labor is required for manufacturing a mask.

Also, when exposing a pattern on a semiconductor wafer using a mask having an “L” -shaped opening pattern, the light inside the corner of the “L” -shaped pattern projected on the wafer becomes excessive due to light interference. This causes a problem that the pattern expands. Japanese Patent Application Laid-Open No. 2-140743 discloses that, when a pattern is exposed on a semiconductor wafer using a mask, the pattern is resolved in a region on the mask corresponding to a portion where the amount of light is insufficient due to light interference on the wafer. Although a technique for providing a light transmitting region having a dimension smaller than the limit is described, a technique for preventing a pattern from expanding due to excessive light due to light interference is not described.

An object of the present invention is to provide a phase shift technique that solves the above-mentioned problems.

One object of the present invention is that even if there is a step on the surface to be exposed,
It is an object of the present invention to provide a reduced transmission exposure technique capable of providing the best image surface with a single exposure for a plane having each step.

An object of the present invention is to provide a projection exposure technique capable of extending the exposure limit of a fine pattern by ultraviolet and far ultraviolet light to a further fine range.

An object of the present invention is to provide a projection exposure technique capable of combining and exposing two mask patterns.

An object of the present invention is to provide a reduced projection exposure technique capable of projecting and exposing two mask patterns by synthesizing interference even when the distance at which a light source can interfere is short.

An object of the present invention is to provide a mask pattern layout technique useful for manufacturing an integrated circuit using a phase shift method.

One object of the present invention is to provide an SRAM using a phase shift method or the like.
It is an object of the present invention to provide a projection exposure technique that is useful for the manufacture of a device such as the one described above.

An object of the present invention is to provide an exposure technique that is useful for manufacturing a highly integrated semiconductor integrated circuit device such as a DRAM having a fine dimension equivalent to an exposure wavelength.

An object of the present invention is to provide a projection exposure technique effective for exposing a periodic fine pattern.

An object of the present invention is to provide an effective projection exposure technique applied to an excimer laser exposure technique.

An object of the present invention is to provide a mask inspection technique useful for inspecting a mask used for a phase shift method.

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

One aspect of the present invention is to provide a circuit pattern by exposing a photoresist film on a semiconductor wafer by a reduction projection exposure apparatus using an optical mask having a first light transmission pattern in a light shielding region formed on a mask substrate. A method of manufacturing a semiconductor device, comprising: forming an auxiliary in the vicinity of a pattern peripheral region in the first light transmission pattern corresponding to a region where an exposure amount becomes excessive due to light interference in the photoresist film. Providing a light shielding area,
A method of manufacturing a semiconductor device, wherein a part of light transmitted through the first light transmission pattern is blocked.

[Action]

According to the above-described means, even when a pattern such as an “L” -shaped opening is exposed, the projected light pattern expands because the auxiliary light shielding area is formed in a portion where light is excessive. Can be prevented.

〔Example〕

The following description of the embodiments of the present invention will be made into a plurality of sections for the sake of convenience. However, each embodiment is not a separate one, but corresponds to a part of a process relating to a single invention or a modified example. Therefore,
Except where it is necessary at times, description of overlapping parts will not be given. Further, with respect to the reference numbers used in the following examples,
Those having the same last two digits have the same or similar structure or function unless otherwise specified.

(1) Embodiment 1 FIG. 1A shows a phase shift mechanism 1 of an exposure apparatus which is I of Embodiment 1 of the present invention.

The phase shift mechanism 1 includes a beam expander 4 provided between a light source 2 of the exposure apparatus and a sample 3 to be irradiated, a mirror 5,
6 and 9, half mirrors 7, 8, a corner mirror 10, an optical system including a variable optical path length mechanism 11 for minutely driving the corner mirror 10, a pair of lenses 12a, 12b, a reduction lens 13, and the like. In the alignment system of the optical system, a mask 14 on which an original image of a pattern to be transferred to the irradiation sample 3 is formed is positioned. The mask 14 is, for example, a mask (reticle) used in a manufacturing process of a semiconductor integrated circuit device, and the irradiated sample 3 is, for example, a semiconductor wafer made of silicon single crystal.

Light L such as i-ray (wavelength 365 nm) generated from the light source 2
Is expanded by the beam expander 4, and then after being refracted to the main surface perpendicular to the direction in which the mask 14 via the mirror 5, the light L ₁ to straight through the half mirror 7 provided in the optical path which is divided into two parts and the light L ₂ which advances in a direction perpendicular to the. Light L ₂ is refracted through the mirror 9 and the corner mirror 10, it is irradiated to another point of the mask 14 through the path different from the optical L _1. The two lights L ₁ and L ₂ transmitted through different portions of the mask 14 pass through the lenses 12a and 12b,
After being combined into one light L ′ via the half mirror 8, the light L ′ is reduced by the reduction lens 13 and irradiated onto the irradiation target 3 positioned on the XY table 15.

In the phase shift mechanism 1, since the optical path lengths of the two lights L ₁ and L ₂ from passing through the half mirror 7 to reaching the mask 14 are different, the corner mirror
By varying up to 10 height (the length of the optical path of light L _2),
A desired phase difference can be generated between the two lights L ₁ and L ₂ immediately after passing through the mask 14. For example, the position of the corner mirror 10 when the phases of the two lights L ₁ and L ₂ immediately after passing through the mask 14 are the same as the origin, and from the origin, the following equation d = (2m + 1) λ / 4 (λ : Wavelength of light, m: integer) by moving the corner mirror 10 in the vertical direction by the distance (d) defined by the following formula, whereby the phases of the two lights L ₁ and L ₂ immediately after passing through the mask 14 are reversed. Phase (180 degree phase difference). The vertical movement of the corner mirror 10 is performed using, for example, an optical path length variable mechanism 11 using a piezoelectric control element or the like.

 FIG. 1B is an enlarged view of a cross section of the mask 14.

The mask 14 is made of, for example, transparent synthetic quartz glass having a refractive index of about 1.47, and has a main surface on which a metal layer 16 of Cr or the like having a thickness of about 500 to 3000 ° is formed. At the time of exposure, the metal layer 16 becomes a light-shielding area A through which light does not pass, and the other area becomes a transmission area B through which light passes. The integrated circuit pattern is constituted by the light shielding area A and the transmission area B, and has, for example, a size five times the actual size.

FIGS. 1C and 1C are examples of an integrated circuit pattern formed on the mask 14. FIG. Circuit pattern P ₁ shown in the diagram (a) is, the light shielding region A of the light shielding regions A Toko hatched
And an L-shaped transmissive area B surrounded by a circle. On the other hand, the transmission region B of the circuit pattern P ₂ shown in (b) has a transmissive region B and the same shape of the circuit pattern P _1, and the interior of the transmission region B in which the size is enlarged,
Transmission region B and the same shape of the circuit pattern P _1, and has a pattern of arranging the light-shielding region A of the same size. That is,
Transmission region B of the circuit pattern P ₂ is substantially the circuit patterns
Consistent with the pattern of the peripheral portion of the transmission region B of P _1. The two circuit patterns P ₁ and P ₂ are a pair of patterns for transferring a circuit pattern P (hatched portion) as shown in FIG. 1C (c) to the wafer with high accuracy. They are arranged at predetermined locations at predetermined intervals.

 Next, a method for forming the mask 14 will be briefly described.

First, after polishing and cleaning the surface of the synthetic quartz glass plate,
On the entire surface on the main surface, for example, Cr having a thickness of about 500 to 3000 mm
A film is deposited by a sputtering method, and then a photoresist is applied on the entire surface of the Cr film. Next, based on the integrated circuit pattern data previously encoded on a magnetic tape or the like, an integrated circuit pattern is drawn on the photoresist by an electron beam exposure method, and then the exposed portions of the photoresist are removed by development, and the exposed Cr film is exposed. Is removed by wet etching to form an integrated circuit pattern. The pattern data of the pair of circuit patterns P ₁ and P ₂ is obtained by enlarging or reducing the data of the light shielding area A or the transmission area B of one of the circuit patterns, or inverting the data of one of the circuit patterns and the other of the circuit patterns. And can be automatically created by taking a logical product with the data of For example, the pattern data of the circuit pattern P ₂ is a data obtained by enlarging the pattern of the through region B of the circuit pattern P _1, the circuit pattern
It can be created automatically by taking the logical product of the inverted data of the transmission region B of P _1.

In order to transfer the integrated circuit pattern formed on the mask 14 onto the wafer 3, first, the wafer 3 having a surface coated with photoresist is placed on the XY table 15 of the exposure apparatus shown in FIG.
It is positioned above and the mask 14 is positioned in the alignment system. Mask 14, when the light L ₁ of one divided by the half mirror 7 is irradiated onto one of the circuit patterns P ₁ of the pair of the circuit patterns P _1, P _2, the other light L ₂ There performed as accurately irradiated onto the other circuit pattern P _2. Next, the corner mirror 10 is vertically moved, and the phase difference is adjusted so that the phases of the two lights L ₁ and L ₂ immediately after passing through the mask 14 are opposite to each other. Mask 14
In order to accurately perform the positioning of the laser beam and the adjustment of the phase difference between the two light beams L ₁ and L ₂ , for example, a pair of alignment marks formed on the mask 14 as shown in FIGS. 1A and 1B are used.
Use M ₁ and M ₂ . Each of the marks M ₁ and M ₂ is constituted by a pattern composed of a light-shielding area A indicated by oblique lines and a square transmission area B surrounded by the light-shielding area A, and their dimensions and shapes are exactly the same. It is. When the positioning of the mask 14 and the adjustment of the phase difference between the lights L ₁ and L ₂ are accurately performed, the light L ₁ transmitted through the mark M ₁
The light L ₂ transmitted through M ₂ interferes with each other and completely disappears, so that the projected images M of the marks M ₁ and M ₂ are not formed on the wafer 3. That is, the projected image M on the wafer 3
By discriminating the presence or absence, it is possible to easily determine whether or not the positioning of the mask 14 and the adjustment of the phase difference between the lights L ₁ and L ₂ have been accurately performed.

After performing the positioning of the mask 14 and the adjustment of the phase difference between the lights L ₁ and L ₂ in this manner, the original image of the integrated circuit pattern formed on the mask 14 is optically reduced to 1/5, for example. The above operation is repeated while projecting onto the wafer 3 and sequentially moving the wafer 3 in steps.

The 1D diagram (a) is a sectional view of the mask 14 in the circuit pattern P ₁ is formed region, FIG. 4 (b) is a sectional view of the mask 14 in the circuit pattern P ₂ is formed regions is there.

The light L ₂ immediately after passing through the transmission region B of the light L ₁ and the circuit pattern P ₂ immediately after passing through the transmission region B of the circuit pattern P _1, shown in 1D view (a '), (b' ) Thus, the phases are opposite to each other. Further, the circuit pattern P ₂ transmission area B
Since match the pattern of the peripheral portion of the transmission region B of the circuit pattern P _1, the amplitude of the combined beam L 'of the two light L _1, L ₂ is as Fig. (C). Therefore, when the combined light L ′ is irradiated onto the wafer 3, as shown in FIG.
At the boundary between the original light beams L ₁ and L ₂ , they interfere and weaken each other. as a result,
As shown in FIG. 3E, the contrast of the image projected on the wafer 3 is greatly improved, and the resolution and the depth of focus are greatly improved.

As described above, the exposure apparatus of the first embodiment divides the light L generated from the light source 2 into two lights L ₁ and L ₂ , and these two lights L ₁ and L ₂
By changing the optical path length until reaching the mask 14, the phases of the two lights L ₁ and L ₂ immediately after passing through the mask 14 are made opposite to each other, and then the two lights L ₁ and L ₂ are combined. Irradiate on the wafer 3. The mask 14 of the first embodiment, the transmission region B of one of the circuit pattern P ₂ is a pair that match the pattern of the peripheral portion of the other circuit pattern P ₁ in the transmission region B circuit pattern P ₁ , and it has a P _2. Therefore,
By transferring the integrated circuit pattern formed on the mask 14 by using the exposure apparatus on the wafer 3, the light L ₁ and the circuit pattern that has been transmitted through the transmissive region B of the circuit pattern P ₁
The light L ′ obtained by synthesizing the light L ₂ transmitted through the transmission region B of P ₂ interferes with the light L ₁ and L _{2 at} the boundary between the light L ₁ and L ₂ and is weakened. Thus, the circuit pattern P can be transferred onto the wafer with high accuracy.

Therefore, the following effects can be obtained by the exposure method I of the first embodiment.

(1) Unlike the conventional phase shift technique, there is no need to provide a phase shift means such as a transparent film on the mask, so that there is no restriction on the pattern design. In I of the first embodiment, when transferring one circuit pattern onto a wafer, it is necessary to form a pair of circuit patterns on a mask. You can enlarge or reduce the data in the transparent area,
It can be automatically created by taking the logical product of the inverted data of one circuit pattern and the data of the other circuit pattern.

(2) The step of inspecting the transparent film for defects, which is indispensable in the conventional phase shift technique, is unnecessary. Example 1
In I, the defect inspection of a pair of circuit patterns can be performed in the same manner as a normal mask by comparing with the original pattern data. Also, the dimension inspection can be performed by laser measurement or the like in the same manner as a normal mask. Therefore, the mask inspection process does not become complicated.

(3) Since no phase shift means such as a transparent film is provided on the mask, cleaning can be performed by the same method as that for a normal mask. Therefore, it is possible to create a mask free of foreign matter as much as a normal mask.

(4) According to the above (1) to (3), the transfer accuracy of the circuit pattern can be improved without requiring much time and labor for manufacturing the mask.

FIGS. 1F and 1B show another example of a pair of circuit patterns formed on the mask I of the first embodiment (first embodiment).
II).

Each of FIG. (A) circuit is shown in pattern P ₁ and the circuit pattern P ₂ shown in FIG. (B), is surrounded by the light blocking region A of the light shielding regions A Toko indicated by hatching, for example, a rectangular transparent region B. A pair of circuit patterns P ₁ and P
Reference numeral ₂ denotes a pair of patterns for transferring a circuit pattern P (hatched portion) as shown in FIG. 3C onto the wafer with high accuracy, and both are arranged at predetermined positions of the mask 14 at predetermined intervals. ing. The circuit pattern P is composed of four patterns P _A , P _B , P _C , and P _D having the same size and shape. Transmission region B _A of the circuit pattern P ₁ corresponds to the pattern P _A, transmission region B _C of the circuit pattern P ₁ corresponds to the pattern P _C.
Further, the transmission region B _B of the circuit pattern P ₂ in the pattern P _B, the transmission region B _D of the circuit pattern P ₂ respectively correspond to the pattern P _D. That is, the circuit pattern P is a pattern in which the transmission regions B of the pair of circuit patterns P ₁ and P ₂ are alternately arranged.

The 1G diagram (a) is a partial sectional view of the mask 14 in the circuit pattern P ₁ is formed region, the 1G view (b) shows one of the mask 14 in the circuit pattern P ₂ is formed regions It is a fragmentary sectional view.

The light L ₂ immediately after passing through the transmission region B of the light L ₁ and the circuit pattern P ₂ immediately after passing through the transmission region B of the circuit pattern P _1, shown in 1G diagram (a '), (b' ) Thus, the phases are opposite to each other. Also, a combined light L ′ of the two lights L ₁ and L ₂
As shown in FIG. 3C, the boundaries of the original light beams L ₁ and L ₂ approach each other. Therefore, this combined light L 'is irradiated on the wafer 3, as shown in FIG. 2 (d), the original light L _1, L ₂
Interfere and weaken each other at the boundary of. As a result, as shown in FIG. 3E, the contrast of the image projected on the wafer 3 is greatly improved, and the resolution and the depth of focus are greatly improved.

1H (a) and (b) show still another example of the pair of circuit patterns formed on the mask I of the first embodiment (III of the first embodiment).

Circuit pattern P ₁ shown in the diagram (a), was surrounded by the light blocking region A of the light shielding regions A Toko hatched, for example, a square of the transmission region B. On the other hand, the transmission region B of the circuit pattern P ₂ shown in (b) is arranged on the outside of each side of the transmission region B of the circuit pattern P _1. The pair of circuit patterns P ₁ and P ₂ are a pair of patterns for transferring a circuit pattern P (hatched portion) as shown in FIG. At predetermined intervals.

The 1I diagram (a) is a partial sectional view of the mask 14 in the circuit pattern P ₁ is formed region, the 1I view (b) shows one of the mask 14 in the circuit pattern P ₂ is formed regions It is a fragmentary sectional view.

The light L ₂ immediately after passing through the transmission region B of the light L ₁ and the circuit pattern P ₂ immediately after passing through the transmission region B of the circuit pattern P _1, shown in 1I diagram (a '), (b' ) Thus, the phases are opposite to each other. Also, a combined light L ′ of the two lights L ₁ and L ₂
As shown in FIG. 3C, the boundaries of the original light beams L ₁ and L ₂ approach each other. Therefore, this combined light L 'is irradiated on the wafer 3, as shown in FIG. 2 (d), the original light L _1, L ₂
Interfere and weaken each other at the boundary of. As a result, as shown in FIG. 3E, the contrast of the image projected on the wafer 3 is greatly improved, and the resolution and the depth of focus are greatly improved.

As described above, the invention made by the inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments, and it can be said that various modifications can be made without departing from the gist of the invention. Not even.

In the above description, the case where the invention made by the present inventor is mainly applied to a mask used in a manufacturing process of a semiconductor integrated circuit device which is a utilization field as a background has been described, but the present invention is not limited to this. Instead, the present invention can be widely applied to all exposure techniques for transferring a predetermined pattern formed on the mask by irradiating the sample to be irradiated with light transmitted through the mask.

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

A predetermined pattern formed on the mask is formed by irradiating light on a mask on which a predetermined pattern including a light-shielding region and a transmission region is formed, and irradiating the light on the sample to be irradiated with light transmitted through the transmission region of the mask. When transferring onto the sample to be irradiated, by dividing the light generated from the light source into two lights, by changing the optical path length until each of the two lights reaches the mask, a different portion of the mask The phases of the two lights immediately after passing through are opposite to each other,
According to the exposure method of the present invention, in which the two lights are combined and irradiated onto the irradiated sample, one light transmitted through a predetermined transmission area on the mask and another light transmitted through another transmission area on the mask are combined. At a place where one of the lights is located close to the irradiated sample, the two lights interfere with each other at their boundary region and weaken each other, so that the contrast of the projected image is greatly improved.

Thereby, the transfer accuracy of the pattern can be improved without requiring much time and labor for manufacturing the mask.

(2) Embodiment 2 An outline of a typical invention disclosed in this embodiment is as follows.

The first invention has a first pattern and a second pattern each having a light-shielding region and a transmission region, and irradiates the two types of patterns with at least partially coherent two lights having a phase difference. A mask for forming a desired pattern on a sample to be irradiated by synthesizing a transmission pattern of the light, and transmitting the first pattern at a boundary where the accuracy of the desired pattern is required. The first pattern and the second pattern are formed on the same substrate or with the first pattern so that light transmitted through the region and light transmitted through the transmission region of the second pattern interfere with each other and weaken each other. The second pattern and the second pattern are separately formed on two substrates.

In the invention of the second exposure apparatus, a light source that generates at least partially a coherent light beam, a light beam splitting unit for splitting the coherent light beam into two, and until the light beam is combined again from the light beam splitting unit An optical phase shift member placed on one of the optical paths, an optical system for synthesizing a light beam transmitted through the first pattern and the second pattern into a single light beam, and a sample to be irradiated with the single light beam An optical system for projecting the light transmitted through the first pattern and the light transmitted through the second pattern by 180 degrees by the optical phase shift member. A synthesized desired pattern was created.

In the description of the third exposure method, the first pattern and the second pattern on the first mask are irradiated with at least partially coherent two lights each having a phase difference, and the light is transmitted. The patterns were synthesized to create a desired pattern on the sample to be irradiated.

In this specification, an at least partially coherent light beam means a light beam having sufficient coherence to achieve an effect of interference and weakening.

Further, in the present embodiment, the boundary portion includes not only the boundary of the line segment constituting the pattern of the desired pattern but also the region sandwiched between the two line segments.

According to the above-described means, the light transmitted through the transmission area of the first pattern and the light transmitted through the transmission area of the second pattern interfere with each other and weaken each other at the boundary where the accuracy of the desired pattern is required. As described above, the first pattern and the second pattern on the mask constituting the first pattern and the second pattern are irradiated with at least partially coherent two lights having a phase difference, respectively, Since the desired pattern is created on the sample to be irradiated by combining the light transmission patterns, it is possible to improve the transfer accuracy of the boundary where the accuracy of the desired pattern is required.

FIG. 2A is a configuration diagram of a main part of an exposure optical system that is an embodiment of an exposure apparatus using the mask of the present invention, FIGS. 2B to 2D,
Main part plan view of the mask of the present invention using the exposure optical system,
2E to 2G correspond to FIGS. 2B to 2D, respectively, and are explanatory diagrams showing the amplitude and intensity of light passing through the mask.

The exposure apparatus according to the present embodiment is roughly divided into four elements functionally. The first element irradiates two light beams having a phase difference to the mask 209 (first element), the second element composed of the mask 209 (second element), and the third element that transmits two transmitted lights of the mask 209. An element (third element) that synthesizes and irradiates the irradiated sample 215 in a reduced size, and a fourth element that is an alignment mechanism that adjusts the synthesis of a single light beam (fourth element)
It is.

The first element includes a light source 201 that emits partially coherent light, an expander 202 that expands the light emitted from the light source 201, mirrors 203 and 206 that bends the optical path, and transmits part of incident light and reflects part of incident light. It comprises a half mirror 204 and a phase shift member 205 for changing the phase of light. The third element includes lenses 201 and 211 for converting two transmitted lights from the mask 209 into parallel light, a mirror 212, a half mirror 213, a reduction lens 214 for reducing light, a sample to be irradiated 215, and a movable sample table. It consists of 216. The fourth element includes an alignment mechanism 207 for moving the mirror 203, the half mirror 204, the lens 210, and the mirror 212, and a control circuit 208 therefor.

In the above description, the mirror 203 is provided to reduce the size of the entire apparatus. However, the light from the expander 202 may be directly incident without providing the mirror 203. The half mirror 204 has a function of splitting the light from the expander 202 into two, and is arranged on the first pattern 209a on the mask 209. The phase shift member 205 is placed between the half mirror 204 and the mirror 206 or between the mirror 212 and the half mirror 213, and has a function of shifting the phase by a predetermined amount. The phase shift member 205 uses, for example, synthetic quartz glass having a refractive index of 1.47. With the mask 209 disposed and the phase shift member 205 not provided, the first light flux 230 from the mirror 212 and the lens 211
If the phase difference of the second light flux 231 is zero, the thickness d of the phase shift member is d = mλ / 2 (n−n, where λ is the wavelength of the light source and n is the refractive index of the member. 1) (m: integer) is used.

The phase shift member 205 is used because, during exposure, of the light transmitted through the two transmission regions, the light transmitted through the phase shift member 205 and the light not transmitted through the phase shift member 205 This is to cause a phase difference of degrees. For example, the wavelength λ of the light irradiated at the time of exposure is set to 0.365 μm (i.
Line), when the refractive index n of the phase shift member 205 was set to 1.5, the thickness X ₁ of the phase-shift member 205 may be in the m (integer) times of 0.365 .mu.m.

The mirror 206 is a mirror for making the light transmitted through the half mirror 204 and the light transmitted through the phase shift member 205 parallel. The two patterns 209a and 209b on the mask 209 are 2
The two light beams 330 and 331 are arranged so as to be orthogonal to each other.

The lenses 210 and 211 are usually arranged such that the centers of the optical axes thereof coincide with the centers of the patterns 209a and 20b, respectively. The half mirror 213 is for combining the two lights 230 and 231. The mirror 212 has a function of bending the light 230 for the synthesis.

The alignment mechanism 207 for the fourth element is a mechanism for moving a part of the optical system of the exposure apparatus necessary for alignment, and uses a piezoelectric element or the like. In FIG. 2A, the mirror 203, the half mirror 204, the lens 210, and the mirror 212 are configured to be moved. However, the type and number of optical elements to be moved naturally vary depending on the configuration of the exposure apparatus. The method for controlling the movement of the alignment mechanism 7 will be described later.

Next, the configuration of the mask 209 of the present invention, which is the second element, will be described.

First, it is assumed that a pattern (desired pattern) desired to be formed on the sample to be irradiated 215 is an inverted L-shaped pattern 229 having a two-dimensional spread as shown in FIG. 2B (c). FIGS. 2B (a) and 2 (b) each show a first pattern 209 formed on a mask 209 to produce such a desired pattern.
FIG. 6A is a plan view of an example of a second pattern 209b, which is arranged while maintaining a relative positional relationship in consideration of a desired pattern (c) to be synthesized by the sample 215 to be irradiated.

Both the first pattern 209a and the second pattern 209b are formed from a combination of a light shielding area and a transmission area, respectively. These patterns may be formed on a single substrate, or may be separately formed on two glass substrates. However, in this case, the difference in the thickness of the glass substrate is also corrected by the thickness of the phase shift member. In FIG. 2B, the transmissive area is shown by a white surface, and the light-shielding area is shown by oblique lines.

The transmission pattern 232 in FIG. 2B (a) has an inverted L-shaped transmission area, and the transmission pattern 236 in FIG. 2B (b) has a slightly smaller inverted L-shaped light shield in the inverted L-shaped transmission area. region
234 are provided, and are configured to have a band-shaped transmission region 236.

 Next, the operation of the present invention will be described.

The light emitted from the at least partially coherent light source 201 is expanded by the expander 202, the optical path is bent by the mirror 203, and then split by the half mirror 204 into two light beams. Normally, the half mirror 204 has a transmittance of 50% and a reflection of 50% (more precisely, a mirror having the same reflectance and transmittance). A phase shift member 205 is disposed on the optical path to one of the two luminous fluxes to the optical system. The light transmitted through the phase shift member 205 is 1
After a phase difference of 80 degrees is given, the mirror 206 irradiates the second pattern 209b of the mask 209. On the other hand, the light transmitted through the half mirror 204 is the first pattern of the mask 209.
Irradiates 209a.

The two light beams transmitted through the two patterns 209a and 209b formed on the mask 209 are converted into parallel light beams by the lenses 210 and 211 again and then combined. That is, the first pattern
After the optical path of the first light 230 that has passed through 209a is bent by the mirror 212, the first light 230 is combined with the second light 231 that has passed through the lens 211 by the half mirror 213 to form a single light beam.

Thereafter, the irradiation target 215 held on the movable sample stage 216 is irradiated with the two patterns 209a and 209b on the mask 209 in a combined state using the reduction lens 214, and the irradiation target 2
A desired pattern is formed on 15.

Here, when projecting the desired pattern shown in FIG. 2B (c), if the transmitted light of the first pattern 209a and the transmitted light of the second pattern 209b are combined with a phase difference of 180 degrees, why the mask 209 A description will be made as to whether or not the transfer accuracy of the pattern is improved.

First, as described above, the mask 209 is considered in consideration of the reduction ratio.
The first pattern 232 is configured as a pattern 232 having an outer periphery slightly wider than the outer periphery of the desired pattern 229 and having a transmission area inside the outer periphery. The second transmission pattern 236 is also assumed to be a strip-shaped transmission pattern 236 formed when a shielding pattern 234 having the same size as the desired pattern 229 obtained from the first pattern 232 is also taken into consideration in consideration of the reduction magnification.

With this configuration, the desired pattern to be obtained can be obtained.
In the peripheral area 238 of the 229, the transmitted light from the second transmission pattern 236 and the band-shaped area 23 inside the first transmission pattern 232 are provided.
The transmitted light from 6 ′ is weakened by the interference of light, and the boundary of the desired pattern 229 can be sharpened. Further, the desired pattern 229 is a shielding area 234 on the second pattern side.
And the transmission area 234 'on the side of the first pattern having the same size are synthesized, so that the exposure is the same as normal exposure, and a pattern is formed. In FIG. 2B (c),
Portions irradiated with light are indicated by hatched portions, and portions that are weakened by interference are indicated by white regions 238, and have a pattern opposite to that of FIGS. 2B (a) and 2 (b).

FIGS. 2E (a) and (b) are cross-sectional views of the first pattern 209a and the second pattern 209b on the mask 209, respectively, taken along the line YY. Reference numeral 262 indicates a substrate, and reference numeral 263 indicates a shielding member. 2E (a ') and (b') show the amplitude of the light immediately after transmission through the mask, respectively, and the light (b ') transmitted through the phase shift member in each of the transmission region 232 and the transmission region 236 of the mask. It can be seen that there is a phase difference of 180 degrees between the light and the light (a ') not transmitted through the phase shift member 205. FIG. 2E (c) is a diagram showing the amplitude of light transmitted through the first pattern and the second pattern and immediately after synthesis.

If irradiation is performed only with the first pattern 232, the amplitude of the light on the wafer will be sloped at the periphery of the pattern due to light diffraction, and the boundary will not be sharp. However, in the present embodiment, the light 242 having a phase difference of 180 degrees transmitted through the transmission region 236 in FIG.
Since it is arranged around the light 240 transmitted through the transmission area 232 in FIG. 2B, the desired pattern 22
At the 9th boundary, they are weakened, and the degree of decrease in light amplitude is remarkable. Therefore, blurring of the outline of the image projected on the wafer is reduced, the contrast of the projected image is greatly improved, and the resolution and the depth of focus are greatly improved (FIG. 2E).
d)). Since the light intensity is the square of the light amplitude,
The waveform on the negative side of the light amplitude on the wafer is shown in FIG. 2E (e).
Is inverted to the positive side as shown in FIG.

As described above, according to the mask of the present embodiment, when the desired pattern to be obtained is a pattern having a two-dimensional spread, the first pattern is placed on the outer periphery of the two-dimensional pattern (desired pattern) at a relative position on the mask. The transmission pattern has a two-dimensional spread by forming a transmission pattern having a transmission region inside a slightly wider pattern and a second pattern being a strip-shaped transmission pattern having an outer periphery slightly larger than the outer periphery of the first pattern. Only the boundary of the desired pattern can be sharpened.

The mask 209 has alignment marks for aligning the first pattern 209a and the second pattern 29b. The driving of the alignment mechanism 207 is controlled by the alignment marks.

FIG. 2I is an example of a mark for positioning a pattern divided into two parts. This mark pattern is
(A) and (b) have exactly the same configuration, the same relative position and dimensions. The shape of the mark is not limited to a square as shown in the figure, and an L-shaped or cross-shaped figure can be used. However, it is better to provide a plurality of the same shapes for each direction in order to increase the accuracy. Further, in principle, these alignment marks are provided on the mask 209 only in dimensions required for alignment of the alignment mechanism 207. That is, X
If two-dimensional alignment of the Y-axis is required, these marks are also required in the two-dimensional direction of the XY axis, but in the case of the apparatus shown in FIG. Often.

If the transmitted light that has passed through this mark has a phase difference of 180 degrees and the positional relationship is correctly matched, all the transmitted light is the same as the light that has been shielded. Therefore, the state of the light shielding may be monitored by a CRT or the like, and when the condition is satisfied, the alignment may be completed.

Conversely, if the light is not completely shielded at the time of initial setting, the alignment mechanism
What is necessary is to drive the 207 to align the positions (a) and (b).

Next, a method for manufacturing the mask 209 of this embodiment will be described with reference to FIG. 2H.

As the mask 209 of this embodiment shown in FIG. 2A, a mask (reticle) used in a predetermined manufacturing process of a semiconductor integrated circuit device is used. Note that the mask 209 of this embodiment includes:
For example, an original image of an integrated circuit pattern that is five times the actual size is formed, and is constituted by a light-shielding region A and a transmission region B.

In manufacturing, first, after polishing and washing the surface of a transparent substrate 262 made of quartz glass or the like, a metal layer 263 made of, for example, Cr having a thickness of about 500 to 3000 mm is formed on the surface by a sputtering method or the like. I do. Next, this metal layer 26
For example, a photoresist (hereinafter, referred to as a resist) having a thickness of 0.4 to 0.8 μm is applied to the upper surface of 3. Subsequently, after pre-baking the resist, a predetermined portion of the resist is irradiated with an electron beam E by an electron beam exposure method or the like based on the integrated circuit pattern data of the semiconductor integrated circuit device which has been pre-coded on a magnetic tape or the like. The integrated circuit pattern data includes
The position coordinates and the shape of the pattern are recorded.

Next, for example, the patterns (a) and (b) are transferred to the resist by an electron beam exposure method or the like based on the pattern data shown in FIGS. 2A and 2B.

The pattern data of (a) and (b) is automatically created by enlarging or reducing the pattern width of the light-shielded area A or the transmissive area B of the above-mentioned integrated circuit pattern data. For example, in the present embodiment, (a) increases the pattern width of the light-shielding region by, for example, 0.5 to 2.0 μm, and (b) logically ANDs this with the inverted data of the original data to thereby convert the pattern data. It can be created automatically.

Thereafter, through processes such as development, etching of a predetermined portion, removal of the resist, cleaning and inspection, etc., FIG. 2B (a),
A mask 209 having the pattern shown in FIG.

To transfer the integrated circuit pattern on the mask 209 onto the irradiated sample 215 (hereinafter simply referred to as a wafer) on which a resist is applied using the mask 209 manufactured in this manner, for example, as follows.

That is, the mask 209 and the wafer are arranged in the reduction projection exposure apparatus shown in FIG. 2A, the original image of the integrated circuit pattern on the mask 209 is optically reduced to 1/5 and projected onto the wafer, and the movable sample stage Each time the wafer is sequentially moved in step 216, the integrated circuit pattern on the mask 209 is transferred to the entire surface of the wafer by repeating the projection exposure.

Next, another example of the mask according to the present embodiment will be described.

FIGS. 2A and 2B are main part configuration diagrams of the mask according to the present invention, and FIGS. 2A and 2B are 2A and 2B, respectively.
FIG. 4 is a plan view showing first and second patterns of a mask 209 shown in the figure and dividing the mask pattern while maintaining a relative positional relationship in consideration of the desired pattern. (C) is a plan view of the synthesized desired pattern. FIG. 2F (a) to (e)
FIG. 2C is a diagram for explaining the amplitude and intensity of light transmitted through the transmission region of the mask shown in FIG. 2C. The exposure apparatus and the method used are the same as those in the above embodiment.

In the embodiment shown in FIG. 2C, the desired pattern 248 has lines 244-247.
This shows a pattern configuration on a mask for sharpening the boundary when is a one-dimensional pattern arranged in a row in the horizontal direction. In this case, out of the lines 244 to 247, lines 244 and 24
6, the transparent areas 249, 250 and the lines 245, 250 of the first pattern
The transparent regions 251 and 252 of the second pattern forming the 247 are alternately arranged. Then, a region that interferes and weakens is located in the middle region 255 of each line constituting the desired pattern 248, and each line becomes sharp.

In FIG. 2F (a) to (e), the relationship will be described in the case where only the lines 244 and 245 are extracted from the desired pattern.
Also in this case, the light 256 transmitted through the transmission region 249 of the first pattern and the light 25 transmitted through the transmission region 251 of the second pattern are used.
There is a phase difference of 180 degrees between them (Fig. 2F (a '), (b')). Therefore, in the desired pattern on the wafer, the light components indicated by 259 and 260 in FIG. 2D (d ′) in the area 255 between the two lines 244 and 245 cancel each other by drying, and
As shown in FIG. 2D, the slope 261 of the light amplitude increases. Therefore, a sharp boundary can be formed in the region between the lines 244 and 245 shown in FIG. 2C. The second floor
FIG. 4D is a diagram schematically showing the amplitude of light on the wafer before interference.

As a result, the contrast of the projected image of the one-dimensional pattern can be significantly improved, and the resolution and the depth of focus can be greatly improved (FIG. 2F (e)).

According to this embodiment, when the desired pattern is a one-dimensional pattern in which the lines are arranged in a line in the horizontal direction, the transmission area of the first pattern constituting the line is determined at a relative position on the mask. And, by alternately arranging the transmission areas of the second pattern, and arranging the interfering and weakening areas in the middle of each line constituting the desired pattern,
In the case where a plurality of lines are arranged in a narrow area where the two-dimensional pattern technique cannot be used, the transfer accuracy can be greatly improved.

Next, other examples of the mask according to the present invention will be described.

FIGS. 2D and 2B are main part configuration diagrams of a mask according to the present invention, respectively. FIGS. 2A and 2B are 2A and 2B, respectively.
FIG. 4 is a plan view showing first and second patterns of a mask 209 shown in the figure and dividing the mask pattern while maintaining a relative positional relationship in consideration of the desired pattern. (C) is a plan view of the synthesized desired pattern. 2G (a) to (e) show
FIG. 3 is a diagram for explaining the amplitude and intensity of light transmitted through a transmission region of the mask shown in the 2D diagram. The exposure apparatus and the method used are the same as those in the above embodiment.

The desired pattern 269 of the present embodiment is one in which minute sub-patterns 272 are arranged around a square mask pattern 270.

Although it was difficult to transfer such a fine sub-pattern 272 around the two-dimensional pattern 270 with high accuracy by a conventional method of attaching a phase transparent film to a mask, according to the present invention, it is easy to obtain a good pattern. A desired pattern 269 can be created. That is, also in the mask of the present embodiment shown in FIG. 2D, at a relative position on the mask, the first pattern is formed into a pattern 274 having a transmission area of the same size as the two-dimensional pattern 270 in consideration of the reduction magnification. By making the second pattern the fine pattern 276, as shown in FIGS. 2G (a) to 2 (e), the light 277 transmitted through the phase shift member and the phase A phase difference of 180 degrees is generated between the light 278 that has not passed through the shift member 205 (FIGS. 2G (a ′) and (b ′)), and these lights are generated between the two-dimensional pattern and the minute pattern. Interference in region 280 can reduce blurring of the image projected on the wafer. As a result, the contrast of the projected image can be greatly improved, and the resolution and the depth of focus can be greatly improved (FIG. 2 (e)).

According to the masks according to these embodiments, the following effects can be obtained.

At the time of exposure, at the boundary where the accuracy of the desired pattern is required, the light transmitted through the transmission region of the first pattern and the light transmitted through the transmission region of the second pattern interfere with each other and weaken each other. Since the first pattern and the second pattern are configured, blurring of the outline portion of the image projected on the wafer is reduced, the contrast of the projected image is greatly improved, and the resolution and the depth of focus are greatly improved. Can be done. As a result, even if the same wavelength is used with the same projection lens as before, the resolution limit can be greatly increased. Therefore, even if the pattern on the mask is as complicated as an integrated circuit pattern and fine, the transfer accuracy of the entire pattern formed on the mask is greatly reduced without partially reducing the pattern transfer accuracy. It can be improved.

In addition, since two patterns are prepared and the effect of the phase shift is obtained by the synthesized pattern, the inspection is performed as in the case where the transparent film is not provided on the mask surface and the conventional transparent film is provided on the mask. The above inconvenience disappears.

Further, since there is no step of applying a transparent film, the manufacturing time of the mask can be significantly reduced as compared with a mask using a transparent film on a mask substrate as a phase shift means.

Although the invention made by the present inventors has been described based on the embodiments, the present invention is not limited to the above-described embodiments, and it goes without saying that various changes can be made without departing from the gist of the invention.

For example, according to the exposure method using the mask of the present invention,
It is not limited to the specific configuration of the apparatus, and is not limited to the configuration of the above-described embodiment in which the light beam is divided into two, and may be a unit that divides the light beam into a plurality of pieces, adds a phase difference to each of them, and synthesizes and exposes a plurality of mask patterns. It can also be.

In the above description, the semiconductor device manufacturing technique, which is a field of application in which the invention made by the present inventor is the background, has been described. However, the present invention is not limited to this. It is apparent that the present invention can be widely applied to the technical field of exposure to which the enhancement effect can be applied.

The effects obtained by the representative inventions among the inventions disclosed in the present embodiment will be briefly described as follows.

That is, the light transmitted through the transmission region of the first pattern and the light transmitted through the transmission region of the second pattern interfere with each other and weaken at the boundary where the accuracy of the desired pattern is required. A first pattern and a second pattern on a mask constituting the first pattern and the second pattern are irradiated with at least partially coherent two lights having a phase difference, respectively, and transmission patterns of the lights are radiated. Are synthesized to form the desired pattern on the sample to be irradiated, so that the transfer accuracy of the boundary portion where the accuracy of the desired pattern is required can be improved.

A method of combining and exposing a normal main pattern and a main pattern or a fine shift pattern (associated pattern) to be given a phase shift of π or an equivalent thereto on two masks as described in Embodiments 1 and 2 will be described. In the present specification,
It is referred to as "multi-mask phase shift method" or "multi-mask phase inversion shift method".

(3) Third Embodiment FIG. 3A shows a phase shift mechanism 301 of an exposure apparatus (1: 5 reduction projection / step-and-repeat method) according to a third embodiment of the present invention.

In the figure, a phase shift mechanism 301 includes a beam expander 304, mirrors 305, 307, 308, half mirrors 306, 313, an optical axis shifter 309, and a corner provided between a light source 302 of an exposure apparatus and a sample to be irradiated 303 (wafer). Mirror 310, variable optical path length mechanism 31 for minutely driving this corner mirror
1. An optical system including a pair of relay lenses 312a and 312b, a reduction lens system 315, and the like. A mask 314 (or reticle) on which an original image of a pattern to be transferred to the irradiation sample 303 is formed is positioned in the alignment system of the optical system. The mask 314 is, for example, a mask (reticle) used in a manufacturing process of a semiconductor integrated circuit device, and the irradiation target 303 is, for example, a semiconductor wafer made of silicon single crystal.

Light L such as i-line (365 nm wavelength) generated from the light source 302
Is expanded by the beam expander 304, and then after being refracted to the main surface perpendicular to the direction in which the mask 314 via a mirror 305, a light L ₁ to straight through the half mirror 306 provided in the optical path which Light L ₂ traveling in a direction orthogonal to
Divided. Light L ₂ is refracted through the mirror 307 and the corner mirror 310, the mask 31 through the path different from the optical L ₁
Irradiated to another part of 4. The two lights L ₁ and L ₂ transmitted through different portions of the mask 314 pass through the lenses 312a and 312b, are combined into one light L ′ via the mirror 308 and the half mirror 313, and then are reduced to a reduction lens 315. Reduced by X
An image is irradiated on the irradiation target 303 positioned on the Y table 316.

In the phase shift mechanism 301, the half mirror 306
Since the optical path lengths of the light beams L ₁ and L ₂ after passing through the optical path are different, the height from the main surface of the mask 314 to the corner mirror 310 (the light beam L ₂
, The desired phase difference can be generated between the light beams L ₁ and L ₂ that have reached the wafer 303. The vertical movement of the corner mirror 310 is performed using, for example, an optical path length variable mechanism 311 using a piezoelectric control element.

FIG. 3B is an enlarged view of a cross section of the mask 314. The mask 314 is made of, for example, a transparent synthetic quartz glass 322 having a refractive index of about 1.47, and a metal layer 323 such as Cr (chromium) having a thickness of about 500 to 3000 ° is formed on a main surface thereof. At the time of exposure, the metal layer 323 becomes a light-shielding region A through which light does not pass, and the other region becomes a transmission region B through which light passes. The integrated circuit pattern is constituted by the light-shielding region B and has, for example, a size five times the actual size (dimension on the wafer).

3C (a) and (b) are examples of an integrated circuit pattern formed on the mask 314. Circuit pattern P ₁ shown in the diagram (a) is part of a composite pattern after transfer (c), is obtained by extracting the low portion of the irradiated sample surface steps. Circuit pattern P ₂ shown in (c) is a part of a composite pattern after transfer (c), is obtained by extracting the high portion of the irradiated sample surface steps. Pattern P ₁ and P _2, the mask
314 are arranged at predetermined positions at predetermined intervals. In FIGS. 3C (a) to (d), reference numeral 331 denotes a semiconductor substrate such as an Si single crystal substrate or an epitaxial layer (Si), and 332 denotes SiO _2.
Films, 334a and 334b are gate electrodes or wirings made of poly-Si, polycide, silicide or refractory metal, 33
3 coated positive resist film thereon, B _A and B _C opening pattern on the main mask 314a, B _B and B _D opening pattern on the sub-mask 314b, P _A and P _C are lower portion position on the resist film corresponding to the pattern, P _B and P _D is the position on the resist film corresponding to the higher portion pattern.

Next, a method of forming the masks 314a and 314b will be briefly described.
First, after polishing and washing the surface of the synthetic quartz glass, a Cr film having a thickness of, for example, about 500 to 3000 mm is deposited on the entire surface of the main surface by a sputtering method. Apply resist. Next, based on the integrated circuit pattern data previously encoded on a magnetic tape or the like, an integrated circuit pattern is drawn on the electron beam resist by an electron beam exposure method, and then the exposed portion of the electron beam resist is removed by development, and the exposure is performed. The Cr film thus removed is removed by wet etching to form an integrated circuit pattern. The pattern data of the pair of circuit patterns P ₁ and P ₂ may be obtained by enlarging or reducing the data of the light shielding area A or the light transmitting area B of one of the circuit patterns, or inverting the data of one of the circuit patterns and the other circuit. It can be automatically created by taking a logical product with the pattern data. For example, the pattern data of the circuit pattern P ₂ is a data obtained by enlarging the pattern of the through region B of the circuit pattern P _1, the circuit pattern
It can be created automatically by taking the logical product of the inverted data of the transmission region B of P _1.

In order to transfer the integrated circuit pattern formed on the mask 314 onto the wafer 303 (FIG. 3A), first, the wafer 303 coated with photoresist on the surface is positioned on the XY table 316 of the exposure apparatus shown in FIG. 3A. Then, the mask 314 (314a and 314b) is positioned in the alignment system. mask
314 is one light L ₁ split by the half mirror 306
When but irradiated on one of the circuit patterns P ₁ of the pair of the circuit patterns P _1, P _2, other such that one optical L ₂ is accurately irradiated onto the other circuit pattern P ₂ Perform Next, the corner mirror 310 is moved vertically, and the phase difference is adjusted so that the phases of the _two lights L ₁ and L ₂ when recombined are opposite to each other. At this time, considering the coherence length of the light source, the difference between the two optical paths is kept as small as possible. In order to accurately position the mask 314 and adjust the phase difference between the two lights L ₁ and L ₂ , for example, a pair of alignments formed on the mask 314 as shown in FIGS. 3A and 3B Marks M ₁₁ , M ₁₂ , M ₂₁ , M ₂₂ (collectively Mln) are used.
The mark Mln is formed of openings of the same shape and the same arrangement provided at equal intervals in the shaded area indicated by oblique lines. That is, M ₁₂
All the distance dimension M ₁₁ and M ₂₁ and M ₂₂ are the same. When the positioning of the mask 314 (314a and 314b) and the adjustment of the phase difference between the light L ₁ and L ₂ are accurately performed, the light transmitted through the mark M ₁ n and the light transmitted through the mark L ₁ and the mask M ₂ n Since L ₂ interferes with each other and disappears completely, no mark images M ₁ and M ₂ are formed on the wafer 303. That is, wafer 3
By identifying the presence or absence of the projection images M ₁ and M ₂ on the 03, it is determined whether or not the positioning of the mask 314 (314a and 314b) and the adjustment of the phase difference between the light L ₁ and L ₂ are accurately performed. It can be easily determined.

The alignment of the patterns P ₁ and P ₂ on the mask is performed using the alignment mechanism 309. Next, the phase difference is adjusted according to the surface step of the irradiation target 303 (FIG. 3C). This adjustment is performed by computer-controlling (programming) the piezoelectric control element of the optical path length variable mechanism 311. That is, as shown in FIG. 3D, the focal position can be shifted in accordance with the phase difference, so that even when the irradiated sample has a surface step, it is possible to focus on both the upper and lower parts. Become.

After the positioning of the mask 314 and the adjustment of the phase difference between the lights L ₁ and L ₂ in this manner, the original image of the integrated circuit pattern formed on the mask 314 is optically reduced to, for example, 1/5. The above operation is repeated while projecting onto the wafer 303 and sequentially moving the wafer 303 in a step shape.

The data in FIG. 3D are obtained by the on-mask phase shift method as shown in FIG.
A transparent shifter layer on a mask was formed so as to be 0 ° and exposed. The experimental condition is the minimum pattern size 0.35
μm, exposure wavelength λ = 365 nm (i-line), NA = 0.42, partial coherency σ = 0.3, resist “RI7000P” (manufactured by Hitachi Chemical Co., Ltd.), exposure apparatus: 5: 1 i-line stepper “RA101” (manufactured by Hitachi, Ltd.) It is.

Note that the principle of the present invention is that two masks as described above are used.
The present invention can be realized not only by a pair mask phase shift method by combining patterns, but also by an on-mask phase shift method in which one mask is exposed with a single light beam. In this case, the thickness of the phase shift film 22 in FIG.
It must be formed to have a desired value between {} and {210}.

As described in the present embodiment, in the “phase shift method”, the method of projecting on a plurality of image planes by setting the shift amount to a value other than (2n + 1) π; The "phase shift method" will be referred to as "multi-mask multi-image plane phase shift method" particularly when two masks are used.

The exposure method according to the present embodiment and the exposure method based on simultaneous imaging of a plurality of planes having a step without a phase shift shown in the following embodiments are collectively referred to as a “multi-image plane projection exposure method”.

(4) Fourth Embodiment This embodiment relates to a modification of a step-and-repeat type 5: 1 reduction projection exposure apparatus (stepper) applicable to the first to third embodiments and the embodiments described later. This embodiment is effective when the coherence length is relatively short because, for example, exposure light with low coherency is used at the request of a process or the like.

FIG. 4A is a schematic front sectional view of the exposure optical system of the stepper of this embodiment. In the figure, reference numeral 402 denotes a mercury arc lamp, i-line of a mercury xenon arc lamp, etc. (365n
m), an exposure light source such as an excimer laser (249 nm or 308 nm), 403 is a wafer to be exposed, 404 is an illumination optical system including a beam expander and a condenser lens, 405 is a mirror such as a cold mirror, and 406 is a mirror. Half mirrors for splitting the light L almost equally into two, 407a and 407b are mirrors for reflecting the split lights L ₁ and L ₂ respectively, and 408 is a light
Corner mirror block, 408a the front corner mirror, 408b rear corner mirror, the drive control means of corner mirror block 408 is 409 for alignment between the optical path length control and a mask with respect to L _1, corner mirror block, 410a is a front portion thereof a mirror for optical path length control with respect to the light L ₂ is 410, 410b rear corner mirror, 414a primarily masks, 414b are sub-masks, 412a and 412b, respectively A front projection lens system corresponding to the light L ₁ , L ₂ , a drive control system 411 for the corner mirror 410, a combining half mirror 413 for combining L ₁ , L ₂ to L ′, 415 Is a rear projection lens system for forming an image of the combined light L ', and 416 is an XY
An XY stage and a wafer suction table for moving in the direction.

Since the operation of the present apparatus is almost the same as that of each of the above-mentioned apparatuses, the description of the operation will not be repeated.

(5) Embodiment 5 In this embodiment, the optical distances from the main mask to the wafer and from the sub-mask to the wafer are made substantially the same, and the optical distances from the main mask to the light source and from the sub-mask to the light source. The main feature is that the
The present invention relates to an AND repeat type 5: 1 reduction projection exposure apparatus. However, it goes without saying that none of these features is necessarily an essential feature of the present invention.

5A and 5B are a cross-sectional view of the i-line exposure apparatus of the fifth embodiment and additional explanatory views of representative light beams.

In these figures, reference numeral 502 denotes a light source unit, which is substantially monochromatic i-line (36) from an ultraviolet lamp such as an ultra-high pressure mercury arc lamp or a xenon mercury lamp and its emission spectrum.
It consists of a filter group that extracts only 5 nm) and a mirror. Reference numeral 504 denotes a condenser lens or a lens system including a group of one or several lenses (synthetic quartz), which forms Kler illumination on the mask. Reference numeral 551 denotes a first prism (synthetic quartz) for optical path length alignment bonded on the half mirror surface, and 506 splits the exposure light beam L,
A half-mirror surface for the main exposure light beam L ₁ in the sub-exposure light beam L _2. This half mirror is designed to have substantially the same reflectance and transmittance for the same polarization mode. 507a and 580a are mirror surfaces for 90 ° deflects the main luminous flux L _1, 507b are mirror surfaces for 90 ° polarize the sub beam L _2, 552a and 552b are polarization prism (synthetic quartz having a respective evaporated mirror surface ). 514a and 514b are main masks (reticles) having patterns to be exposed or transferred
And sub-masks (reticles) 561a and 561b are holders of the respective masks and minute driving means in the Z axis (optical axis direction) and XY axis directions. 540a and 540b are phase difference setting means for setting the phase difference φ between the two light beams by adjusting the optical path lengths of L ₁ and L ₂ , and 541 is a communicating pipe thereof. 562a and 562b, respectively front projection lens, 554 a second prism for optical path length matching (synthetic quartz), 553b is deflecting prism (synthetic quartz) for 90 ° polarization to L _2, 549a, 549b, and 508b Is a deflecting mirror surface, and 513 is a combining half mirror surface for combining the light beams L ₁ and L ₂ into L ′ (synthesized light beam). This half mirror 513 has the same characteristics as the above-described half mirror 506 for division. Reference numeral 515 denotes a rear projection lens group for exposure, 565 denotes a rear projection lens group for reference, 566 denotes light detection means provided on the image plane of the reference projection lens group, and 503.
Is a wafer to be exposed, 576 is a wafer chuck and θ rotation (rotational axis around a vertical axis passing through the center of the wafer) stage for securing the wafer flatness by vacuum suction, and 577 is a Z axis (vertical axis). Axial direction stage, 578 is 3
The horizontality adjusting means is composed of Z-axis driving means, 579 is an X stage, and 580 is a Y stage.

FIG. 5C is a sectional view of a main part of the phase difference setting means 540a of the stepper. In the figure, 542a and 543a are synthetic quartz glass plates, 541a is a means for adjusting the distance between them, 544a is a metal bellows, 547a is a pressure reservoir (Reservoir), 546a is a communicating pipe made of an austenitic stainless steel pipe, 545a
Is an optical path length control chamber in which a single gas or a mixed gas having a different refractive index from the atmospheric gas in the chamber in which the stepper is disposed or the main atmospheric gas in the exposure light beam passage is maintained at a constant pressure by the action of the pressure reservoir 547a. is there. The optical path length control chamber 545a can be brought into a vacuum state by using the vacuum pump 547a. In the case of a vacuum, it is not necessary to consider the temperature rise of the gas in the optical path length control chamber.

FIG. 5D is a top view of the wafer stage portion of the stepper. In the figure, reference numeral 503 denotes a wafer to be exposed, 576 denotes a wafer chuck and θ stage, 577 denotes a Z stage, and 578a.
Ｃc are the respective Z-axis direction driving elements which are elements of the horizontality adjusting means 578, 579 is an X table, and 580 is a Y table.

Next, the exposure operation of the present stepper will be described. First, the inclinations of the main mask 514a and the sub-mask 514b are adjusted so that the optical path length between the light source and the point on each mask corresponding to the exposure area is made as equal as possible. Further, the optical path length between each mask and each corresponding point on the wafer 503 is adjusted (tilt of the wafer) so as to be as identical as possible. Next, as described in the third embodiment, alignment, focusing using the mask M, XY
Mask adjustment in the plane and phase adjustment to phase difference φ = π (After that, if necessary, readjust the phase difference φ within the range of πφ <π (this may be a relative phase difference as long as interference occurs) Corresponding to the step), and then exposure of the same site is performed.

The adjustment of the phase difference is performed by adjusting the optical path length control room 54 as shown in FIG. 5C.
This is performed by changing the thickness of 0a or 540b. That is, the distance between the quartz plates 542a and 542b is moved in parallel by one of the quartz plates.

Further, the inclination of each mask or wafer is adjusted by three inclination adjusting means 578a to 578c (in the case of a wafer, the mask is also substantially the same mechanism) as shown in FIG. 5D.
Performed by moving in the axial direction.

The rear projection lens group 515 (FIG. 5A) is itself configured to be "telecentric" on both sides, that is, so that the principal ray travels parallel to the optical axis on both sides of the lens group. I have. Therefore, like the infinity cylinder length correction system in the microscope, the front projection lens group 562a or 56
When various optical elements are inserted between the second projection lens group 515 and the rear projection lens group 515, it is possible to minimize a change in overall imaging characteristics. Further, separately from the rear-stage projection lens group 515, the front-stage projection lens groups 562a and 562b are located near the masks 514a and 514b.
Therefore, it is easy to secure the optimum object-side numerical aperture.

(6) Embodiment 6 This embodiment mainly exposes the main mask and the sub-mask separately.
A description will be given of a mask pattern used in the invention in which the light beams are combined with a phase difference of (2n + 1) π and the wafer is exposed by the combined light. In the following description,
The main pattern and the sub-pattern corresponding to the same pattern (on the wafer) on the mask and the main mask are projected and shown on the same plane for convenience. Also, the dimensions attached to the pattern are shown in terms of dimensions on the wafer in the case of 5: 1 reduced projection. Regarding the sub-pattern, the boundary between the shielding area and the opening area is indicated by a broken line. Regarding the opening area of the sub-pattern, the corresponding portion is indicated by dispersed points.

FIG. 6A shows the isolated Al line of the embodiment 6A (other similar metal wiring lines, insulating film strips, strip-shaped openings,
The present invention can be applied to a poly-Si wiring or a gate line, a polycide wiring or a gate line, etc., but the description is limited to representative ones among them. 3) shows the patterns of the main mask and the sub-mask when the pattern is exposed by the negative process. (If a linear opening is to be formed, it is necessary to use a positive resist process with this mask pattern.) In the figure, reference numeral 601a denotes an opening on the main mask corresponding to the Al line, 604d and 605d is a light-shielding portion of the same main mask made of a chrome film, and 602b and 603b are sub-patterns (shifter and
When the pattern or the compensation pattern, especially the phase is inverted, it is referred to as phase inversion or simply inversion pattern or inversion slit. ), Dimension A is 0.3-0.4μm, dimension B is about 0.2μ
m and the dimension E are about 0.1 μm.

FIG. 6B shows a main mask and a sub mask pattern of the embodiment B. This example corresponds to a contact hole or a through hole or other isolated holes, and a positive resist process is used. (On the other hand, in the case of an isolated film pattern, a negative resist process is used.) In the figure, reference numeral 611a denotes an opening corresponding to a hole (opening) on the main mask, 612d denotes a light-shielding portion on the main mask, 613b, Reference numerals 614b, 615b, and 616b denote reverse slit groups on the sub-mask. Regarding the dimensions, the same symbols are substantially the same as those in the previous example.

FIG. 6C shows a mask corresponding to the isolated openings of the main mask and the sub-mask of the embodiment 6C which is a modification of the embodiment 6B.
It is a pattern. In the figure, 613C, 614C, 615C, and 6
Reference numeral 16C denotes an auxiliary opening pattern (corner enhancement pattern or enhancer) on the main mask for preventing the opening from being rounded, and all other components are the same as those in the embodiment 6B. The dimension of the enhancer is about 0.1 μm square. According to the embodiment 6B, this method is effective for preventing the corner portion from being excessively rounded.

FIG. 6D shows a main mask and a sub-mask pattern in the case where an “L” -shaped opening pattern corresponding to the minimum line width in the exposure process is processed by a positive resist process, as in the previous examples. . In the same figure, reference numeral 621a denotes an opening on the main mask, and 622d denotes a shielding portion on the main mask (this portion also becomes a part of the shielding portion with respect to the sub-mask as before, that is, a broken line. Except for the reversing shifter portion shown by, all correspond to the light shielding portion or the shielding portion.), 623b, 6
Reference numerals 24b, 625b, 626b, 627b, and 628b denote shifter region openings on the sub-mask, respectively. The dimensions are indicated by the same symbols as in FIG. 6B. (These symbols indicate the same dimensions unless otherwise noted.) If a negative resist process is used, this pattern becomes an isolated film pattern such as an Al “L” -shaped pattern as it is.

FIG. 6E is a modification example 6E of the embodiment 6D. In this figure, 621a 'is an opening pattern on the main mask corresponding to 621a in FIG. 6D, and 621d is an auxiliary light shield for preventing excessive expansion inside the corner of the "L" -shaped opening on the main mask. Pattern (corner reduction pattern or reducer), the size of which is the same as that of the enhancer. 623c, 624c, 625c, 626c, and 627c are opening patterns corresponding to enhancers provided on the main mask to prevent excessive reduction of corners, 622d is a shielding portion on the main mask,
623b, 624b, 625b, 626b, 627b, and 628b are shifter patterns (inversion openings), respectively.

FIG. 6F shows an embodiment of a main mask and a sub-mask corresponding to a negative resist process of an isolated bent Al wiring pattern of the 6F.
It is a pattern. In the figure, 631a is an opening on the main mask corresponding to the Al wiring, 638d and 639d are shielding parts on the main mask, and 633b, 634b, 635b, and 636b are shifters running along the Al wiring. Each dimension is basically the same as the others. When this pattern is applied to a positive resist process, it can be applied to forming a band-shaped opening.

FIG. 6G shows a main mask and a sub-mask pattern (corresponding to a negative process such as an isolated Al bending pattern) of the embodiment 6G. This example is a modification of the above-described 6F. In the same figure, 631c is an opening pattern acting as an enhancer, 631d is a shielding pattern acting as a reducer, these are both provided on the main mask, and the dimensions are the same as the equivalent pattern in FIG. 6E. The other points are exactly the same as those in the above-mentioned Example 6F.

FIG. 6H shows a main mask and a sub mask pattern for the line and space pattern of the embodiment 6H.
In this case, a negative resist process is used. In the same figure, 641a, 642a, and 643a are band-shaped opening / pattern portions on the main mask corresponding to the Al line pattern, and 641b, 642b, and 643b are band-shaped shifter openings on the sub-mask corresponding to the Al line pattern portion.・ Pattern part (or complementary ・
Line patterns), 645d, 646d, 647d, and 648d are shielding portions on the main mask. The dimensions are 0.3 μm for both lines and spaces. In the case of positive, it is necessary to replace the shielding portion between the opening on the main mask and the opening on the sub-mask and the opening adjacent thereto in FIG. That is, it is necessary to make the opening of the main or sub mask at a portion corresponding to the space. This is the same when a periodic strip-shaped opening is formed.

In the present embodiment, the 6A to H mask patterns are not limited to the multi-mask system as described above (embodiments 1 to 5), but also include an on-mask phase shift (relative position φ = π on one mask). Shifter pattern with inverted transparent film
(Phase shift exposure method using one mask having both the main pattern = ₀ ). In this case, the mask may be created by using the patterns of FIGS. 6A to 6H as they are on a single mask.

(7) Embodiment 7 Here, a wafer processing and an exposure process used for carrying out the present invention will be described.

FIG. 7A is a top view of a wafer showing an exposure flow of 5: 1 reduction step-and-repeat projection exposure. In the figure, reference numeral 703 denotes a wafer to be exposed (for example, an 8-inch single crystal S
i, wafer 702, orientation flat of the wafer, 731 and 732, exposure areas that have already been exposed (areas irradiated with light by one exposure operation, also called unit exposure areas), and 733 to 736, respectively. Each unit exposure area to be exposed from now on, this area will cover almost the entire area of the upper surface of the wafer 703. Exposure is performed in the numerical order shown here.

FIG. 7B is a plan view showing the relationship between the unit exposure area 733 and the chip areas 721, 722 and the inter-chip area 723 in the case of a memory IC.

7C to 7E and 7F to 7H are schematic cross-sectional views for explaining the flow of the exposure process using the positive and negative resists and the flow of the wafer process of the present invention, respectively. In FIGS. 7C and 7F, for the sake of simplicity, the ray diagram and the mask are on-mask phase shift (the phase shift method using one mask. However, only the main pattern is shown in the mask, and the shifter is omitted). Is shown), but
In the case of a multi-mask, the optical paths are only two in the middle and are combined into one on the wafer surface, so that they are exactly the same as those shown here.

7C to 7E, reference numeral 714 denotes a positive type mask, 745 denotes an opening of the mask 714, 714 denotes a reduction projection lens system shown in another embodiment, and 703 denotes a vacuum on a wafer stage of a stepper. The adsorbed wafer to be processed, 741 is the first oxide film on the main surface of the semiconductor wafer, and 742 is the Al formed thereon.
The wiring pattern 743 is a second oxide film formed on the entire surface thereof, and 744 is coated on the entire surface thereof by a spinner (0.6 μm).
m) is a positive resist film (see Example 16 for the resist).

In FIG. 7D, reference numeral 746 denotes an opening formed in a predetermined portion of the resist film 744.

In FIG. 7E, reference numeral 747 denotes a through hole of the second oxide film formed using the resist film 744 as a mask.

7F to 7H, reference numeral 714 denotes a negative mask, 755 denotes its opening or light-transmitting pattern, 715 denotes the same reduced projection lens system, and 703 denotes a semiconductor wafer which is adsorbed to the stepper wafer stage as before. Numeral 741 denotes an oxide film formed on the main surface thereof, 742 denotes an Al film deposited on the entire surface thereof by sputtering, and 754 denotes a negative type having a thickness of about 0.6 μm formed (applied) thereon. It is a photoresist film.

In FIG. 7G, 754x is a patterned resist film.

In FIG. 7H, reference numeral 742x denotes an Al wiring pattern patterned using the resist film 754x as a mask.

Fig.7J or Fig.7P shows CM using twin well method
FIG. 7 is a cross-sectional view of a manufacturing process flow of an OS-static RAM (SRAM), and FIG. 7Q is a layout diagram on the chip. Hereinafter, description will be made sequentially.

FIG. 7J shows an n and p well formation process by a twin well process. In the figure, 703 is an n ^- type Si
A single crystal wafer (substrate), 760n is an n-type well region, and 760p is a p-type well region.

FIG. 7K shows a subsequent gate forming process and a process of forming the source / drain of each FET by ion implantation with a self-aligned line using the formed gate as a mask. In the figure, reference numerals 761a to 761c denote LOCOS oxide films and 762p
And n are gate oxide films, 763p and n are polysilicon gate electrodes (or polycides), respectively, and 764p and n are p-type and n-type high-concentration source / drain regions, respectively.

FIG. 7L shows an interlayer PSG film forming process, a second layer poly-Si wiring, and a high resistance forming process. In the figure, 76
Reference numeral 5 denotes an interlayer PSG film, 766 denotes a second-layer poly-Si wiring, and 766r denotes poly-Si high resistance serving as a load resistance of the SRAM memory cell.

Figure 7M shows the SOG planarization process and contact
4 shows a hole or through-hole forming process. In the figure, 767 is a SOG film, 768a, b, d, and e are contact holes with the Si substrate, and 768c is a through hole between the second-layer poly-Si wiring and the upper layer.

FIG. 7N shows a process of forming a first-layer Al wiring. In FIG. 7, reference numerals 769a to 769 denote first layer Al wirings.

FIG. 70 shows a process of forming an interlayer insulating film on the first layer Al wiring and a process of forming the second layer Al wiring. In the figure, 77
0 is an interlayer insulating film on the first layer Al wiring, and 771a and 771b are second layer Al connected to a lower layer Al wiring or the like via through holes.
Wiring.

FIG. 7P shows a process of forming a final passivation film on the second-layer Al wiring. In the figure, reference numeral 772 is a final passivation film.

FIG. 7Q is a top view showing a layout of the SRAM in a chip unit. In the figure, 721 is a chip, 722 is a memory cell mat, and 723 is a peripheral circuit including an I / O circuit, an address decoder, a read / write circuit, and the like.

FIG. 7I is an exposure process flow diagram showing a process relating to photolithography in the above SRAM manufacturing process, that is, an exposure process extracted and flowd. In the figure, an n-well photo step 7P1 is a step of forming a resist pattern on a Si ₃ N ₄ film (on a substrate) so as to cover a portion other than a portion to be an n-well, and a field photo step 7P2 is a P-step. In order to pattern the Si ₃ N ₄ film so as to cover the active regions of the channel and the N channel, a resist film is applied thereon and patterned. The p-well photo step 7P3 is a step of patterning a resist film covering the n-well to form a channel stopper region of the p-well, and the gate-photo step 7P4 is a step of patterning the entire surface to pattern the gate electrodes 763p and n. This is a step of patterning a resist film on the applied poly-Si or polycide layer. The details of the process up to this point will be described in more detail in FIGS. 8A to 8E and the description thereof, so that it has been briefly described here. The n-channel photo step 7P5 is a step of patterning a resist film on the p-channel side for ion-implanting n-type impurities using the gate 763n as a mask on the n-channel side, and the p-channel photo step 7P6 is reversed on the p-channel side. A step of patterning a resist film on the n-channel side in order to implant a p-type impurity by using the gate 763p as a mask.
The step of forming a resist pattern on the poly-Si film deposited on the whole surface to pattern the second-layer poly-Si film to be 6r (FIG. 7L), the R photo step 7P8 is a poly-Si high resistance 766
r (Fig. 7L) Step of patterning the resist film as a mask to implant impurity ions into other parts with the resist film coated on the top by a negative process. The drain region, the first poly-Si layer, the second poly-Si layer, etc.
A resist pattern for forming contact holes 768a to 768e (FIG. 7M) for making contact with the layer Al wiring (Al-I) by a positive process, and an Al-I photo step 7P10 (FIG. 7N) is a resist patterning process for patterning Al-I, and a through-hole photo step 7P11 is for opening a through-hole for making a connection between Al-I and the second-layer Al wiring. Al-II photo step 7P12 (FIG. 70) is a resist patterning step for Al-II patterning, and a bonding pad
Photo process 7P13 is final passivation film 772
In this step, a resist film is deposited on the final passivation film other than the pads in order to form an opening of about 100 μm square corresponding to the bonding pad.

Among these exposure processes, n-well photo 7P1, n
Since the channel photo 7P5, the p-channel photo 7P6, and the bonding pad photo 7P13 have relatively large minimum dimensions, it is generally not necessary to use the phase shift method.

On the other hand, for the other exposure processes in FIG. 7I, it is effective to apply the “phase inversion shift method” of each embodiment of the present invention. The “phase inversion shift method” is a concept including both the “multi-mask phase shift method” and the “on-mask phase shift method”.

When there is a considerable difference between each plane of the memory mat 722 and the peripheral circuit section in FIG. 7Q, it is effective to use one of the shifts of the “multi-image plane projection exposure method” of the present invention. is there.

(8) Embodiment 8 FIGS. 8A to 80 show the process flow of 16MDRAM according to the present invention. The basic design rule is 0.6μm, stack type memory cell, LOCOS oxide film separation. The basic features are twin well CMOS configuration, WSi ₂ polycide bit line, and two-layer Al wiring using WSi ₂ / TiN tangent. is there. In the following processes, a photoresist removing step, a pre-processing (such as cleaning) and a post-processing step, an inspection step, a back surface processing step, and the like are omitted.

FIG. 8A is a cross-sectional view showing an n ^- well formation process by phosphorus (P) ion implantation. In the figure, reference numeral 803 denotes a P-type Si single crystal wafer having a resistivity of 10 Ω · cm (boron is a dopant) and a main surface of a mirror surface (100). 860 is a thin thermal oxide film, 861 is a Si ₃ N ₄ film as an oxygen-resistant mask, and 862 is a patterned resist layer that acts as a mask for ion implantation. Reference numeral 863 denotes an n-well region formed by P (phosphorus) introduced by implantation.

FIG. 8B is a sectional view showing a p ^- well forming process by boron (B) ion implantation. In the figure, reference numeral 865 denotes a thick oxide silicon film (SiO ₂ ) formed by thermal oxidation, 864a
Is the p-well region of the peripheral circuit, and 864b is the p-well of the memory array.
This is a well region.

FIG. 8C shows B (boron) in the p ⁺ type channel stopper region.
It is sectional drawing which shows the formation process by injection | pouring. In the same figure, 866a-d are p ⁺ channel stopper regions, 867a-c
Is an Si ₃ N ₄ film as an oxygen implantation and ion implantation mask, 868 is a photoresist film as an ion implantation mask, and 869a and b are gate oxide films.

FIG. 8D is a cross-sectional view showing a state where the LOCOS oxide film is formed. In the figure, reference numerals 870a to 870e denote LOCOS oxide films.

FIG. 8E is a cross-sectional view showing a process for forming a phosphorus-attached Si gate and an n-channel source / drain. In the figure, 871a, 871c and 871d are gate electrodes (P-doped polysilicon) of an n-channel FET, 871b are gate electrodes (P-doped polysilicon) of a p-channel FET, and 872a to 872e are n-channel sources or drains. P (phosphorus) ion implantation region corresponding to, 873 is a photo-
It is a resist film.

FIG. 8F shows a process of forming a high-concentration n-channel source / drain region performed after formation of a side wall. In the figure, 872x and y are p-channel source
The drain region, 874 is a photoresist film as an ion implantation resistant mask, and 874a to 874d are side wall insulating films (Si
O ₂ ).

FIG. 8G is a sectional view showing an interlayer SiO ₂ deposition process and a polycide bit line forming process. In the figure, reference numeral 877a denotes a poly-Si film (addition of phosphorus), and 877b denotes a silicide (WSi ₂ ) film, which form bit lines. 877c
SiO ₂ film by CVD is 876 is a SiO ₂ film by CVD which is As (arsenic) formed after implantation (deposition).

FIG. 8H is a cross-sectional view showing a process for forming a poly-Si electrode serving as an individual electrode of a capacitor of a memory cell. In the figure, 878 is a SiO ₂ film 876 and 877c integrally become thus formed SiO ₂ film, 879A and b is a poly Si deposited film serving as individual electrodes of the memory cell capacitor.

FIG. 8I is a cross-sectional view showing a process of forming a capacitor plate serving as the other common electrode of the capacitor of the memory cell. In the figure, reference numeral 880 denotes an Si ₃ N ₄ deposited film serving as a dielectric of a capacitor, and 881 denotes a phosphorus-doped poly-electrode serving as a plate electrode.
This is a Si deposited film.

FIG. 8J is a cross-sectional view showing a process of forming a high-concentration source / drain of a p-channel FET by implanting B ⁺ (boron). In the figure, reference numerals 882a and 882b denote resist films as ion implantation resistant masks.

FIG. 8K is a cross-sectional view showing a reflow process of the interlayer insulating film. In the figure, 883a-f are BPSG (Boro-Phos
The reflow films 884a to 884d are pho silicate glass films, and contact holes are formed there.

FIG. 8L is a cross-sectional view showing a silicide (WSi ₂ / TiN) wiring formation process. In the figure, 885a to 885c are lower layers.
This is a silicide wiring layer composed of both deposited films of a TiN film and an upper layer of tungsten silicide (WSi ₂ ).

FIG. 8M is a cross-sectional view showing a process of depositing an interlayer PSG (Phospho-Silicate-Glass) and forming a through hole. In the figure, reference numerals 886a to 886c denote interlayer insulating films formed of three layers of PSG / SOG / PSG.

FIG. 8N is a sectional view showing a forming process of the first-layer Al wiring. In the figure, reference numerals 887a to 887d denote a lower TiN buffer layer and an upper Al (Al99%, Si1%) wiring layer (Al-I).

FIG. 80 shows an upper interlayer PSG film and a second layer Al wiring (Al-I
It is sectional drawing which shows I) formation process. In the figure, 8
Reference numeral 88 denotes an inter-layer PSG film comprising the same three-layered deposited film of PSG / SOG / PSG as 886a to 886c. 889a and b are the second layer Al (Al
-II) The wiring layer.

FIG. 8P is a circuit layout diagram on the chip of the DRAM. In the figure, 821 is a chip area, 822a and b are memory arrays or memory cell mat sections, and 823 peripheral circuit sections (including bonding pads).

FIG. 8Q is a top view showing the cell plane structure of the memory array of the DRAM substantially for one period of the translation symmetry. However, the above wiring structure is omitted for simplicity. In the figure, 871c is a word line, 872d is an n-type source or drain region, 877a and b are bit lines, 879a is a storage node (capacitance), and 881 is a plate.

Next, a process flow of a preceding process (wafer process) of the DRAM will be described with reference to these drawings.

As described above, a p-type Si single crystal wafer having a thickness of 0.7 mm to 1.0 mm is prepared, and a thin thermal oxide film for a buffer is formed on the entire (100) plane. A Si ₃ N ₄ film is deposited on the entire surface by CVD with a sufficient thickness as an oxygen-resistant mask. Thereafter, spin coating is performed on the entire main surface of the wafer, and the resist is patterned and the underlying Si ₃ N ₄ film is etched by the exposure process (exposure process 1) of the present invention. next,
As shown in FIG. 8A, using the resist film 862 or the like as a mask, phosphorus is implanted into a portion to be an n-well region. Next, the resist film 862 is entirely removed, and a thermal oxide film is selectively formed on the n-well 863 using the Si ₃ N ₄ film 861 as an oxygen-resistant mask. Next, the entire surface of the Si ₃ N ₄ 861 is removed, and as shown in FIG. 8B, boron (B ⁺ ) is implanted into a portion to be a p-well using the oxide film 865 on the n-well as a mask for ion implantation.
Next, the spreading diffusion (N ₂ annealing) and activation processing in each well. After the oxide films 860 and 865 on the substrate are entirely removed, thin thermal oxide films 869a and 869b and a Si ₃ N ₄ film are formed on the entire surface. Next, as shown in FIG. 8C, the above Si ₃ N ₄
The film is patterned by the exposure process (exposure process 2) of the present invention so that the film remains only in the active region, thereby obtaining oxygen-resistant masks 867a to 867c. After that, the resist is removed. Further, a resist film is applied to the entire surface, and is exposed by any of the methods of the present invention (exposure process 3), and the entire upper surface of the n-well is covered with the resist 868. In this state, boron (B ⁺ ) is ion-implanted into regions 866a to 866d to be channel stoppers. Next, the resist film 868 is entirely removed, and the Si ₃ N ₄ film 86 is removed.
Using the masks 7a to 7c as masks, field oxide films 870a to 870e are selectively formed by thermal oxidation as shown in FIG. 8D. Next, Si
₃ N ₄ film 867a~c entirely removed, and further a thin oxide film 869A and b also removed on the active region, the new gate oxide film 869A 'and b' again, formed by thermal oxidation (first 8D view).

Further, a phosphorus-added poly-Si film is formed on the entire surface by low-pressure CVD, and a resist is applied. Then, the resist film is patterned (exposure process /
4) Then, using the resist film as a mask, the gate electrode 87 is formed.
Pattern 1a-d (FIG. 8E). Next, the n-well is covered with a resist film 873 (exposure process 5), and phosphorus (I) is implanted into the regions 872a to 87e to be the source / drain of the n-channel FET by ion implantation in a self-aligned manner with the gate electrodes. P) Implant ions. After that, resist 871b
Is removed. Further, the p-well region is similarly covered with a resist film (exposure process 6).
Boron (B) is ion-implanted into the regions 872x and y to be the source or drain of the FET (FIG. 8F). In addition, the gates 871a-87d
Are formed in a self-aligned manner around the edge of the substrate. Further, as shown in FIG. 8F, the p-channel portion is covered with a resist 874 (exposure process 7), and arsenic (As) is ion-implanted using the resist as a mask to form an LDD (Lightly
An n-type region forming a high-concentration region of Doped Drain is formed. After that, the resist 874 is removed.

Further, as shown in FIG.
₂ Film 876 is deposited. Next, a resist with a wide opening
According to the pattern (exposure process 8), a contact hole serving as a contact between the bit line of the memory cell and the substrate is formed in a semi-self-aligned manner. Furthermore, poly Si, WSi ₂ , pressure reduction
CVD SiO ₂ is sequentially deposited, a photoresist is applied (exposure process 9), and the bit lines 877a and 877b are patterned. After forming the bit line and removing the resist, an SiO ₂ film is deposited on the entire surface by low pressure CVD, and the side of the bit line is covered with an insulating film 8.
Cover with 78 (Figure 8H). Next, a contact hole between the storage node electrode of the memory cell and the substrate is coated with a photoresist (exposure process 10), and an opening is formed by etching the SiO ₂ film 878 and the underlying oxide film. Next, a poly-Si film to be a storage node electrode is deposited on the entire surface by low pressure CVD. Further, phosphorus (P) is ion-implanted into the entire surface of the poly-Si film, an activation annealing (N ₂ annealing) treatment is performed, and a photoresist is deposited (exposure resist /
11) Then pattern storage nodes 879a and b as shown in FIG. 8H. After that, the resist is removed.

Further, as shown in FIG. 8I, a Si ₃ N ₄ film to be a capacitor insulating film is deposited by low pressure CVD. Next, the above Si ₃ N
₄ is oxidized to a partial thickness. Further, a phosphorus-added poly-Si film serving as a capacitor plate is deposited thereon.
Next, a resist film is applied on these films, and unnecessary poly-Si and Si ₃ N ₄ films are removed by using a patterned (exposure process · 12) mask.
80 and plate 881 are formed. After that, the resist is removed.

Further, as shown in FIG. 8J, the n-channel portion is covered with a resist film (exposure process 13), and SiO ₂ in the p-channel portion is exposed.
The film 878 is removed. Next, after removing the previous resist,
The resist films 882a and 882b are again applied to the n-channel portion (exposure process 14), and the p-channel FE
Boron (B ⁺ ) is ion-implanted into a region to be a high-concentration source / drain region of the LDD structure of T. Thereafter, the resist film is entirely removed, and N ₂ annealing for activation is performed.

Further, as shown in FIG. 8K, a SiO ₂ film and a BPSG film are deposited on the entire surface and flattened by reflow. Next, a photoresist is applied and patterning is performed (exposure process 15) to form contact holes 884a to 884e. Next, the upper surface of the p-channel portion is covered with a photoresist (exposure process 16), and an n ⁺ -type
Form an n ⁺ contact region. After removing the resist, the n-channel portion is covered with a photoresist (exposure process 17), and the p ⁺ -type p ⁺ contact region is formed under the p-type source / drain contacts by ion implantation (B). Form. And removing the resist film, performing N ₂ anneal for reflow activation and BPSG film 883a~f ion implantation layer.

Further, as shown in FIG. 8L, a base TiN buffer layer and a wiring layer WSi ₂ (tungsten silicide) are deposited on the entire surface by CVD, and a photoresist film is applied thereon, and patterned into a desired shape (exposure process). 18) Then, using the mask as a mask, silicide wirings 885a to 885c are formed by dry etching. After that, the unnecessary resist film is removed. Perform N ₂ annealing treatment.

Further, as shown in FIG. 8M, an inter-layer PSG film having a PSG / SOG / PSG structure was deposited and formed, and the resist was coated by a positive resist process (exposure process 19) except for the place where a through hole was to be formed. Dry etching is performed in this state to form a through hole. After that, the resist film is removed.

Further, as shown in FIG. 8N, an underlying TiN film to be Al-I and an Al wiring layer (Al 99% superposition, Si1 superposition%) are deposited, and a resist is exposed thereon by a negative process (exposure process 20). The Al-I wirings 887a to 887d are formed by patterning by dry etching, leaving only the portions to be wirings. After that, the resist film is removed.

Further, as shown in FIG. 80, plasma SiO ₂ / SOG (Spin-On-
Glass) / plasma SiO ₂ inter-layer insulating film 888 is deposited, and dry etching is performed with a portion covered with a resist by a positive process (exposure process 21) except for the portion to be a through hole. Form a through hole. After that, the resist is removed. Next, Al-II
Al wiring layer (Al99%, Si1%) to be
A resist film is applied only on the portions to be wiring thereon by a negative process (exposure process 22). Thereby, dry etching is performed using this resist film as a mask, thereby forming Al-II wirings 889a and 889b.

Furthermore, normal pressure PSG film (final passivation)
Is deposited, and a resist film is applied by a positive process (exposure process 23) to a portion other than a portion to be a bonding pad thereon. Using this resist film as a mask,
A bonding pad opening is formed by chemical etching.

Of the above exposure processes, the phase shift method of each embodiment of the present invention is applied to the exposure processes 2, 4, 9 to 11, 15, and 18 to 22 in which strict conditions are required in dimensions. It is valid. Among them, as shown in Fig. 8P, the memory array section
When there is a large step between the planes 822a and 822b and the peripheral circuit 823 belong to, it is effective to utilize the multi-image projection exposure method shown in each embodiment of the present invention. In the process including a large number of periodic wirings such as the exposure processes 9, 18, 20, and 22, the mutual opening (FIG. 6H of the embodiment 6 and FIGS. 15A to 15F of the embodiment 15, etc.) The phase shift method (the phase inversion shift method) using the mask described above is effective.

(9) Embodiment 9 The concept of creating a mask layout according to the present invention and the theoretical background will be described.

FIG. 9A shows the amplitude intensity u (broken line) and the same energy intensity I (solid line) in the case of light from two apertures separated by ε (equivalent distance on the wafer) on a mask without a normal phase shift on the wafer. This is a plot of the coordinates X on the main surface. (Numerical value) Thus, for example,
When 5: 1 reduction projection is performed, the phase difference φ ₂ −φ ₁ =
When Δφ is equal to or equal to 0, constructive interference occurs, as indicated by the solid line I, and the peaks u ₁ and u ₂ are not resolved.

The problem of the resolution of such a minute proximity object by the projection system is given by Rayleigh as follows. That is, the distance between two adjacent points (converted on the wafer) is δ
Then: Here, λ is the exposure wavelength, and NA _i is the NA (numerical aperture) of the projection system on the image side.

For example, considering the case of the i-line, λ = 0.365 μm, for example, NA = 0.4, and the resolution limit δ is about 0.56 μm.
Therefore, as shown in FIG.
% To 50%), a pattern with a size of 2
A problem arises in that the lines cannot be merged and separated.

On the other hand, when a phase difference π (or its equivalent) is given to the light flux between two adjacent apertures as shown in FIG. 9B (phase inversion shift method), a sharp dent appears in the energy intensity I near the origin, and as a result , The peak is resolved into two.

FIG. 9C is a schematic diagram for explaining the principle of the multi-image plane phase shift method in which the phase difference Δφ between the main aperture and the sub-aperture is set to a value other than π or an equivalent value as in Embodiment 3. This greatly simplifies the optical action of the reduction projection system. In the figure, 991 is an exposure light beam (wavelength λ), 914 is a mask, 921a is a main aperture (for example, B _{A in} FIG. 3A), 921b
The sub opening (e.g. B _B of Figure 3C (b)), d is the distance between (the wafer on the basis) thereof opening, l is the distance between the mask and the image plane, l _1, l ₂ is the screen 903 from the opening (Optical length to image plane or wafer). Light intensity I on the screen
(X) is determined as follows.

The electrolysis intensity u ₁ , u ₂ by each aperture is represented by wave number k, phase φ ₁ , φ
Assuming that ₂ , u ₁ = Aexp [−i (kl ₁ −φ ₁ )] (9.2) u ₂ = Bexp [−i (kl ₂ −φ ₂ )] (9.3) For synthetic light, From this, assuming that the change of l is Δl, Δφ = φ ₂ −φ ₁ , It can be seen that changing Δφ changes the image plane. However, this model is a rough model, and needs to be corrected and confirmed by numerical calculations and experiments.

(10) Embodiment 10 This embodiment describes an ultraviolet light source for projection exposure applied to each exposure process of the present invention and its periphery.

FIG. 10A is a table summarizing various characteristics of the available exposure illumination system. In the diagram, Partial Coherence is generally denoted by the Greek letter “σ”, and its definition is It is. Here, NA _C is the numerical aperture on the mask side of the illumination system condenser lens, NA _O is the numerical aperture on the mask side of the exposure projection lens system, here, the NA _O = 0.4. As the ultraviolet light source used for the exposure of the present invention, a deep UV spectrum (far ultraviolet) between 0.2 and 0.3 μm of a Xe-Hg light source,
Excimer laser emission around 0.2 μm, Hg arc emission other than those shown in the above figure, and the like are available.

The illumination used in the present invention has a so-called Koehler illumination (Khler) structure. However, illumination with other configurations is also possible.

A specific example of the exposure illumination system will be described separately with reference to FIG. 19A.

(11) Embodiment 11 Here, a modified example (corresponding to embodiment 5) of the 5: 1 reduction projection exposure apparatus used for exposure according to the present invention will be described. In this example, in the illumination system and the exposure projection system, the lens operation for operating the two divided light beams is performed only by the same lens system. Therefore, a pair of lens systems is used for each of the left and right light beams. There is an advantage that it is not necessary to consider a difference in aberration of the lens system, which is a problem in the case. This exposure system is a double-sided telecentric system configured to be telecentric on the mask side (object side) and on the wafer side (image side).

FIG. 11A is a simplified schematic cross-sectional view of the illumination system and the exposure projection system of the stepper of this embodiment. In the figure, 1102
Is a light source that emits i-rays of mercury, etc., L is an initial light beam, 1104 is an illumination optical lens system such as a condenser lens that constitutes Koehler illumination, and L ₁ and L ₂ are separated by a half mirror with the same uniform intensity. 1114a is a main mask, 1114b is a sub-mask, 1140a is a light path length control room (which is a main light beam), 1140b is a light path length control room for a sub light beam,
L ′ is a combined light beam, 1115 is a projection lens system, and 1103 is a wafer to be exposed.

Since in this method are common to various easy lens system out difference in aberration for both light beams L ₁ and L _2, it is possible to increase the simultaneous exposure possible area. In addition, the phase shift can be adjusted to a desired value over the entire field that can be exposed at one time, so that a high resolution can be obtained.

This embodiment is not limited to the one shown in FIG. 11A. For example, two independent light source systems can be used. Also in this case, since the main lens system 1115 for the main and sub-beams is common in the lower half (after the mask) of the optical system, the aberration of the two optical systems with respect to the transfer characteristic of the pattern on each pair of masks. Adverse effects due to differences can be minimized.

Further, the present apparatus is applicable to all the exposure methods for simultaneously transferring the patterns on two masks onto one wafer.

The simplified optical structure in FIG. 11A is almost the same as in FIGS. 5A and 5B. The different part corresponds to the former-stage lens groups 562a and 562b, but is not present in this embodiment, but only in the presence of a double-sided telecentric projection lens system 1115 provided at a position equivalent to 515 in FIG. 5A.

(12) Embodiment 12 Here, a mask defect inspection apparatus for inspecting a mask according to the present invention will be described.

FIG. 12A is a simplified schematic cross-sectional view of a mask inspection apparatus. In the figure, 1252 monochromatic light source of the e-line (546 nm), L is the initial inspection light beams, L ₁ and L ₂ each main beam split inspection light flux uniformly divided with equal intensity similarly to the above exposure apparatus, and sub beam, M ₁ and M ₂ to be inspected mask, 1240a and b optical path length control chamber, 1265 1: 1 projection lens system, L 'synthetic inspection light beam, 1266 indicates an optical detector.

Note that the projection lens 1265 may have a magnification larger than 1 if necessary, or may have a reduced size. But,
In the case of reduction, the projection lens system must be able to resolve the accompanying pattern.

Next, the operation of the present apparatus will be described. First, the mask to be inspected
In mask M ₁ is for on-mask phase inversion shift, the reference mask M ₂ has the identical opening patterns, the shifter pattern that the (associated pattern and complementary pattern) portion is not phase shifted processing, i.e. The case where no phase shift film is formed will be described. In this case, by adjusting the optical path control means 1240a and b, the optical path L ₁ and L
_{If 2} is equal (a phase difference of 2nπ may be used), the shift pattern will not be visible at all in the composite image under normal conditions. On the other hand, when the thickness of the phase shift film is abnormal, the portion becomes a bright portion and is detected by the detector 1266.
In this case, since the corresponding main pattern is imaged as a bright portion, the mutual relationship between the defective portion and the main pattern can be clearly grasped.

Secondly, a description will be given of a case where the masks M ₁ and M ₂ to be inspected are a main mask and a sub-mask, respectively, in a mask inspection for multi-mask phase inversion shift. In this case, if the optical path length control means 1240a and 1240b are adjusted so that the phase difference between the two optical paths L ₁ and L ₂ is equal to or equal to 0, the main surface and the sub-pattern (associative) are formed on the image plane. Pattern) are imaged. Therefore, the defect can be comprehensively determined by electrically comparing the combined pattern and the mask design pattern information.

Third, in a mask inspection for a multi-mask phase inversion shift (including a mask having a phase difference other than π), both of the inspection target masks M ₁ and M ₂ remove accompanying patterns that cannot be resolved by the exposure projection system. A description will be given of a case where the masks are the same and have the same pattern. In this case, if the light dew length adjusting means 1240a and b are adjusted to set the phase difference to π or an equivalent value, the composite image of the normal accompanying pattern disappears or is weaker than the general case. Becomes On the other hand, if there is an abnormal pattern, only that part becomes a clear bright part.

(13) Embodiment 13 This embodiment relates to a technology effective when applied to reduced projection exposure of a wafer having a chip region having a height difference on the surface, such as a memory IC such as a DRAM.

FIG. 13A shows a step-and-repeat type of the embodiment.
1 is a simplified front sectional view (optical system) of a 5: 1 reduction projection exposure apparatus. In the figure, 1302a, monochromatic light source (e.g., i-line) of b are each independently identical wavelengths, L _1, L ₂ each main beam and sub beam, 1304a, b, respectively main and auxiliary exposure illumination lens system (Koehler illumination ), 1314a is the main mask for exposing the basin (peripheral circuit in case of memory IC), and 1314b is the plateau (memory cell or memory mat part in case of memory)
1334i and 1334j are shielding portions corresponding to the plateau portion on the chip, 1334k is a main pattern portion corresponding to the peripheral circuit pattern on the chip, and 1344k is a shielding portion corresponding to the basin portion on the chip. , 1344i and j are sub-pattern portions corresponding to the memory mat on the chip, L 'is a combined light beam by a half mirror, 1315 is a reduction projection lens system in which the object side and the image side are telecentric, and 1303 is a wafer to be exposed. , 1313i and j are the plateau (memory mat part), 1
313k or 1324 is a basin (peripheral circuit part).

FIG. 13b is a top view showing the arrangement of regions on the wafer corresponding to unit steps of exposure. In FIG. 13, the area surrounded by a broken line 1313 is the entire area exposed by the unit step,
That is, unit exposure areas, 1321 and 1322 are first and second chip areas, respectively, 1323 and 1324 are peripheral circuit parts of each chip area, and 1313k is a main exposure part corresponding to a basin or a valley (length divided by a broken line). Thin rectangular part), 13
13i and j are sub-exposure portions corresponding to a plateau or a plateau (both sides separated by broken lines).

Next, the operation of the reduction projection exposure apparatus of the present invention will be described. In this method, the exposure area 1313 includes two masks 1314a and 1314b.
It is divided into This is, for example, the memory mat area 13
13i and j and the peripheral circuit unit 1313k. These areas often have a step as shown in the normal drawing (FIG. 13A). In such a case, each area is formed as a pattern on a separate mask, and the masks are separately moved in the Z-axis (same as the optical axis) direction so that an image of each area is formed on the resist film on the wafer. Exposure is performed at the same time while adjusting to form an image on the corresponding plane.

In this case, a plurality of light source lamps or the like having the same wavelength are used as the light source. If there is a difference between both wavelengths, the projection lens system 1315 is used.
In order to avoid this, the effect of the chromatic aberration of
The luminous flux from a single light source may be split as in the twelfth embodiment.

In this stepper, the projection lens system 1315 converts the light fluxes L ₁ and L ₂
Are common and both sides (the object side and the image side) are telecentric, so that a slight movement in the Z-axis direction of each mask changes its imaging position without changing its magnification. Can be.

(14) Embodiment 14 In the present embodiment, a phase shift exposure method (in this application, referred to as “on-mask phase shift method”) is performed by forming a transparent film for inverting the phase on a predetermined portion on the same mask. ) Is applied.

FIG. 14A is a simplified front sectional view (optical system) of the step-and-repeat type 5: 1 reduction projection exposure apparatus of the embodiment. In the figure, 1402a and b monochromatic exposure light source such as independent i-line with one another, L ₁ and L ₂ are the main beam and sub beam, 1404
a and b are illumination lens systems constituting Koehler illumination, 1414a
And b are a main mask for exposing a predetermined pattern in a lowland (on the wafer) portion, 1414b is a sub-mask for exposing a predetermined pattern in a highland portion on the wafer, and 1414x and y are synthetic quartz mask substrates. , 1414 m and n are chrome light shielding portions, 1414 p and q are main openings corresponding to the pattern, 1414 s
And t are a transparent film for phase inversion provided on the opening corresponding to the phase shifter, L ′ is a combined light beam by a half mirror,
1415 is a 5: 1 reduction projection lens system in which both the object and image sides are telecentric, and 1413k is on the wafer (wafer is 14
03) is a lowland portion, and 1413i is a highland portion on the wafer.

FIG. 14B is a top view showing a unit exposure area on the wafer 1403 and explaining the exposure method of the present invention. In FIG. 14, reference numeral 1413 denotes a unit exposure area, 1421 and 1422 denote chip areas corresponding to chips such as memories, 1423 and 1424 denote peripheral circuit portions corresponding to lowlands on the respective chips, and 1451a denotes as shown in FIG. 14A. A portion provided with an opening 1414p,
Reference numeral 1451b similarly denotes a portion provided with an opening 1414q.

FIG. 14C shows the predetermined pattern portion 1 in the lowland portion and the highland portion.
FIG. 14 is a plan view of a mask showing a specific example of a mask when 451a and b are long and thin patterns such as isolated Al wirings. This mask corresponds to a negative resist process. In the figure, reference numerals 1414p and 1414q denote opening patterns corresponding to Al wirings, 1414g and h denote slit opening patterns respectively corresponding to shifters, and 1414s and t denote phase inversion films formed thereon.

Regarding the operation of the stepper of the present embodiment,
This is exactly the same as 13 and will not be described. In this embodiment, two areas having a step can be simultaneously exposed by the on-mask phase shift method. Therefore, in a fine dimension of a DRAM having a large step as shown in the previous embodiment 8, resolution can be reduced in a normal process. This is effective when applied to an exposure step that cannot be performed. The method is valid for any type of on-mask phase shift method.

(15) Embodiment 15 This embodiment is directed to a cycle or an approximate cycle to which the multi-mask phase shift method or the on-mask phase shift method of the present invention is applied.
The present invention relates to a method for forming an Al wiring pattern and the like.

FIGS. 15A to 15C are wafer top views schematically showing Al periodic patterns (on the wafer) to which the present embodiments 15A to 15C are applied.
In FIG. 15A, 1503 is the upper surface of the wafer, 1553 is the unique pattern, 1559 and 1560 are adjacent patterns, and 1551 and 1552 are the remaining periodic patterns. In FIG.15B, 1556 is a unique pattern, 1561 and 1562 are adjacent patterns 1554 and
1555 is the remaining periodic pattern, and 1503 is the upper surface of the wafer.
In FIG. 15C, 1558 is a peculiar pattern corresponding to the end of the periodic Al wiring pattern, 1557 is the remaining periodic pattern,
Is the upper surface of the wafer.

FIG. 15D is a layout or superimposed layout diagram on the mask corresponding to FIG. 15A described above, wherein a solid line indicates the boundary of the opening pattern of the main mask, and a broken line indicates the boundary of the opening pattern of the sub-mask. In the case of the on-mask phase shift mask, the solid line corresponds to the opening pattern with the phase shift amount “0”, and the broken line corresponds to the opening pattern with the phase shift amount “π”. The dimensions are as follows: Figures 15D to 15F show that the Al line width is 0.3 to 0.4 μm,
Each figure is drawn at the same magnification.

In FIG. 15D, 1514 is a quartz mask substrate, 1559a is a main opening pattern corresponding to the Al line 1559 on the main mask, and 1559b is associated therewith (hereinafter mainly described in the case of the multi-mask phase inversion shift method). Shifter pattern on sub-mask, 1553b is main opening pattern on sub-mask corresponding to Al line 1553, 1560a is main opening pattern on main mask corresponding to Al line 1560, 1560b is shifter on sub-mask accompanying it The pattern 1559c is an auxiliary opening pattern for canceling a ghost that may be caused by being at the same distance from the openings 1559a and 1560a corresponding to the Al lines on both sides.

FIG. 15E is a mask layout diagram corresponding to FIG. 15B, similar to FIG. 15D. In the figure, reference numeral 1514 denotes a mask substrate, 1556a denotes a main opening (on the main mask) corresponding to the Al line 1556 in FIG. 15B, 1556b and b 'denote shifter patterns on the sub-mask associated therewith, 1561b and 1562b Are opening patterns on the sub-mask corresponding to 1561 and 1562, respectively.

FIG. 15F is a mask layout diagram corresponding to FIG. 15C, similar to FIGS. 15D and 15E. In the figure,
1558a is a main opening on the main mask corresponding to the end Al wiring 1558 in FIG. 15C, 1558b is a shifter pattern on the corresponding sub-mask, and 1557b is a sub-mask corresponding to one of the inner Al lines 1557. The upper main opening 1514 is a mask substrate.

Next, how to use these masks will be described.
First, FIG. 15C and FIG. 15F will be described. In such a dense periodic pattern, a mask layout of the type shown in FIG. 6H is used.
As for the outer half of 1558, there is no adjacent shifter pattern (complementary main pattern), so that the line width becomes broad. Therefore, an additional accompanying opening pattern (shifter) 1558b is provided so as to cancel the unnecessary spread.

Next, the case of FIGS. 15B and 15E will be described. In such a periodic pattern, “π” etc. alternately use a mask layout having a phase shift equivalent thereto as shown in FIG. 6H, but when only one protrudes as shown in FIG. 15B, or In the case of protruding every few lines (or one line), there is a problem that the Al wiring or the like 1556 of the protruding portion becomes undesirably thick for the same reason as described above. To avoid this, shifter patterns 1556b and b 'are provided.

Next, the case of FIGS. 15A and 15D will be described. Even in such a periodic pattern, “π” is alternately applied as shown in FIG. 6H.
A mask layout having a phase shift of (or its equivalent) is used, but when only one is short as shown in FIG. A first problem occurs that the inside of each of the wirings 1559 and 1560 becomes undesirably thick. Further, when the valleys of the amplitude shown in FIG. 9B are overlapped with each other, a second problem that a ghost appears in the middle thereof occurs. To solve the first problem, the associated shift patterns 1559b and 1560b are provided. In order to solve the second problem, an auxiliary pattern 1559c (auxiliary accompanying pattern) is provided.

The above techniques described above are particularly effective when applied to a dense pattern portion in the following process. That is, 7I
Processes in the figure 7P2, 7P4, 7P7, 7P10, and 7P1
2. Exposure process in Example 8: 2, 4, 9, 11, 18, 20,
And 22 mag. The mask and exposure method may be either on-mask phase shift or multi-mask phase shift.

(16) Embodiment 16 This embodiment is an explanation of a photoresist used for exposing a wafer of the present invention. The resist can be selected from FIG. 16A according to the wavelength of the monochromatic ultraviolet light source used for exposure.

The resist is applied uniformly over the entire upper main surface of the wafer to a thickness of, for example, 0.6 μm by a spin coater.

(17) Embodiment 17 This embodiment relates to an improvement of a mask used for a pair mask or a multi-mask phase shift method.

Figure 17A shows a step-and-repeat type using the same method
FIG. 2 is a schematic sectional view of a main part of an optical system of a 5: 1 reduction projection exposure apparatus. In the figure, 1702 is Hg lamp i rays ultraviolet monochromatic light source of, 1704 illumination optical lens system for forming a Koehler illumination, L is the illumination light, L ₁ and L ₂ are split illumination light, 1714a and b are primarily A main mask and a sub-mask corresponding to the divided light and the sub-divided light, 1751a is a first main opening pattern corresponding to the first isolated pattern, 1754b is a second main opening pattern corresponding to the second isolated pattern, 1752a And 1753a are second sub-opening patterns (ie, shifters) associated with the second main opening pattern, 1755b and 1756b are first sub-opening patterns associated with the first main opening pattern, 1740a and b
Are optical path length adjusting means or adjusting chambers as shown in FIG. 5C, L 'is synthetic light, 1715 is a 5: 1 reduction projection lens system, 1
Reference numeral 703 denotes a wafer to be exposed, and reference numeral 1709 denotes a photoresist film uniformly coated on the wafer 1703.

FIG. 17B is a layout plan of a superposed mask showing how main opening patterns corresponding to a large number of isolated patterns are distributed on the main mask and the sub-mask. In the same drawing, a mask substrate when 1714a is overlaid on 1714b, a pattern portion (one shot) to be simultaneously exposed, and a solid circle in a dashed square are the main mask 1714a.
The upper main opening patterns and circles indicated by broken lines are sub-masks 1714b.
These are the upper main opening patterns.

As described above, by uniformly distributing the main opening patterns on both masks, heating of both masks by exposure light can be made substantially the same and uniform.

(18) Embodiment 18 FIG. 18A is a step-and-repeat 5: 1 reduced projection for implementing a multi-mask phase shift method (pair mask phase shift method) according to an embodiment of the present invention. FIG. 2 is a schematic front sectional view of an exposure optical system of an exposure apparatus (stepper).
In the figure, 1802 is Hg lamp i-line exposure light source (details Example-10) such as a, L is the original exposure light beam, L ₁ is the main exposure light beams split, L ₂ is also divided subsidiary exposure Luminous flux, 1851
Is a prism that houses the half mirror 1806 for light splitting, 1840
2A, FIG. 5C, or a phase or optical path length adjusting means or shifter, 1808a and 1 as shown in the example below.
807b is a mirror for main beam and sub beam, 1804a and 1
804b is a prism for accommodating a condenser 6 forming a Koehler illumination (Khler), and 1840 is a prism 20 in FIG. 2A.
5, a phase adjusting or optical path length adjusting means as shown in FIG. 5C or the following example, ie, a shifter, 1808a and 1807b respectively form a main beam and a sub beam mirror, and 1804a and 1804b respectively form a Koehler illumination (Khler). Condenser lenses, 1814a and 1814b are main and sub-masks, respectively, 1854 is a combining prism that houses a combining half mirror 1813,
L 'is a light beam for synthesis, and 1815 is a 5: 1 reduction projection lens system which is telecentric on both the object side and the image side. Reference numeral 1803 denotes a wafer to be exposed, and 1881 denotes a wafer stage as shown in FIGS. 5A and 19A.

In this embodiment, since the main exposure optical axis passing through the wafer and the main illumination optical axis passing through the light source are orthogonal to each other, it is relatively easy to configure the optical paths of the main and sub-divided light beams substantially symmetrically. I can do it.

It is needless to say that the present apparatus can be widely applied not only to the phase shift method but also to the exposure method using two masks described in other embodiments of the present application.

(19) Embodiment 19 In this embodiment, a specific example of an exposure illumination system for performing the pair mask phase shift method (multi-mask phase shift method) of the present invention and another example of the exposure optical system will be described. Will be described.

FIG. 19A shows a step-and-repeat type of this embodiment.
FIG. 2 is a schematic front sectional view of an exposure optical system of a 5: 1 reduction projection exposure apparatus. In the figure, 1902 is an ultra-high pressure mercury lamp, 1982 is an ellipsoidal mirror, L is an original exposure illumination light beam, 1983 is a first reflecting mirror (for example, an Al mirror), 1985 is a shutter, 1986 is a fly-eye lens, and 1987 is an aperture. , 1988 is a filter (for example, a short cut filter), 1984 is a second reflecting mirror (for example, a cold mirror), 1904 is a condenser lens constituting Koehler illumination, and 1906 is the original exposure light beam L and the main and auxiliary exposure light beams L. _1, a half mirror for splitting the L _2, 1940 another optical path length adjusting means shown in the embodiments or phase shift plate (205 FIG. 2A, the Figure 5A 540a, b others), 1907b is sub beam L Deflection mirror for ₂ ; 1914, a mask on which the main pattern and sub-pattern are mounted; 1961, XYZ
And θ directions more mask holder for adjusting the inclination, 1961C is the opening of the center, each of the object-side projection lens system 1964a and b corresponding to the main and sub light beams, 1949A deflection mirror for main luminous flux L ₁ , 1913 are combining half mirrors for combining the main light beam L ₁ and the sub light beam L ₂ to obtain a combined light L ′.
1954 is a combining prism for storing a half mirror,
1915 is an image-side lens system that forms a part of a 5: 1 reduction projection lens system configured to be telecentric on both the object side and the image side separately from the previous object-side lens systems 1964a and 1964b (similar to Embodiment 11), 1903 is a wafer to be exposed, 1976 is a wafer suction table also serving as a θ drive table, 1977 is a vertical direction, that is, a Z-axis moving table,
Reference numeral 1979 denotes one direction in the horizontal direction, that is, an X-axis slide, and 1980 denotes another direction in the horizontal direction, that is, a Y-axis slide.

In the present embodiment, since there is only one mask substrate, there is no need for alignment between the main and sub masks.

(20) Embodiment 20 This embodiment describes a two-dimensional locally variable shifter plate which can be used as an optical path length adjusting means or a shifter plate shown in other embodiments.

FIG. 20A shows the variable shifter of the present embodiment,
FIG. 4 is a simplified front sectional view of a stepper when replacing or adding to 1940. In the figure, 2002 is an ultraviolet or far-sighted light source as shown in FIGS. 10A and 19A, L is the original exposure light flux, and 2091 is the coordinates (x, y) of the original exposure light flux on the field.
A phase detector or scanner for measuring the phase of
2006 half mirror for splitting the original exposure light beam L to main luminous flux L ₁ and sub beam L _2, 2040 is the phase of the same coordinates of the phase and sub beam L ₂ of the coordinate main luminous flux L ₁ (x, y) Two-dimensional variable phase shift plate or shifter for locally setting (for each minute portion) the difference Δφ (x, y) between L ₁ (x, y) and L ₂
(X, y) shows a portion of the light beams L ₁ and L ₂ of the coordinate (x, y) at.
2014 is a mask in which the main pattern and sub-pattern are mounted in isolated places on a single mask. The figure shows that the thickness of each part of the mask is different and the phase shift when passing through the mask is represented by coordinates (x, y ) Is exaggerated. 2049a is the main beam
Deflection mirror for L ₁ , 2013 is a combining half mirror for combining the main light beam L ₁ and the sub light beam L ₂ to obtain L ′, φ
₁ (x, y) and φ ₂ (x, y) are the phases of L ₁ (x, y) and L ₂ (x, y) on the reference plane immediately before the synthesis, respectively, and 2015 is used alone or in another lens group. A projection lens system constituting a 5: 1 reduction projection system is telecentric on both the object side and the image side. 2003 is a semiconductor wafer to be exposed, and 2092 is a phase difference Δφ over the entire exposure field (unit shot) based on the phase difference Δφ (x, y) data between the divided beams of coordinates (x, y) detected by the scanner 2091. This is a variable shifter control circuit for controlling the variable shifter 2040 to a constant uniform value.

FIG. 20B is an enlarged view of one main surface of the variable shifter 2040 of FIG. 20A. In the figure, 2040a is a large number of square transparent electrodes, and 2041 is a gap without electrodes. When the width of the gap is set to be equal to or smaller than the size corresponding to the minimum resolution dimension on the wafer, it is effective to reduce noise due to the gap. One side of the square electrode is, for example, 20 μm to 20 μm.
It is about 0 μm. Further, it is desirable that the position of the variable shifter 2014 on the optical path is near the optical axis of the optical member by which the phase variation is to be compensated. That is,
If the largest cause of the phase variation in a single shot is the mask substrate, it is effective to dispose it on the optical axis near the mask.

FIG. 20C is a sectional view taken along line XX of the variable shifter in FIG. 20B. In this figure, reference numeral 2042 denotes an electro-optic crystal having a Pockels effect, which is one of those shown in FIG. 20D, 2040a and 2040a are opposing square transparent electrodes (segments), and 2043 is a transparent insulating film. . This insulating film
In 2043, a transparent wiring having a width equal to or smaller than the minimum resolution (on a wafer) is formed so that a desired voltage can be independently applied to each segment. Variable shifter control circuit
The 2092 compensates for the variation of the phase difference Δφ within a single shot, that is, a single step exposure region, by controlling the voltage of a large number of segments via these wirings.

(21) Literature to supplement the description of the present application Logical explanation on the on-mask phase shift exposure method,
The method of forming the mask, the method of calculating the pattern, the experimental data, and the like are described below, and will be described in the embodiments of the present application. That is, Japanese Patent Application No. 63-2953
No. 50 (filed on November 22, 1988) and Japanese Patent Application No. 1-2572
No. 26 (filed on October 2, 1999) and corresponding US patent application 07 / 437,268 (filed on November 16, 1989), Japanese Patent Publication No. 62-50811, "Nikkei Micro Devices" 1990
May 2005, pp. 74-75, "Improving Resolution in Photolithography with a Phase Shifting Mask" by Levenson et al. Devices ED-29, Volume 12, Issued December 1982, pages 1828-1836 (“Improving Resolution in Photolithograph with a
Phase-Shifting Mask ", Levenson et al, IEEE Transac
tion on Electron Devices, vol.ED-29, No.12 December
1982, P. 1828-1836), "Correction of projected image distortion of a photomask pattern for 1 μm process" by Ito et al., Transactions of the Institute of Electronics, Information and Communication Engineers, May 1985, vol. J 68-C No. 5, pp. 325-332. .

Japanese Patent Application Laid-Open No. Sho 62-171123 discloses an exposure illumination system using a high-pressure mercury lamp or the like, which will be described in the embodiments of the present application.

Japanese Patent Application Laid-Open No. 61-22626 discloses a configuration of a projection lens system having a double-sided telecentric structure.

Japanese Patent Application Laid-Open No. Sho 61-43420 discloses a technique for producing a mask using an electron beam, and this is incorporated in the description of the present embodiment.

[Effects of the Invention] Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

In a method of manufacturing a semiconductor device in which a mask pattern is exposed on a semiconductor wafer to form a pattern, a portion where the pattern expands due to light interference and is exposed, such as inside an L-shaped opening corner, is removed. Since the auxiliary light shielding pattern is provided in the vicinity thereof and the light amount is adjusted, a semiconductor device with high pattern accuracy can be manufactured.

[Brief description of the drawings]

FIG. 1A is an overall view of a phase shift mechanism provided in an exposure apparatus which is I of Embodiment 1 of the present invention. FIG. 1B is an enlarged cross-sectional view of the mask of the above embodiment of the present invention. (A) and (b) are plan views of a pair of circuit patterns formed on the mask. FIG. 1C (c) is a plan view of a circuit pattern obtained by synthesizing the pair of circuit patterns. FIGS. 1 (a) to 1 (g) are explanatory diagrams showing the amplitude and intensity of light transmitted through a transmission region of the circuit pattern shown in FIGS. 1 (a) and 1 (b), respectively. FIGS. ) Is a plan view of a pair of alignment marks formed on the mask, FIG. 1E (c) is a plan view of a circuit pattern obtained by synthesizing the pair of alignment marks, and FIG. 1F (a). And (b) is a plan view showing another example of a pair of circuit patterns formed on the mask II of Example 1 of the present invention. FIG. 1F (c) is a plan view of a circuit pattern obtained by synthesizing the pair of circuit patterns, and FIGS. 1G (a) to (g) are circuits shown in FIGS. 1 (a) and 1 (b). FIGS. 1H and 1B are diagrams illustrating amplitude and intensity of light transmitted through a transmission region of a pattern, respectively. FIGS. 1H and 1B are diagrams of a pair of circuit patterns formed on a III mask according to Embodiment 1 of the present invention. FIG. 1H (c) is a plan view of a circuit pattern obtained by synthesizing the pair of circuit patterns, and FIGS. 1I (a) to (e) are plan views of FIG. 1H (a). FIG. 1J is an explanatory diagram showing the amplitude and intensity of light transmitted through the transmission region of the circuit pattern shown in FIG. 1B. FIGS. 1J to 1D show the amplitude of light transmitted through the transmission region of the conventional mask. FIG. 1K (a) to (d) show the intensity of light transmitted through a transmission region of a conventional mask provided with a transparent film. Is an explanatory diagram showing an intensity, respectively. FIG. 2A is a main part configuration diagram of an exposure optical system that is Embodiment 2 of the present invention, and FIGS. 2B (a) and (b) are main part plan views each showing an example of a pattern configuration of the mask in FIG. 2A. , (C) is a plan view of a desired pattern formed by the patterns, FIGS. 2C (a) and (b) are main part plan views each showing an example of the pattern configuration of the mask in FIG. 2A, and (c) is a plan view thereof. 2D is a plan view of a desired pattern formed by the pattern. FIGS. 2D and 2B are main part plan views each showing an example of the pattern configuration of the mask in FIG. 2A. FIG. 2C is a desired pattern formed by the pattern. 2E (a) to (g) are explanatory diagrams showing the amplitude and intensity of light transmitted through the transmission region of the mask in FIG. 2B, and FIGS. 2F (a) to (h) are FIG. 2C. FIG. 2G is an explanatory diagram showing the amplitude and intensity of light transmitted through the transmission region of the mask of FIG. 2) is an explanatory diagram showing the amplitude and intensity of light transmitted through the transmission region of the mask shown in FIG. 2D, FIG. 2H is a cross-sectional view of the mask, and FIGS. 2I (a) to (c) show the apparatus of the present invention. FIG. 3A is an explanatory view of a pattern alignment method used in the present invention. FIG. 3A is a step-and-step diagram according to Embodiment 3 of the present invention.
FIG. 3B is a schematic front sectional view showing an outline of an exposure optical system of a repeat type 5: 1 reduction projection exposure apparatus, which corresponds to a periodic or quasi-periodic line-and-space pattern of the embodiment of the present invention. FIG. 3C is a cross-sectional view of a mask, FIG. 3C is a main mask pattern (positive mask) corresponding to the periodic pattern having steps in the above embodiment, and FIG. FIG. 3C is a plan view of the synthetic aperture pattern, FIG. 4D is a cross-sectional view of a periodic step portion of the semiconductor integrated circuit device being manufactured on the wafer to be exposed, and FIG. The phase difference φ between L ₁ and L ₂ is (2n + 1) π
FIG. 3E is a diagram showing a state of a shift of an image plane corresponding to the main and sub-patterns when shifted to the front and back. FIG. FIG. 3E (b) is a plan view of a phase matching opening pattern formed in the sub-pattern portion, and FIG. 3E (c) is a projection pattern when these are combined. is there. FIG. 4A is a schematic sectional view of a stepper device according to Embodiment 4 of the present invention. FIG. 5A is a schematic front sectional view of an exposure projection optical system of a step-and-repeat type 5: 1 reduction projection exposure apparatus of Embodiment 5 of the present invention, and FIG. 5B is an exposure light source and illumination (exposure) of the apparatus. FIG. 5C is an enlarged cross-sectional view of a phase difference setting unit of the apparatus, and FIG. 5D is a top view of a wafer holding unit of the apparatus. FIG. 6A is a plan view of a mask pattern corresponding to the isolated strip pattern according to the sixth embodiment of the present invention, and FIG. 6B is a mask corresponding to the isolated square pattern according to the sixth embodiment of the present invention.
FIG. 6C is a plan view of a mask pattern corresponding to the isolated square pattern according to the modification of FIG. 6B, and FIG. 6D is an “L” -shaped pattern according to Embodiment 6 of the present invention. 6E is a plan view of a corresponding mask pattern, FIG. 6E is a plan view of a mask pattern corresponding to the “L” -shaped pattern according to the modification of FIG. 6D, and FIG. 6F is a plan view of the sixth embodiment of the present invention. FIG. 6G is a plan view of a mask pattern corresponding to the bent isolated strip pattern according to the modified example of FIG. 6F, and FIG. 6H is a plan view of a mask pattern corresponding to the bent isolated strip pattern according to the sixth embodiment of the present invention. FIG. 6 is a plan view of a mask pattern corresponding to the uniform periodic strip pattern according to FIG. FIG. 7A is a top view of a wafer showing a light emitting step according to Embodiment 7 of the present invention, FIG. 7B is a plan view showing a unit exposure area in an exposure method according to Embodiment 7 of the present invention, and FIGS. The drawings are flow sectional views showing a positive process according to Embodiment 6 of the present invention, FIGS. 7F to 7H are flow sectional views showing a negative process according to Embodiment 7 of the present invention, and FIG. 7I is the present invention. Twin well SRAM according to the seventh embodiment of the present invention
7J to 7P are cross-sectional views of the SRAM wafer process corresponding to FIG. 7I of the present invention, and FIG. 7Q is a plan layout diagram of the chip region of the SRAM. is there. 8A to 8O are cross-sectional views showing a wafer process of a DRAM according to Embodiment 8 of the present invention. FIG. 8P is a plan layout view of a chip area of the DRAM. FIG. 8Q is a memory cell area of the DRAM. FIG. 4 is a plan layout diagram of a unit translation cycle of FIG. FIG. 9A is a graph for explaining the distribution of the amplitude intensity and the energy intensity of the light when the phases of the adjacent patterns are the same, and FIG. 9B is the same as FIG. To)
FIG. 9C is a schematic sectional view of an optical system for explaining the principle of reduced projection according to the present invention. FIG. 10A is a table showing various conditions of a monochromatic light source for exposure used in the exposure method of the present invention. FIG. 11A is a simplified front sectional view of a 5: 1 reduction projection exposure apparatus according to an eleventh embodiment of the present invention in which all the projection lens systems are made common using the object side telecentric configuration. FIG. 12A is a simplified front sectional view of a mask inspection apparatus according to Embodiment 12 of the present invention. FIG. 13A shows a step-and-repeat type of Embodiment 13 of the present invention using two light sources that are not coherent with each other.
FIG. 2 is a simplified front sectional view of a 5: 1 reduction projection exposure apparatus. FIG. 13B is a plan view of a mask or a wafer showing a layout of unit exposure areas exposed by the exposure method of FIG. 13A. FIG. 14A is a simplified front sectional view of a step-and-repeat type reduction projection exposure apparatus (using mutually non-coherent light sources) for explaining an exposure method according to Embodiment 14 of the present invention. 14A is a plan layout diagram of a unit exposure area (mask or wafer) in the method of FIG. 14A, and FIG. 14C is a plan pattern diagram of a mask used in the method of FIG. 14A. FIG. 15A is a plan view of a pattern on a wafer corresponding to the quasi-periodic pattern of Embodiment 15 of the present invention. FIG. 15B is a plan view of a pattern on the wafer corresponding to another quasi-periodic pattern of the above embodiment. The drawing is a pattern plan view on a wafer corresponding to still another quasi-periodic pattern of the above embodiment. FIG. 15D is a plan layout diagram or a superimposed plan layout diagram of a mask in the on-mask or multi-mask phase shift method corresponding to the pattern on the wafer in FIG. 15A. 15E and 15F are similar plan layout diagrams corresponding to FIGS. 15B and 15C, respectively. FIG. 16A is a list of photoresists used in the practice of the present invention. FIG. 17A shows two accompanying patterns according to the embodiment 17 of the present invention.
FIG. 17B is a simplified front sectional view of a step-and-repeat type 5: 1 reduction projection exposure apparatus showing an exposure method separately mounted on one mask, and FIG. 17B is a superimposed mask pattern diagram for explaining the same method. . FIG. 18A is a front sectional view of a simplified multi-mask stepper according to Embodiment 18 of the present invention. FIG. 19A is a front sectional view of a pair mask (pattern) exposure apparatus (stepper) using a single mask substrate according to the nineteenth embodiment for explaining the configuration of the individual illumination light source of the exposure apparatus of each embodiment of the present invention. . 20A is an overall configuration diagram of a two-dimensional phase matching device according to Embodiment 20 of the present invention, FIG. 20B is a top view of the two-dimensional phase shift plate, and FIG. 20C is a cross-sectional view of the two-dimensional phase shift plate. FIG. 20D is a list of crystals having an electro-optical effect used for the phase shift plate.

Claims (4)

(57) [Claims] A first light transmission pattern provided in a light shielding region formed on a mask substrate and provided in the vicinity of the first light transmission pattern, and having a phase with respect to light passing through the first light transmission pattern. A method for manufacturing a semiconductor device, comprising a step of forming a circuit pattern by exposing a photoresist film on a semiconductor wafer by a reduction projection exposure apparatus using an optical mask having an inverted second light transmission pattern. In the resist film, an auxiliary light shielding region is provided near a pattern peripheral region in the first light transmission pattern corresponding to a region where an exposure amount becomes excessive due to light interference, and light transmitted through the first light transmission pattern is provided. A method for manufacturing a semiconductor device, characterized in that a part is blocked. 2. An auxiliary light transmitting area is provided near a pattern peripheral area outside the first light transmitting pattern corresponding to an area where an exposure amount is insufficient in the photoresist film, and transmits the first light transmitting pattern. 2. The method according to claim 1, wherein a part of the light is emphasized. 3. The first light transmission pattern is L-shaped,
3. The method of manufacturing a semiconductor device according to claim 1, wherein the auxiliary light shielding region having a size equal to or less than a resolution is formed at or near a corner in the first light transmission pattern. 4. The method according to claim 1, wherein said second light transmission pattern has a size smaller than a resolution limit.