JP3161425B2 - Method of forming STI - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an STI (Shallow
Trench Isolation), more specifically,
The present invention relates to a method of forming an STI by polishing and flattening an insulating film in which the STI is embedded without unevenness when forming the STI.

[0002]

2. Description of the Related Art In recent years, as LSI miniaturization progresses, element isolation is changed from LOCOS to STI (Shallow Trench).
ch Isolation). In the STI, trenches (Trench) are formed in a semiconductor substrate, and an insulating film is buried in the trench, thereby performing electrical insulation between elements.

Here, a conventional method of forming an STI will be described with reference to FIGS. FIGS. 5A to 5D and FIGS. 6E to 6H are cross-sectional views showing the cross-section of the substrate in each step when forming the STI according to the conventional method. First, as shown in FIG. 5A, a pad oxide film 22 having a thickness of 200 形成 is formed on a semiconductor substrate 21, for example, a silicon substrate 21, and then a polishing stopper is formed on the pad oxide film 22 by CMP. A film having a low polishing rate, for example, a nitride film 23 is formed to a thickness of 1500 °. The role of the pad oxide film 22 is to alleviate the stress generated between the nitride film 23 and the silicon substrate 21 and to protect the substrate when the nitride film 23 is removed. Normally, the pad oxide film 22 is formed by thermal oxidation that can easily obtain a high-quality film. Next, a mask 24 is selectively formed in a region to be a diffusion layer by a known photolithography technique.

[0005] Next, as shown in FIG.
The stopper film 23 and the pad oxide film 22 in the region not covered with 4, that is, the element isolation region are removed by an anisotropic etching technique. Further, the semiconductor substrate 21 is 3000
Only by anisotropic etching, a trench 25 reaching the semiconductor substrate 21 is formed in the element isolation region. Subsequently, the mask 24 is removed.

[0005] Next, as shown in FIG. 5 (c), an oxide film having a thickness of 6000 ° is formed as an insulating film 26 over the entire surface of the wafer by CVD, and the trench 25 is buried. Fine and steep projections 27 are formed on the small diffusion layer pattern.

Next, as shown in FIGS. 5D to 6E, the oxide film 26 on the nitride film 23 is formed on all the diffusion layer regions by CMP (Chemical Mechanical Polishing).
Is polished, and finally, as shown in FIG.
6 is removed.

[0007] In this conventional CMP polishing, a polishing liquid in which silica (SiO 2) abrasive grains having an average particle diameter of 100 nm are dispersed in an alkaline aqueous solution, for example, a potassium hydroxide aqueous solution having a pH of about 10 is used for the slurry. As the polishing pad, for example, an IC-1000 / SUBA400 laminated pad manufactured by Rodale is used. The polishing condition is, for example, a polishing load of 7
psi, the number of rotations of the wafer and the polishing table are both 20
rpm. In ordinary CMP using a slurry of silica abrasive grains, polishing proceeds faster in a place where the pattern density of the projections is small, and becomes slow in a place where the pattern density of the projections is large. Such variation in polishing is not a problem as long as polishing can be stopped by the nitride film 23 serving as a stopper.

However, in the case of slurry using silica as abrasive grains, the selectivity of the polishing rate (oxide film / nitride film) is only about 3, and the nitride film does not sufficiently function as a stopper, and is used in a place where polishing is fast. 1000Å ~ 200 in a slow place
Å Polished. As a result, the remaining thickness of the nitride film on the diffusion layer varies widely, such as 500 ° at a thin portion and about 1300 ° at a thick portion.

Next, as shown in FIG. 6G, when the nitride film 23 is removed by etching, an STI is formed. For etching, usually the selectivity with the oxide film is high,
A wet etch with phosphoric acid is used. However, since the thickness of the nitride film varies, the height of the upper surface of the formed STI is obtained by adding the thickness of the pad oxide film to the thickness of the nitride film by 200 ° based on the height of the silicon surface in the diffusion layer region. 700
It varies from ~ 1500Å.

After that, as shown in FIG. 6H, when the oxide film is wet-etched with hydrofluoric acid or a solution containing hydrofluoric acid to remove the pad oxide film, the STI portion is etched by about 1200 ° and becomes lower. . As a result,
The height of the top surface of the STI is based on the height of the diffusion layer region,
−500 ° / + 300 °, and a step occurs. If there is a step, the thickness of the photoresist will vary when patterning the gate electrode using lithography technology, and the gate dimensions will fluctuate, and the gate electrode material will remain on the step during subsequent etching. Problems may occur (SS Cooperman et al. J. Electrochm. Soc., Vol.
142, pp3180-3185, 1995).

Although the size of the step can be adjusted by the amount of wet etching or the thickness of the initial nitride film, the height of the diffusion layer and the upper surface of the STI is changed in all patterns because of variations. They cannot be aligned.

In order to reduce the difference in the polishing pattern, a slurry having a high selectivity (oxide film / nitride film) for the polishing rate of the oxide film and the nitride film is required (DREvans et al., Proceeding of C).
MP-MIC, pp347-350, 1998.). As a slurry capable of providing a high selectivity, a slurry using ceria (CeO2) as abrasive grains is known. However, in a slurry using ceria as abrasive grains, a phenomenon was observed in which the polishing rate decreased as the pattern became smaller (DREvans et al., Proceeding of C).
MP-MIC, pp. 347-350, 1998.), and fine and steep protrusions can hardly be polished. As a result, a polished shape as shown in FIG. 7 is obtained.

This phenomenon can be explained as follows. The average secondary particle diameter of optically measured ceria abrasive grains is typically about 300 to 400 nm, and 100 nm of silica abrasive grains.
Large compared to degree. There is a fine and steep pattern,
Where the slurry layer between the pad and wafer is thin,
Abrasive grains with small silica can enter and polishing proceeds, but ceria abrasive grains cannot enter because they are large and polishing does not proceed.

[0014]

As described above, in the CMP using only a slurry using ordinary silica as abrasive grains, the selectivity of the polishing rate (oxide film / nitride film) is only about 3, and the nitride film is not formed. Since it does not function sufficiently as a stopper, variations in polishing due to the pattern cannot be suppressed. Therefore, a step between the upper surface of the STI portion and the diffusion layer cannot be eliminated. Further, in an extreme case, there is a disadvantage that the nitride film disappears at the time of overpolishing and the bulk portion of silicon is polished. To prevent this, a slurry having a high selectivity is required. As a slurry having a high selectivity, there is a slurry using ceria (CeO2) as abrasive grains. However, with this slurry, fine and steep protrusions cannot be polished.

It is an object of the present invention to provide a method for forming an STI in which polishing variation hardly occurs.

[0016]

In order to achieve the above object, a method of forming an STI according to the present invention is a method of forming an STI on a silicon substrate, wherein a stopper layer is formed on the silicon substrate. A step of forming an STI isolation groove penetrating through the stopper layer and reaching the silicon substrate; a step of forming an insulation film on the silicon substrate while filling the STI isolation groove with an insulation film; A first insulating film removing step of removing a steep unevenness by a removing method to flatten the insulating film, and a second removing an insulating film up to the stopper layer by a second removing method different from the first removing method. The method is characterized by including an insulating film removing step and a step of removing the stopper layer to form STI.

In order to achieve the above object, another method of forming an STI according to the present invention is a method of forming an STI on a silicon substrate, comprising the steps of: forming a stopper layer on a silicon substrate; Forming a STI isolation groove that reaches the silicon substrate through the layer, forming a non-SOG insulation film on the silicon substrate while embedding the STI isolation groove with the non-SOG insulation film, Forming an SOG insulating film on the film, and removing S
A first insulating film removing step of removing the OG insulating film, a second insulating film removing step of removing the non-SOG insulating film up to the stopper layer by a second removing method different from the first removing method, and a stopper layer And forming a STI by removing the STI.

For example, in the first insulating film removing step, non-C
The insulating film is removed by MP processing, and in the second insulating film removing step, the insulating film is removed by CMP processing. that time,
In a first insulating film removing step for removing an insulating film by non-CMP processing, reflow processing or etch-back processing is used.

Further, in the first insulating film removing step, the insulating film is planarized by removing the steep irregularities of the insulating film using the first abrasive, and then in the second insulating film removing step, the first insulating film is removed. The insulating film is polished to the stopper layer and removed using a second polishing agent different from the above polishing agent to form STI. In the first insulating film removing step, the first polishing agent is used to remove sharp irregularities in the insulating film to planarize the insulating film, and then to remove the second insulating film.
In the insulating film removing step, the insulating film is polished and removed up to the stopper layer using a second abrasive having an average particle diameter larger than the average particle diameter of the abrasive grains of the first abrasive. At that time, for example, the first
The average particle size of the abrasive particles of the abrasive is less than 200 nm, and the average particle size of the abrasive particles of the second abrasive is 200 nm or more.

The first abrasive is an abrasive for silica abrasive grains, and the second abrasive is an abrasive for non-silica abrasives. For example, an abrasive of ceria abrasive is used as an abrasive of non-silica abrasive.

In the case where the insulating film and the stopper layer are a silicon oxide film and a silicon nitride film, respectively,
Has a small polishing rate selectivity (silicon oxide film / silicon nitride film) between the silicon oxide film and the silicon nitride film, and the second abrasive has a higher polishing rate selectivity than the first abrasive. . Preferably, the polishing rate selectivity of the second abrasive is at least 10 times greater than the polishing rate selectivity of the first abrasive.

The time for removing the insulating film in the first insulating film removing step is shorter than the time for removing the insulating film in the second insulating film removing step.
The amount of the insulating film removed in the first insulating film removing step is smaller than the amount of the insulating film removed in the second insulating film removing step in terms of the polishing amount of the film to be polished on the wafer having no pattern.

[0023]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Embodiment 1 This embodiment is an example of an embodiment of a method for forming an STI according to the present invention, and includes FIGS. 1 (a) to 1 (d) and FIG.
FIGS. 4E and 4F are cross-sectional views each showing a cross section of a substrate when forming an STI according to the STI forming method of the embodiment. In the silicon wafer used in this embodiment, as shown in FIG. 1A, a CMP is performed on a diffusion layer region of a semiconductor substrate 1 through a pad oxide film 2 having a thickness of 200 °.
Sometimes a film 3 serving as a stopper, for example, a nitride film having a thickness of 100
0 ° is deposited. The element isolation region has a depth of 300
A trench 5 having a thickness of 0 ° is formed, and an insulating film 4, for example, an oxide film having a thickness of 6000 ° is formed thereon.
Fine and steep protrusions 6 are formed on the diffusion layer region.

First, the first polishing is performed to flatten a fine and steep step as shown in FIG. In the first polishing, the slurry is silica (Si) having an average particle diameter of 100 nm.
O2) Use abrasive grains dispersed in an alkaline aqueous solution, for example, an aqueous solution of potassium hydroxide having a pH of about 10. The polishing pad is, for example, Rodel IC-1000 / SUBA4
Use 00 layer pad. Polishing conditions are, for example,
The polishing load is 7 psi, and the rotation speed of both the wafer and the polishing table is 20 rpm.

In the CMP using a slurry of silica abrasive grains, a portion having a small pattern density, such as a fine and steep convex portion, has a large force applied per unit area and is polished quickly. When the part is almost flat,
Polishing is stopped before the nitride film is exposed. At this time, in a place where the pattern density of the protrusions is large, the polishing has hardly progressed yet.

Next, a second polishing is performed to remove the oxide film on the nitride film on all the diffusion layer regions as shown in FIG. In the second polishing, the slurry has an average particle diameter of 300 n.
A material obtained by dispersing ceria (CeO2) abrasive grains of m in a neutral dispersion medium is used. The polishing pad is, for example, a Rodale IC-
Use a 1000 / SUBA400 laminated pad. The polishing conditions are, for example, a polishing load of 7 psi, and the rotation speeds of both the wafer and the polishing table are 20 rpm. FIG.
(C) shows a state during polishing at this time. While the oxide film in the place where the pattern density is large and polishing is slow is being polished,
In places where the pattern density is small and polishing is fast, the nitride film is exposed and polished. However, the polishing rate selectivity (oxide film / nitride film) is 150
The polishing amount of the nitride film can be almost negligibly reduced to 20 ° at 1000 ° when polished with silica abrasive grains, and uniform polishing is possible.

The two polishing steps may be performed by separate polishing apparatuses, or in an apparatus having a plurality of polishing tables, two polishing tables may be used to perform the polishing step continuously. Further, only one slurry may be switched on one polishing table.

Next, as shown in FIG. 2E, the nitride film 3 is removed by etching. Usually, wet etching with phosphoric acid, which has a high selectivity to an oxide film, is used for etching. Since the nitride film 3 is hardly polished, the height of the upper surface of the formed STI based on the silicon surface in the diffusion layer region is 1200 ° which is the thickness of the nitride film plus 1000 ° and the thickness of the pad oxide film which is 200 °. It does not vary.

Next, as shown in FIG. 2F, when the oxide film is wet-etched with hydrofluoric acid or a solution containing hydrofluoric acid to remove the pad oxide film, the STI portion becomes 12%.
It is etched by about 00 ° and becomes lower. As a result, ST
The height of the upper surface of I is almost the same as the height of the diffusion layer region.

Embodiment 2 This embodiment is another example of the embodiment of the method of forming an STI according to the present invention, and FIGS. 3A to 3D show the embodiment of the present invention, respectively. FIG. 3 is a cross-sectional view illustrating a cross section of a substrate when forming an STI according to an STI forming method. In this embodiment, SOG (spin-on-glass) is used instead of silica polishing in order to eliminate fine and steep protrusions. The wafer shown in FIG. 2A is a silicon wafer formed in the same state as FIG. 1A. First, FIG.
As shown in FIG. 7, an organic SOG 13 having a thickness of 3000 ° is formed by spin coating.

Next, as shown in FIG. 3C, the film is etched back by a thickness of 4000 ° by anisotropic dry etching. In the etching at this time, it is desirable to set the etch rate of the oxide film and the etch rate of the organic SOG as close as possible in order to maintain the flattening effect of the organic SOG 13 as much as possible. With this method, global steps cannot be flattened, but fine and steep projections can be flattened.

Next, as shown in FIG. 3D, polishing is performed until the oxide film on the nitride film is removed from all the diffusion layer regions. In this polishing, the slurry has an average particle diameter of 300 n.
A material obtained by dispersing ceria (CeO2) abrasive grains of m in a neutral dispersion medium is used. Polishing pads include, for example, Rodale IC
Use a -1000 / SUBA400 laminated pad. The polishing conditions are, for example, a polishing load of 7 psi, and the rotation speeds of both the wafer and the polishing table are 20 rpm. There are no fine and steep protrusions, and high selectivity polishing can be performed without any trouble.

Embodiment 3 This embodiment is still another example of the embodiment of the method of forming an STI according to the present invention. FIGS. 4A to 4D show the embodiments of the present invention, respectively. According to the STI forming method of
FIG. 4 is a cross-sectional view showing a cross section of the substrate when forming I. FIG.
The wafer shown in FIG. 1A is in the same state as in FIG. First, as shown in FIG.
The oxide film 20 doped with 1% and having a lowered melting point is
0 ° is formed. Next, as shown in FIG.
Heat treatment for 30 minutes to reflow the oxide film 20,
Flatten fine and steep protrusions.

Next, as shown in FIG. 4D, polishing is performed on all the diffusion layer regions until the oxide film on the nitride film is removed. In this polishing, the slurry has an average particle diameter of 300 nm.
(CeO2) abrasive grains dispersed in a neutral dispersion medium is used. The polishing pad includes, for example, Rodale IC-
Use a 1000 / SUBA400 laminated pad. The polishing conditions are, for example, a polishing load of 7 PSI, and the rotation speeds of both the wafer and the polishing table are 20 rpm. There are no fine and steep protrusions, and high selectivity polishing can be performed without any trouble.

[0035]

According to the present invention, the STI is formed by removing the insulating film up to the stopper layer by the second removing method different from the first removing method, for example, to flatten fine and sharp convex portions. Since polishing is performed beforehand with slurry using ceria as abrasive grains, the oxide film can be polished at a high selectivity with respect to the nitride film of the stopper regardless of the pattern. Can be absorbed.
In addition, since the embedded oxide film thickness and the in-plane non-uniformity of the CMP are absorbed and uniform CMP becomes possible, the step between the diffusion layer region and the upper surface of the STI can be made constant, and the absolute value can be reduced. As described above, since the absolute value of the step can be reduced according to the present invention, patterning of the gate electrode by lithography and subsequent etching of the gate electrode are facilitated.

[Brief description of the drawings]

FIGS. 1A to 1D are cross-sectional views each showing a cross section of a substrate when an STI is formed according to the STI forming method of the first embodiment.

FIGS. 2 (e) and 2 (f) are FIGS. 1 (d) and 1 (d), respectively.
Subsequently, according to the STI forming method of the first embodiment, S
FIG. 3 is a cross-sectional view showing a cross section of a substrate when forming a TI.

FIGS. 3A to 3D are cross-sectional views each showing a cross section of a substrate when an STI is formed according to the STI forming method of the second embodiment.

FIGS. 4A to 4D are cross-sectional views each showing a cross section of a substrate when an STI is formed according to the STI forming method of the third embodiment.

5 (a) to 5 (d) are cross-sectional views each showing a cross-section of a substrate in each process when forming an STI according to a conventional method.

6 (e) to 6 (h) respectively show FIG. 5 (d).
FIG. 14 is a cross-sectional view showing a cross-section of a substrate in each step when forming an STI according to a conventional method.

FIG. 7

[Explanation of symbols]

 1, 7, 14, 21, 28 Semiconductor substrate 2, 8, 15, 22, 29 Pad oxide film 3, 9, 16, 23, 30 Stopper film 4, 10, 17, 26, 31 Insulating film 5, 11, 18 , 25 Trench 6, 12, 19, 27 Fine and steep protrusion 13 SOG 20 Phosphorus-doped oxide film 24 Mask

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/76

Claims (9)

(57) [Claims] An STI (Shallow Tren) is formed on a silicon substrate.
a step of forming a stopper layer on a silicon substrate, a step of forming an STI isolation groove penetrating through the stopper layer and reaching the silicon substrate, and an STI isolation with an insulating film. A process of forming an insulating film on a silicon substrate while filling a groove, and forming a steep unevenness by a CMP process using a first abrasive.
A first insulating film removing step of flattening the insulating film by polishing and removing; and a first insulating film having an average particle diameter larger than the average particle diameter of abrasive grains of the first abrasive.
A second insulating film removing step of polishing and removing the insulating film up to the stopper layer by a CMP process using a polishing agent of No. 2, and a step of forming the STI by removing the stopper layer. Forming method. 2. The abrasive of the first abrasive having an average particle diameter of 200.
nm, and the average particle size of the abrasive grains of the second abrasive is 20
The S according to claim 1 , wherein the thickness is 0 nm or more.
Method of forming TI. 3. The STI according to claim 1, wherein the first abrasive is an abrasive of silica abrasive grains, and the second abrasive is an abrasive of non-silica abrasives. Formation method. 4. The method for forming an STI according to claim 3 , wherein a polishing agent for ceria abrasive grains is used as an abrasive for non-silica abrasive grains. 5. The insulating film and the stopper layer each include:
A silicon oxide film and a silicon nitride film, wherein the first polishing agent has a small polishing rate selectivity (silicon oxide film / silicon nitride film) between the silicon oxide film and the silicon nitride film, and the second polishing agent The polishing rate selection ratio is greater than the first polishing agent .
A method for forming an STI according to any one of the preceding claims. 6. The method for forming an STI according to claim 5 , wherein the polishing rate selectivity of the second abrasive is at least ten times greater than the polishing rate selectivity of the first abrasive. 7. A method for forming an STI on a silicon substrate, comprising the steps of: forming a stopper layer on the silicon substrate; and forming an STI isolation groove penetrating the stopper layer and reaching the silicon substrate. Forming a non-SOG insulating film on a silicon substrate while filling the STI isolation trench with the non-SOG insulating film, forming a SOG insulating film on the non-SOG insulating film, and etching the SOG insulating film. Back and remove, non-SOG insulation
A first insulating film removing step of exposing the film and flattening the steep projections, and a second insulating film of removing the non -SOG insulating film up to the stopper layer by CMP using a non-silica abrasive polishing agent A method for forming an STI, comprising: a removing step; and a step of forming an STI by removing a stopper layer. 8. Ceria abrasives as abrasives for non-silica abrasives
The abrasive according to claim 7, wherein the abrasive is used.
Method for forming STI. From 9. claim 1, characterized in that forming the pad oxide film between the silicon substrate and the stopper layer 8
The method for forming an STI according to any one of the above.