JP3158851B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device suitable for reducing power consumption by controlling the potential of a bit line during data writing.

[0002]

2. Description of the Related Art Conventionally, there has been a method of reducing the potential of a bit line not to be accessed during a writing period, thereby shortening a precharge period in the next access, and achieving high speed and low power consumption. . For example, JP
See 1-28795.

[0003]

However, in the above configuration, the precharge of the bit line is not completely stopped at the time of writing data. As the storage capacity of a semiconductor memory device increases, the load capacity of a bit line increases due to an increase in the number of memory cells constituting a memory cell array. Therefore, there is a problem that power consumption in the bit line increases.

Here, the present invention provides a method for writing data,
By comparing previously accessed data with data to be written, a new attention is paid to a control circuit that completely stops precharging of bit lines.

[0005] In view of the above problems, the present invention has the following object.
It is an object of the present invention to provide a semiconductor memory device in which the potential of a bit line is controlled by a control circuit for controlling precharging of a bit line, and power consumption of a precharge circuit and a write driver accompanying a write operation can be reduced.

[0006]

In order to solve the above-mentioned problems, a semiconductor memory device according to the present invention comprises a row decoder that inputs a row address that is a part of a memory address, and a column that is a part of the memory address. A column decoder having an address as an input, a memory cell array composed of a group of memory cells connected to a word line output from the row decoder, and an output signal of the column decoder as a control signal, which is input to the memory cell. A column selector for selecting a pair of bit lines from a connected bit line group and connecting the selected data line to a data line, and comparing a signal one cycle before and held in the data line with write data to generate a data comparison result signal. An output data comparator, a data comparison result signal of the data comparator, and an OR gate receiving a read control signal; Precharge control means for generating a precharge control signal by an AND gate receiving an output signal of the OR gate and a clock signal; precharge means for precharging a bit line of the memory cell by the precharge control signal; A sense circuit for sensing a signal on a data line connected to the column selector, and an input / output buffer for driving write data to the data line and reading data from the data line to a read data line. .

[0007]

According to the present invention, a signal held on a data line is compared with data at the time of a write access, and a data comparison result signal is output, and a logical product of the data comparison result signal and a clock signal is provided. To generate a precharge control signal. If the data comparison results match, the precharge control signal is disabled, and the precharge of the bit line is completely stopped.

Therefore, by comparing previously accessed data with data to be written from now on and controlling the potential of the bit line, the power consumption of the precharge circuit and the write driver associated with the write operation can be reduced. .

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to one embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a semiconductor memory device according to one embodiment of the present invention. When an external system is connected to a semiconductor memory device, a data bus composed of a plurality of signal lines is used. Here, for the sake of simplicity, it is assumed that a 1-bit data bus is used, and the circuit configuration diagram Is shown.

In FIG. 1, reference numeral 120 denotes an address (ADDR) input to the semiconductor memory device; 121, a clock signal (CK); 122, a write control signal (WT);
3 is write data (DIN), and 124 is read data (DOUT).

Reference numeral 100 denotes address holding means for latching an address 120 with a clock signal (CK) 121.
The address comparing means 150 is the column address holding means 10
1 and an address comparator 102. The column address holding unit 101 latches a column address (CAD), which is a part of the output of the address holding unit 100, with a clock signal (CK) 121. The address comparator 102 stores the column address (CAD) and the column address holding means 1
A column address (CAD1), which is the output of the output 01, is input, and an address comparison result signal (DIFF2) is generated.

Reference numeral 154 denotes a column decoder to which the column address (CAD) is input, and 155: a row address (RAD) which is a part of the output of the address holding means 100, and outputs word lines (WL1 to WLm). It is a row decoder.

The precharge means 153 comprises precharge circuits (PC) 113 and 114. The precharge circuit (PC) 113 precharges the bit lines B1 and XB1. The precharge circuit (PC) 114 similarly precharges the bit lines Bn and XBn.

The memory cell array 152 includes memory cells (M
C) Consists of 115 to 118. Memory cell (MC) 115 is connected to bit lines B1, XB1 and word line WL1, memory cell (MC) 117 is connected to bit lines B1, XB1 and word line WLm, and similarly, memory cell (MC) 116 is Lines Bn and XBn and a word line WL1, and a memory cell (MC) 1
Reference numeral 18 is connected to bit lines Bn, XBn and word line WLm. Here, a case where the number of rows is m and the number of columns is n is shown. For simplification of display, only two pairs of bit lines and two word lines are shown.

Reference numeral 112 denotes a bit line group B1, XB1, Bn,
A column selector that receives XBn as an input and selects a pair of bit lines according to a control signal (CSEL) output from a column decoder 154. 119 is a column selector 112
Is a sense circuit that amplifies the signal of the pair of bit lines selected in (1) and outputs a pair of data lines (DL1 and XDL1). Reference numeral 110 denotes a data holding unit that latches the write data (DIN) 123 with the clock signal (CK) 121. Reference numeral 108 denotes an inverter for inverting the clock signal (CK) 121, and its output signal becomes an enable signal for read or write access. 111 is a data line (DL1 and X1) amplified by the sense circuit 119.
DL1) to read out the data bus (DOUT) 12
4 or the write data (DIN1) output from the data holding means 110 is transferred to the data line (D
L1 and XDL1), and its direction is controlled by a write control signal (WT) 122.
And an enable signal output from the inverter 108.

Reference numeral 104 denotes a write control signal (WT) 122
, And its output signal becomes a read control signal. 103 denotes the write data (DIN1) output from the data holding means 110 and the sense circuit 11
9 is a data comparator which receives the data line (DL1) amplified by 9 and generates a data comparison result signal (DIFF1). 106 is an address comparison result signal (DIFF2), a data comparison result signal (DIFF1) and an inverter 104
This is an OR gate that receives a read control signal, which is an output signal of the OR gate. An AND gate 107 receives the output signal of the OR gate 106 and the clock signal (CK) 121 as inputs. The output signal of the AND gate 107 is a precharge control signal (PRE), which serves as a control signal for precharge circuits (PC) 113 and 114 constituting precharge means. Reference numeral 151 denotes precharge control means for controlling precharge, and 156 denotes data storage means corresponding to one bit of the data bus.

The operation of the semiconductor memory device of the present invention configured as described above will be described below with reference to the circuit diagram of FIG. 1 and the timing chart of FIG.

The signals in the timing chart of FIG. 2 have the same reference numerals as those shown in FIG. N-
1, N, N + 1, and N + 2 are time-series codes indicating the order of access to the semiconductor memory device. Here, N is a read cycle, N + 1 is a write cycle, and N + 2 is a write cycle. Clock signal CK
During the “H” period, a precharge operation is performed, and during the “L” period, a read or write operation is performed.

Write control signal W for performing access control
T is "H" for a write cycle and "L" for a read cycle. The precharge control signal PRE for controlling the precharge of the bit line group generates “H” when precharge is performed and “L” when precharge is stopped.

The operation of the address control will be described below. The memory address ADDR is latched at the rising edge of the clock signal CK, and the row address RAD and the column address CAD are output. Thus, the valid period of the address is synchronized with the cycle currently being accessed. Further, the column address CAD is latched at the rising edge of the clock signal CK, and the column address CAD1 one cycle before is output. The column address CAD and CAD1 are compared by the address comparator 102,
An address comparison result signal DIFF2 is generated. "L" is output if the comparison results match, and "H" is output if they do not match. Therefore, if the current access and the column address accessed one cycle ago are matched by comparison, the same bit line as the bit line accessed one cycle ago in the memory cell 152 is currently accessed. Will be detected.

The operation of the read cycle of the time series N will be described below. It is assumed that the row address RAD is decoded by the row decoder 155 and the word line WL1 is activated. It is also assumed that the bit lines B1 and XB1 are activated by the column selector 112 by the signal CSEL obtained by decoding the column address CAD ("1") by the column decoder 154. Here, since the write control signal WT is “L” indicating the read operation, the precharge control signal PRE for controlling the precharge of the bit line group outputs “H”. Therefore, the precharge means is activated, and the bit lines B1 and XB1 and the data lines DL1 and XDL1 are precharged. During the “L” period of the clock signal CK, a read operation is performed. Data stored in the memory cell 115 is read to the bit lines B1 and XB1, passed through the column selector 112, amplified by the sense circuit 119, and amplified by the sense circuit 119. Transferred to XDL1. This data is read by the input / output buffer 111 and the read data bus D
Driven to OUT. Here, the data line DL1 holds data "L".

Next, the operation of the write cycle of the time series N + 1 will be described below. Write data DIN
Is latched at the rising edge of the clock signal CK, and clock-synchronized write data DIN1 is output. This synchronizes the valid period of the write data with the cycle currently being accessed. The data comparison result signal DIFF1 is compared with the write data DIN1 and the signal on the data line DL1, and is set to "L" when they match, and is set to "H" when they do not match. It is assumed that the row address RAD is decoded by the row decoder 155 and the word line WL1 is activated. It is also assumed that the bit lines B1 and XB1 are activated by the column selector 112 by the signal CSEL obtained by decoding the column address CAD ("1") by the column decoder 154. The write control signal WT is “H” indicating a write operation, and the output of the inverter 104 is “L”. Column address C of read cycle of time series N
Since AD1 ("1") matches the column address CAD ("1") in the write cycle of the time series N + 1, the address comparison result signal DIFF2 becomes "L". The write data DIN1 of the time series N + 1 is “L”, and the signal of the data line DL1 accessed and held in the time series N is “L”.
Since the signal is L, the data comparison result signal DIFF1 of the data comparator 103 becomes "L" indicating data coincidence, so that the precharge control signal PRE for controlling the precharge of the bit line group becomes "L", and the bit line The precharge of the group stops, and the bit lines B1 and XB1, the data line DL1
And XDL1 are maintained at the previous signal level. As a result, no power is consumed by the precharge means. The write operation is performed during the “L” period of the clock signal CK. However, since the bit lines B1 and XB1 and the data lines DL1 and XDL1 hold the write data of the time series N + 1 as they are, the data is written in the input / output buffer. No power consumption occurs.

Next, the operation of the write cycle of the time series N + 2 will be described below. The difference from the write cycle of the time series N + 1 is as follows. Since the column address CAD is “2”, the address comparison result signal D
IFF2 becomes “H” and the precharge control signal PRE
Becomes "H", and the bit line group is precharged. The write operation is performed during the “L” period of the clock signal CK, and the write data of the time series N + 2 is driven on the data lines DL1 and XDL1 by the input / output buffer, and the data is written to the bit line corresponding to the column address “2”.

As described above, according to the present embodiment, the data comparator that compares the signal one cycle before held on the data line with the data at the time of write access and outputs a data comparison result signal, A column address holding means for holding a column address accessed one cycle before the target column address, a column address output from the column address holding means,
By providing an address comparison circuit that compares a column address to be accessed at present and outputs an address comparison result signal, in a write operation, a column address to be accessed one cycle earlier than a column address to be currently accessed And the signal at the previous cycle held in the data line matches the data at the time of the write access, the power consumption accompanying the data writing in the precharge means and the input / output buffer does not occur.

In the above description, a 1-bit data bus is assumed for the sake of simplicity. However, in the case of a data bus composed of a plurality of signal lines, the data storage means uses the bit width of the data bus signal. Can be dealt with by expanding by the number corresponding to.

[0026]

As described above, the present invention compares the signal held on the data line with the data at the time of write access, outputs a data comparison result signal, and outputs the data comparison result signal and the clock signal. An AND operation is performed to generate a precharge control signal. If the data comparison results match, the precharge control signal is disabled, and the precharge of the bit line is completely stopped. Therefore, the previously accessed data is compared with the data to be written,
By controlling the potential of the bit line, power consumption of a precharge circuit and a write driver accompanying a write operation can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a timing chart of the semiconductor memory device in the embodiment;

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 address holding means 101 column address holding means 102 address comparator 103 data comparator 104, 108 inverter 106 OR gate 107 AND gate 110 data holding means 111 input / output buffer 112 column selector 107 control circuit 151 precharge control means 153 precharge means 154 Column decoder 155 Row decoder

Claims (2)

(57) [Claims] 1. A row decoder that receives a row address that is a part of a memory address, a column decoder that receives a column address that is a part of the memory address, and a word line that is output from the row decoder. A memory cell array composed of a group of connected memory cells; and an output signal of the column decoder is input as a control signal, and a pair of bit lines is selected from a group of bit lines connected to the memory cell to form a data line. A column selector to be connected; a data comparator for comparing a signal one cycle before held on the data line with write data to output a data comparison result signal; a data comparison result signal of the data comparator; An OR gate that receives a control signal, and an AND gate that receives an output signal of the OR gate and a clock signal Precharge control means for generating a precharge control signal, precharge means for precharging a bit line of the memory cell by the precharge control signal, and sensing a signal on a data line connected to the column selector. A sense circuit, an input / output buffer for driving write data to the data line, and driving data for the data line to a read data line, and one cycle for a column address to be accessed at present.
Holds the column address that was accessed before
A column address holding unit, and a column address output from the column address holding unit.
Address and the column address currently being accessed
And an address comparator for outputting an address comparison result signal.
And adding the address comparison result signal to the input of the OR gate.
A semiconductor memory device characterized by adding: 2. A row address which is a part of a memory address.
And a column decoder which is a part of the memory address
And a word line output from the row decoder
A memory cell array composed of a memory cell group and an output signal of the column decoder are input as control signals.
From a group of bit lines connected to the memory cells.
Column selector to select bit line and connect to data line
And the signal of the previous cycle held in the data line
Outputs the data comparison result signal by comparing
A data comparator; a data comparison result signal of the data comparator;
An OR gate to which a control signal is input, and an output signal and a clock signal of the OR gate to be input.
A program for generating a precharge control signal by an AND gate
Recharge control means; and a bit of the memory cell by the precharge control signal.
A precharging means for precharging the data line and a signal on a data line connected to the column selector.
A sense circuit for sensing and driving write data to the data line,
I / O to read data from the data line and drive it to the data line
A buffer, data holding means for holding the write data, and
Address holding means for holding the memory address
The input timing is synchronized with the clock signal to
A semiconductor memory device for generating only data and the memory address .