JP3153029B2 - Delay circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit using a complementary field effect transistor circuit, and more particularly to a delay circuit in which a delay time is less dependent on a power supply voltage.

[0002]

2. Description of the Related Art Delay circuits are used in various places inside an LSI chip such as a microcomputer. As a typical example using a delay circuit, there is a circuit for generating an LSI clock operation. The LSI clock generation circuit will be described with reference to FIG. 5 showing a circuit diagram and a time chart thereof.

The clock generation circuit is composed of two AND gates 50 and 51, three inverters 52 to 54 and two delay circuits 55 and 56, and a clock input φi
The clock output φout of the normal phase and the inverted clock output φout of the opposite phase are generated from n.

[0004] Here, A having clock input φin as an input
The ND gate 50 receives the inverted clock output inverted φout of the opposite phase via the delay circuit 56 and the inverter 54, and the inverter 5 which is the inverted signal of the clock input φin.
The positive-phase clock output φout is input to the AND gate 51 to which the output of 2 is input via the delay circuit 55 and the inverter 53.

When the clock input φin changes from “L” level to “H” level, the inverted clock output φout of the opposite phase goes to “L” level via the AND gate 51.
When the delay time t1 of the delay circuit 56 has elapsed, the inverter 5
4 goes high, and the positive-phase clock output φout goes high through the AND gate 50.

Next, when the clock input φin changes from “H” level to “L” level, the positive phase clock output φout changes to “H” level via the AND gate 50 and
Inverted clock output φout via D gate 51
Becomes "H" level. By this repetition, the positive phase clock output φout and the negative phase clock output inversion φout
Generates a signal having an interval between the delay time t1 and the delay time t2 without overlapping the "H" level periods. The delay circuit for generating the clock interval has a delay time of several tens ns, and a circuit in which inverters 61 to 68 are connected in series as shown in FIG. 6 is used. Logic gates such as inverters have a switching delay from the input of a signal until the output changes. By connecting a plurality of gates in series, the delay is used as a value that can be regarded as a certain time.

[0007]

In recent years, there has been a tendency for application equipment utilizing LSI to lower the chip operating voltage. For example, it is required to be operable over a wide range from an operating voltage of 2 [V] in a battery to an operating voltage of 6 [V] in a standard logic. In the conventional delay circuit shown in FIG. 6, when the operating voltage range is widened, the voltage dependence of the delay time is high, and when the power supply voltage is reduced from 5 [V] to 2 [V], the delay time is greatly increased to about 3.3 times. (See FIG. 7). When this circuit is used for the operation clock generation circuit shown in FIG. 5, there is a problem that the clock interval is widened at a low voltage, the clock pulse width is narrowed, and normal operation cannot be performed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a delay circuit in which the delay time is less dependent on voltage, that is, which has good voltage dependence characteristics.

[0009]

The delay circuit of the present invention According to an aspect of the place
Operates at a constant power supply voltage and responds to the threshold voltage of the transistors constituting the circuit,
A voltage generating circuit for generating a stabilized voltage independent of the internal delay circuit, an internal delay circuit using a delay signal as an input signal, and using the stabilized voltage as a power supply voltage, and storing an output of the internal delay circuit.
A flip-flop, the input signal and the flip-flop;
The operation of the voltage generation circuit is controlled by using the output of the
A mismatch detecting circuit, the delay time of the internal delay circuit
This is a configuration in which control is performed so as to suppress the fluctuation between them.

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

FIG. 1 shows a delay circuit according to a first embodiment of the present invention. The delay circuit of this embodiment comprises an internal delay circuit 1, a regulator 2, an exclusive OR circuit 3, and a flip-flop 4. .

The internal delay circuit 1 includes, for example, a plurality of stages of inverting circuits, and outputs a delayed signal having the same phase as the input signal 11 to the output 1.
2 and a delayed signal having a phase opposite to that of the input signal 11
3 is output . The power supply voltage 14 of the internal delay circuit 1 is supplied by the regulator 2. If the supply voltage 14 is not supplied, the internal delay circuit 1 Ri inoperative der, output 12 and 13 will both "L" level. Power supply voltage 14
Is supplied , the internal delay circuit 1 is activated, and delay signals 12 and 13 are output.

The regulator 2 is in operation when the output 15 of the exclusive OR circuit 3 is at "H" level, and is inoperative when the output 15 is at "L" level.

The input of the exclusive logic circuit 3 is the input signal 11
The output 15 is connected to the output 16 of the flip-flop 4 so that the output 15 is at the "L" level when the states match, and at the "H" level when the states do not match.

The flip-flop 4 operates based on the signals 12 and 13 delayed by the internal delay circuit 1. When the delayed signal 12 in phase with the input signal 11 is at "H" level, the flip-flop 4 is set. The output 16 becomes "H" level, and when the delay signal 13 having the opposite phase to the input signal 11 is at "H" level, the flip-flop 4 is reset and the output 16 becomes "L" level.

Next, a detailed operation of the delay circuit according to the first embodiment will be described.

For example, consider the case where the input signal 11 is at the "L" level as an initial state. The input signal 11 is at the "L" level, and the output 15 of the exclusive OR circuit 3 is at the "L" level because both inputs are at the "L" level. Since the output 15 of the exclusive OR circuit 3 is at "L" level, the regulator 2 is in the inactive state, the voltage 14 is not supplied to the internal delay circuit 1, and the internal delay circuit 1
, And the flip-flop 4 holds the previous state, that is, the “L” level.

Here, consider the case where the input signal 11 changes to "H" level. When the input signal 11 becomes “H” level, it does not match the output 16 of the flip-flop 4, so that the exclusive OR circuit 3 outputs “H” level to the regulator 2 via the signal 15. When the signal 15 goes to the “H” level, the regulator 2 enters an operating state, supplies a voltage to the internal delay circuit 1 via the voltage supply line 14, and
Becomes operational. Accordingly, “H” of the input signal 11
The level is delayed by the internal delay circuit 1 and the input signal 11
And the delay signal 12 in phase with the input signal 11
The flip-flop 4 is set because the delayed signal 13 having the opposite phase to the “L” level is set to “H” as a delayed signal.
The level is output to the output signal 16. When the output signal 16 goes to "H" level, the inputs of the exclusive OR circuit 3 match, so when the output 15 of the exclusive OR circuit 3 goes to "L" level, the regulator 2 becomes inactive and the internal delay circuit The supply of the voltage to 1 stops. Then, the internal delay circuit 1 is in a non-operation state, and the signals 12 and 13 are both at “L”.
Hold the level.

Next, consider the case where the input signal 11 changes to "L" level. When the input signal 11 goes low, the value of the output 16 of the flip-flop 4 does not match. Therefore, the output 15 of the exclusive logic circuit 3 goes high and the regulator 2 receives the internal delay circuit 1 from the voltage supply line 14. Supply voltage. When the voltage is supplied, the internal delay circuit 1 is activated, the “L” level of the input signal 11 is delayed, and the delayed signal 12 in phase with the input signal 11 is the “L” level signal 1
3 becomes "H" level, the flip-flop 4 is reset and outputs "L" level as a delayed signal.
6 is output. When the output signal 16 becomes “L” level,
Since the inputs of the exclusive OR circuit 3 match, the output 15 of the exclusive OR circuit 3 changes to "L" level. When the output 15 of the exclusive OR circuit 3 goes to the “L” level, the regulator 2 enters a non-operating state and the supply of the voltage to the internal delay circuit 1 is stopped. Then, the internal delay circuit 1 becomes inactive and the signals 12 and 13 both become "L" level, so that the flip-flop 4 holds the previous state "L" level.

The delay circuit of this embodiment generates a delay signal by repeating the above operation.

A feature of the present invention is that the fluctuation of the power supply voltage of the internal delay circuit for generating the delay time is minimized by the regulator to reduce the fluctuation of the delay time.

A specific circuit diagram is shown in FIG.

The internal delay circuit 1 has a configuration in which inverting circuits 21 to 28 are connected in series. The inverting circuit 21 includes a P-channel transistor 201 and an N-channel transistor 10 between the voltage 14 supplied from the regulator 2 and GND.
1 are connected in series, and the inverting circuits 22 to 2
8 also has the same configuration as the inverting circuit 21, and includes P-channel transistors 202 to 208 and N-channel transistors 102 to 108, respectively. The inverting circuit causes a switching delay from the input of the signal to the output of the result. The internal delay circuit 1 functions as a delay circuit by connecting inverting circuits in a required number of stages in series. For this reason, in the internal delay circuit 1, the delay signal in phase with the input signal 11 is output to the output 12 of the inversion circuit 28 (even-numbered stage), and the delay signal in phase opposite to that of the input signal 11 is output from the inversion circuit 2.
7 (an odd-numbered stage).

Next, the regulator 2 will be described. When the output of exclusive OR circuit 3 is at "H" level, N-channel transistor 109 and P-channel transistor 209
Output from the power supply voltage terminal VDD to GND, the P-channel transistors 210 and 211 and the N-channel transistor 11
Current flows through 1. At this time, assuming that the threshold voltage of the N-channel transistor 111 is V _TN , the N-channel transistor 111 functions as a diode for clamping to the threshold voltage V _TN because the gate and the drain are connected. Similarly, the P-channel transistor 211 can be regarded as a diode that clamps to the threshold voltage V _TP , so that the supply voltage 14 _{ends up} with the threshold voltage V _TN and the threshold voltage V _TP.
A regulated voltage is generated that is clamped to the sum of the absolute values of _TP (V _TN + | V _TP |). For example, V _TN
Is 0.8 [V] and _VTP is 0.7 [V], the internal delay circuit 1 does not change even if the power supply voltage changes from 7 [V] to 2 [V].
Is supplied from 3.1 [V] to 1.7.
[V], that is, only about 1.4 [V].

When the input signal 11 and the output 16 of the flip-flop 4 do not match, the exclusive OR circuit 3 sets the output 17 of the NOR circuit composed of the N-channel transistors 112 and 113 and the P-channel transistors 212 and 213 to "L". Become a level. In this state, N-channel transistors 114 to 116 and P-channel transistors 214 to 2
As for the output 15 of the AND-NOR circuit constituted by 16, either the input signal 11 or the output 16 of the flip-flop 4 is at "L" level, so that the P-channel transistor 215 or 216 is conducting, and The output 17 of the NOR circuit is "L"
Since this is the level, the P-channel transistor 214 is in a dynamic state, so that the level becomes “H” level.

When both the input signal 11 and the output 16 of the flip-flop 4 are at "H" level, the N-channel transistors 115 and 116 conduct, and the output 15 goes to "L" level. When both the input signal 11 and the output 16 of the flip-flop 4 are at "L" level, the N-channel transistor 11
2 and 113 and P-channel transistors 212 and 213, the output 17 of the NOR circuit is "H" level, so that the N-channel transistor 214 conducts and the output 15
Becomes "L" level.

When the set terminal S is at "H" level and the reset terminal R is at "L" level, the flip-flop 4
Since the set terminal S is at "H" level, the N-channel transistor 117 conducts, and the contact 18 goes to "L" level. The “L” level of the contact 18 is a value “H” inverted by an inverting circuit composed of the N-channel transistor 120 and the P-channel transistor 218, and the “H” level is the contact 1
9 is output. When the contact 19 becomes "H" level, the N-channel transistor 119 and the P-channel transistor 2
The value “L” level inverted by the inversion circuit 17 is output to the contact 18, and a stable state is maintained at the “L” level. Conversely, the operation is opposite to the case where the set terminal S is at the “L” level, and the contact 18 maintains a stable state at the “H” level.

Both the set terminal S and the reset terminal R are L
At the time of “L” level, both the N-channel transistors 117 and 118 do not conduct, so that the previous state is maintained.

The delay circuit of the present invention minimizes fluctuations in the voltage applied to the internal delay circuit 1 by supplying the voltage 14 of the internal delay circuit 1 by the regulator 2 as shown in FIG. The purpose is to reduce the fluctuation of Referring to FIG. 3 showing the characteristic diagram, when the power supply voltage is 5
Even if the voltage drops from [V] to 2 [V], the delay time changes only about 1.4 times.

Next, a delay circuit according to a second embodiment of the present invention will be described with reference to FIG. In the first embodiment, the voltage 14 supplied from the regulator 2 to the internal delay circuit 1 is the sum of the threshold voltage V _TN of the N-channel transistor 111 and the threshold voltage V _TP of the P-channel transistor 211 (V _TN +
| V _TP |). On the other hand, in the second embodiment, if the threshold voltages of the N-channel transistors 121 and 122 are V _TN ′ and the threshold voltages of the P-channel transistors 221 and 222 are V _TP ′, the N-channel transistors 121 and 122 Since the gate and the drain are connected, and the gates and the drains of the P-channel transistors 221 and 222 are also connected, the respective threshold voltages V _TN ′
And acts as a diode that clamps to the voltage of V _TP '. Therefore, the voltage supply 14 has 2 × V _TN ′ or 2
A regulated voltage is supplied to the lower voltage of × | V _TP '|.

It is common knowledge to those skilled in the art that the regulator can be implemented in various configurations other than the first and second embodiments. In this embodiment, the voltage supplied from the output of the regulator is used as the voltage of the internal delay circuit. However, it can be realized by controlling the switching speed of the inverting circuit constituting the internal delay circuit.

[0032]

As described above, according to the present invention, since the voltage of the delay circuit is supplied by the regulator, even if the power supply voltage fluctuates, the fluctuation of the voltage supplied to the delay circuit can be small. As a result, the variation of the delay time can be small.

Therefore, in the conventional delay circuit, L at a low voltage
Although the normal operation of the SI cannot be guaranteed in some cases, the use of the delay circuit of the present invention has an effect that the normal operation can be ensured even in a low voltage region.

[Brief description of the drawings]

FIG. 1 is a block diagram of a delay circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of the delay circuit shown in FIG.

FIG. 3 is a characteristic diagram of the delay circuit shown in FIG. 1;

FIG. 4 is a diagram illustrating the regulation of a delay circuit according to a second embodiment of the present invention;
It is a circuit diagram of the data.

5A and 5B are diagrams showing an operation clock generation circuit, in which FIG. 5A is a circuit diagram and FIG. 5B is a timing chart.

FIG. 6 is a block diagram of a conventional delay circuit.

FIG. 7 is a characteristic diagram of the delay circuit shown in FIG . 6 ;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 internal delay circuit 2 regulator 3 exclusive OR circuit 4 flip-flop 11 input signal 12 delay signal in phase with input signal 13 delay signal in phase opposite to input signal 14 supply voltage from regulator to internal delay circuit 15 exclusive OR Regulator control signal by circuit 16 Output signal 17 NOR circuit output of exclusive OR circuit 18 Displacement point of flip-flop set terminal 19 Displacement point by flip-flop set terminal 50,51 AND gate 52-54 Inverter 55,56 Delay circuit φin Input signal φout Clock output of positive phase φout Clock output of reverse phase 61-68 Inverter 101-120 N-channel transistor 201-218 P-channel transistor

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 5/13

Claims (1)

(57) [Claims] The circuit operates at a predetermined power supply voltage and corresponds to a threshold voltage of a transistor constituting a circuit.
A voltage generating circuit for generating a regulated voltage independent of variations in the electric supply voltage, and the input signal a delay signal, wherein the stabilizing electrostatic
An internal delay circuit for the pressure and the power supply voltage, the internal delay circuit
A flip-flop storing an output of the input signal;
The output of the flip-flop is used as an input to generate the voltage.
A mismatch detection circuit for controlling the operation of the road,
A delay circuit for controlling a variation of a delay time of the delay circuit.