JP3019543B2 - Image display system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display system for an information processing system, and more particularly to a still image image display system capable of displaying images in a double buffer system.

[0002]

2. Description of the Related Art A conventional image display system includes a normal display for displaying one image (hereinafter, referred to as a normal display) and a normal display.
A double-buffer display (hereinafter, referred to as a double-buffer display) capable of separately displaying two images has been possible. Note that there are two types of methods for enabling double buffer display.

In the first method, two sets of image memories having the same configuration are provided, and two images stored in these memories are switched and displayed. As a second method, an image memory capable of storing and displaying image data of N bits of luminance information corresponding to one pixel is provided. Usually, one image is displayed as one set of image memories and N bits per scanning line. When performing double-buffer display, N bits are divided into upper and lower bits, and two sets of N /
Two images are stored and switched and displayed as a 2-bit image memory.

Next, a conventional example will be described with reference to the drawings.

FIG. 4 is a block diagram showing an example of the second conventional system.

The image display system shown in FIG. 4 includes a host 10b for creating an image, and an image display device 20b for storing the image created by the host 10b and converting the image into a video signal rate.
And a display device 30 such as a CRT or a liquid crystal display device having a display screen 31 for inputting a signal of the image display device 20b and displaying an image. Image display device 20
b denotes an image memory 21 which is a frame buffer using a dual port memory having a random port 21a and a serial port 21b, and the host 10b controls image data read out from the serial port 21b of the image memory 21 for each scanning line. And a read data mask circuit 16 for masking the upper or lower N / 2 bits of the luminance information to "0" and passing the same in double buffer display, and an image memory 21 under the control of the host 10b.
Control signal 301 for controlling the serial read timing of
And a shift register 5 for converting image data read from the image memory 21 via the read data mask circuit 16 into a video signal rate. The host 10b includes an image creating unit 11b that creates and outputs image data, and a read control circuit 3b.
12b for controlling the read data mask circuit 1
6 includes a double buffer control unit 14b for controlling whether to perform normal display or double buffer display.

FIG. 5 is a diagram for explaining the relationship between the image displayed on the display device and the image memory. The image 40 is composed of a pixel 401 which is the minimum unit, and each has N-bit luminance information 410. A group of pixels 401 in the horizontal direction is called a scan line 402, and a plurality of scan lines 402 form the image 40.

[0008] The image memory 21 corresponds to the image 40 and has a pixel storage section 211 for storing pixels 401 and a luminance information 41.
And an N-bit luminance information storage unit 210 for storing 0. The number of bits of the luminance information 410 per pixel = N should be at least 1 bit in the line figure expression, but if the number of bits is increased, it can be used for more luminance gradation expression. With 24 bits, three primary colors for color expression can be specified.

In the double buffer display, the luminance information storage unit 210 is used separately from the upper N / 2 bit storage unit 210a and the lower N / 2 bit storage unit 210b. For this reason, in this description, the luminance information storage unit 210 can store N = 4 bits during normal display, and during double buffer display,
A description will be given assuming that two N / 2 = 2 bits can be stored.

Next, the operation of the conventional image display system will be described with reference to the drawings. FIG. 6 shows image data, image memory, and display device 2 in the case of double buffer display.
FIG. 7 is an explanatory diagram for explaining the correspondence between two display screens, and FIG. 7 is an explanatory diagram for explaining the correspondence between the image data, the image memory, and the display screen of the display device in the case of normal display.

In the case of double buffer display, the host 10
The image creating unit 11b creates two images 40e and 40f as shown in FIG. The image creation unit 11b stores the image 4 in the upper N / 2 bit storage unit 210a of the image memory 21.
0e is stored, and the image 40f is stored in the lower N / 2 bit storage unit 210b. At that time, the luminance information 410 of the images 40e and 40f is reduced to 2 bits.

The control unit 12b controls the read control circuit 3b to output a control signal 301 to the image memory 21 and to output image data from the image memory 21. The double buffer control unit 14b stores the upper N / 2-bit storage unit 2 output from the image memory 21 to the read data mask circuit 16.
It instructs which of the image 40e stored in 10a and the image 40f stored in the lower N / 2 bit storage unit 210b is masked and which is displayed.

When displaying only the image 40e stored in the upper N / 2-bit storage section 210a, the double buffer control section 14b sends the read data mask circuit 16 to the lower N
It instructs to mask image 40f stored in / 2 bit storage unit 210b and display image 40e stored in upper N / 2 bit storage unit 210a. When the image data on the scanning line is output from the image memory 21, the image 40f stored in the lower N / 2 bit storage unit 210b is masked by the read data mask circuit 16, and stored in the upper N / 2 bit storage unit 210a. Image 40e is stored in the shift register 5
To enter. The shift register 5 converts the image data and displays the image 40e on the display screen 31 of the display device 30.

To display only the image 40f stored in the lower N / 2 bit storage section 210b, the double buffer control section 14b sends the read data mask circuit 16 to the upper N
It instructs to mask image 40e stored in / 2 bit storage unit 210a and display image 40f stored in lower N / 2 bit storage unit 210b. When the image data on the scanning line is output from the image memory 21, the image 40e stored in the upper N / 2 bit storage unit 210a is masked by the read data masking circuit 16, and stored in the lower N / 2 bit storage unit 210b. Image 40f is stored in the shift register 5
To enter. The shift register 5 converts the image data and displays the image 40f on the display screen 31 of the display device 30.

In the case of normal display without double-buffer display, the image creating section 11b of the host 10b stores one image 40d in the image memory 21 in the order of scanning lines as shown in FIG. The control unit 12b controls the read control circuit 3b to output a control signal 301. The double buffer control unit 14b controls the read data mask circuit 16 to display normally. As a result, the image data output from the image memory 21 in the scanning line order is transferred to the display screen 3 of the display device 30 via the read data mask circuit 16 and the shift register 5.
One is displayed as one image 40d.

Although two display screens 31 are shown in FIG. 6, this indicates that either one of the image 40e or the image 40f is displayed on the display screen 31 shown in FIG. .

[0017]

The above-mentioned conventional image display system has a problem that the first method has two sets of image memories, so that the amount of hardware is large and the cost is high. .

In the second method, 2 ^N colors can be displayed when a single image is displayed without performing double buffering. However, when double buffering is performed, 2 ^{N / 2} colors are displayed and the display color is greatly increased. There was a problem that it was reduced.

[0019]

According to the present invention, there is provided an image display system comprising: a host as an upper information processing apparatus; and an image created by the host stored in an image memory as a built-in frame buffer and converted into a video signal rate. Image display device, and image data read by the image display device
And an image display system configured to include a display device for displaying on a liquid crystal display device, when displaying image data in a double-buffer method, the host creates two pieces of the image data, one of which is the The image data is stored in correspondence with the even-numbered scanning lines, and the other image is stored in correspondence with the odd-numbered scanning lines, and when outputting the image data, on the even-numbered scanning lines or the odd-numbered scanning output from the image memory. Either of the image data on the line is branched and stored in one line memory, and the other image data is output to the display device. In the case of the next scanning line, the image data stored in the one line memory is output. Is output.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the image display system of the present invention. The image display system according to the embodiment includes a host 10a that creates an image, an image display device 20a that stores the image created by the host 10a, and converts the image into a video signal rate.
It is configured to include a display device 30 such as a CRT or a liquid crystal display device having a display screen 31 for inputting a signal of the image display device 20a and displaying an image. Image display device 20a
An image memory 1 using a dual port memory having a random port 1a and a serial port 1b, a one-line memory 6 for storing image data read from the serial port 1b of the image memory 1 for each scan line, A multiplexer (hereinafter referred to as MPX) 2 for switching between image data read from the serial port 1b of the image memory 1 and image data read from the one-line memory 6, and control of the serial read timing of the image memory 1 under the control of the host 10a. A read control circuit 3a for outputting a control signal 301 for performing the read operation, an identification signal 302 for determining which of the even and odd scanning lines the image memory is currently being accessed, an identification signal 302 from the read control circuit 3a, and a display from the host 10a. The display control instruction signal on the even-numbered scanning line of the Odd display signal 1 is a display control instruction signal in the odd scan lines of the display signal 131 and the display device 30
32, a control circuit 4 for controlling the MPX2, and a shift register 5 for converting image data read from the image memory 1 and passed through the MPX2 into a video signal rate. The host 10a generates an image data and outputs the image data, and a signal output unit 13a that actively outputs one or both of the even display signal 131 and the odd display signal 132 to switch between the normal display and the double buffer display.
And a control unit 12a for controlling the read control circuit 3a.

Next, the operation of the image display system of the present invention will be described with reference to the drawings. FIG. 2 is an explanatory view for explaining the correspondence between image data, image memory, and display screen of the display device in the case of double-buffer display in FIG. 1, and FIG. FIG. 4 is an explanatory diagram illustrating correspondence with a display screen of the device.

In the case of double buffer display, the host 10
The image creating unit 11a stores the two images 40b and 40c on the even and odd scanning lines of the image memory 1 as shown in FIG. The signal output unit 13a outputs one of the even number display signal 131 and the odd number display signal 132. The control unit 12a controls the read control circuit 3a to output a control signal 301 to the image memory 1, and causes the image memory 1 to alternately output image data on odd scan lines and even scan lines. The output image data is input to the MPX 2 and stored in the one-line memory 6 at the same time.

When displaying only the image 40c stored on the even-numbered scanning lines, only the even-numbered display signal 131 is output from the signal output unit 13a. When the image data on the even-numbered scanning line is output from the image memory 1, the image data is stored in the one-line memory 6, and the read control circuit 3a outputs to the control circuit 4 an identification signal 302 indicating that the image data on the even-numbered scanning line has been output. . The control circuit 4 outputs the even display signal 131 and the identification signal 3
With reference to 02, MPX2 is controlled, and only image data on even-numbered scanning lines is input to the shift register 5. The shift register 5 converts the image data and displays it on the display device 30. When the image data on the odd scanning lines is output from the image memory 1, the read control circuit 3a outputs to the control circuit 4 an identification signal 302 indicating that the image data on the odd scanning lines has been output. The control circuit 4 controls the MPX 2 to switch to the image data from the one-line memory 6. Thus,
On the display screen 31 of the display device 30, only the image 40c of the image data on the even scan line is displayed.

When displaying only the image 40b stored on the odd scanning line, only the odd display signal 132 is output from the signal output unit 13a. When the image data on the odd-numbered scanning line is output from the image memory 1, the image data is stored in the one-line memory 6, and the read control circuit 3a outputs to the control circuit 4 an identification signal 302 indicating that the image data on the odd-numbered scanning line has been output. . The control circuit 4 controls the MPX 2 so that only the image data on the odd-numbered scanning lines is input to the shift register 5. The shift register 5 converts the image data, and
To be displayed. When the image data on the even scanning line is output from the image memory 1, the read control circuit 3a outputs to the control circuit 4 an identification signal 302 indicating that the image data on the even scanning line has been output. The control circuit 4 controls the MPX2,
The image data is switched to the image data from the one-line memory 6. Thus, the image 40b of the image data on the odd scanning line is displayed on the display screen 31b of the display device 30.

In the case of normal display without double buffer display, the image creating section 11a of the host 10a stores one image 40a in the image memory 1 in the order of scanning lines as shown in FIG. The signal output unit 13a outputs both the even display signal 131 and the odd display signal 132. The control unit 12a
The read control circuit 3a of the image display device 20a is controlled to output a control signal 301. The control circuit 4 receives both the even display signal 131 and the odd display signal 132 from the signal output unit 13a. The control circuit 4 controls the MPX 2 so that both the image data on the even-numbered scanning lines and the image data on the odd-numbered scanning lines are valid. As a result, the image data output from the image memory 1 in the order of the scanning lines is displayed as a single image 40 a on the display screen 31 of the display device 30 via the MPX 2 and the shift register 5.

FIG. 2 shows two display screens 31. This means that either one of the image 40b and the image 40c is displayed on the display screen 31 shown in FIG. .

[0027]

As described above, according to the image display system of the present invention, an image forming section for storing two images on even-numbered and odd-numbered scanning lines of an image memory and image data read out from a serial port of the image memory, respectively. An MPX that switches between one line memory that branches and stores the data for each scan line and image data read from a serial port of the image memory or image data read from one line memory, and an identification signal, an even display signal, and an odd display signal. Enter MPX
A read control circuit for outputting a discrimination signal to the control circuit and a control signal for controlling the control signal to the image memory;
By adding a signal output section for outputting an odd display signal and a scanning line control section for controlling a control circuit, image data of two images are alternately output from an image memory as odd scanning lines and even scanning lines, and displayed. The image data on the scanning line to be displayed on the device passes through MPX, and the scanning line which is not displayed is MPX.
And by passing the image data stored in the one-line memory, the image data in the image memory can be divided into even-numbered scanning lines and odd-numbered scanning lines. There is an effect that can be displayed in the buffer.

Further, since the display can be performed without reducing the luminance information, there is an effect that the display can be performed by the double buffer without reducing the display color.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining the correspondence between image data and two display screens of an image memory and a display device in the case of double buffer display in FIG. 1;

FIG. 3 is an explanatory diagram illustrating correspondence between image data, an image memory, and a display screen of a display device in a case of normal display in FIG.

FIG. 4 is a block diagram showing an example of the related art.

FIG. 5 is a diagram illustrating a relationship between image data displayed on a display device and an image memory in FIG. 4;

FIG. 6 is an explanatory diagram for explaining the correspondence between image data and two display screens of an image memory and a display device in the case of double buffer display in FIG. 4;

FIG. 7 is an explanatory diagram illustrating correspondence between image data, an image memory, and a display screen of a display device in the case of normal display in FIG.

[Explanation of symbols]

 Reference Signs List 1 image memory 1a random port 1b serial port 2 MPX 3a read control circuit 301 control signal 302 identification signal 4 control circuit 5 shift register 6 1 line memory 10a host 11a image creation unit 12a control unit 13a signal output unit 131 even display signal 132 odd number Display signal 20a Image display device 30 Display device 31 Display screen 40a, 40b, 40c Image

Claims (3)

(57) [Claims] A host that is an upper information processing apparatus; an image display device that stores an image created by the host in an image memory that is a built-in frame buffer and converts the image signal into a video signal rate; And a display device for displaying the image data on a CRT or a liquid crystal display device, when the image data is displayed in a double-buffer system, the host computer creates two pieces of the image data. , One is stored in correspondence with the even-numbered scanning line of the image memory, and the other is stored in correspondence with the odd-numbered scanning line, and when outputting the image data, the even number output from the image memory is output. Either the image data on the scanning line or the odd scanning line is branched and stored in the one-line memory, and the other same image data is output to the display device, Image display system and outputs the image data stored in the one-line memory in the case of a scanning line of. 2. An image display device comprising: an image memory using a dual port memory having a random port and a serial port; and image data read from the serial port of the image memory, and the image data is branched for each scan line. A one-line memory for storing, a multiplexer for switching between image data read from a serial port of the image memory and image data read from the one-line memory, and control for controlling serial read timing of the image memory under the control of the host A read control circuit for outputting a signal and an identification signal indicating which one of the even and odd scanning lines of the image memory is currently being accessed, and an identification signal from the read control circuit and the display device from the host. Display signal which is a display control instruction signal on the even scanning line of A control circuit for controlling the multiplexer from an odd display signal which is a display control instruction signal on an odd scan line of the display device; and a shift register for converting image data read from the image memory into a video signal rate. 2. The image display system according to claim 1, wherein: 3. An image creating section for creating the two image data, outputting the image data in correspondence with even and odd scanning lines of the image memory, and storing the image data in the image memory; A signal output unit that actively outputs one or both of the display signals and switches between a normal display and a display in a double buffer system; and a control unit that controls a read control circuit of the image display device. The image display system according to claim 1.