JP3012427B2 - A / D conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter.
In particular, the invention relates to a successive approximation type A / D conversion circuit having a successive approximation register having a function of correcting a determined bit.

[0002]

2. Description of the Related Art An example of a conventional successive approximation type A / D conversion circuit is shown in FIG. In the following, referring to FIG.
The operation of the D conversion circuit will be described. As shown in FIG. 9, the conventional A / D conversion circuit includes a comparator 60, a successive approximation register 61, a D / A converter 62, and a timing control corresponding to an input terminal 241 and an output terminal 242. An analog voltage input from an input terminal 241 is firstly input to a comparator 60 by a first reference voltage corresponding to the most significant bit output from the D / A converter 62. Are compared, and the comparison result is “1”.
Alternatively, it is output as a digital value of “0” and input to the successive approximation register 61. The successive approximation register 61 is controlled by a timing control signal output from the timing control circuit 63, and updates the most significant bit according to the digital value of “1” or “0” input from the comparator 60. Operation is performed, and then the second
Predetermined data is set in the bit. Thus, the comparison process for the most significant bit is completed, and the analog voltage is compared in the comparator 60 with the second reference voltage output from the D / A converter 62, and the comparison result is similarly calculated. Output as a digital value of “1” or “0”,
It is input to the successive approximation register 61. The successive approximation register 61 is controlled by the timing control signal to operate whether to update the second bit according to the digital value of “1” or “0” input from the comparator 60. Then, predetermined data is set in the third bit. As a result, the comparison process for the second bit is completed, the third reference voltage is output from the D / A converter 62 and input to the comparator 60, and the process shifts to the process for the third bit. The third, fourth,... Reference voltages are output from the D / A converter 62 and input to the comparator 60 through the same sequence, and the bits in the successive approximation register 61 are set in order from the upper bit. Updated sequentially.

When the successive approximation processing up to the least significant bit is completed as described above, at that time, the successive approximation register 61 holds a digital value corresponding to the analog voltage input from the input terminal 241. By reading the digital value, the output terminal 242 outputs the target A / D conversion result.

As a technique for reducing the conversion time in such a successive approximation type A / D conversion circuit, a successive approximation type using a method of sequentially shortening the cycle of successive approximation processing from the most significant bit to the least significant bit is used. An A / D conversion circuit is known (for example, JP-A-1-98022). This successive approximation type A / D conversion circuit is particularly effective when the D / A converter for generating the reference voltage is configured by a capacitance array system as shown in FIG. The D / A converter shown in FIG. 10 has capacitors 66, 67, 68,... Corresponding to each bit of the input digital value.
, 69, and the switch elements 71, 72,
, 77, 78, and 73, 74, 75, 76,..., 77, 78. First, the switch elements 71, 7 constituting the switch element array 70
By setting 2, 73, 74, 75, 76,..., 77, 78 to a predetermined constant state, each of the capacitors 66, 67, 68,. Is connected to one of a high potential applied to the input terminal 253 and a low potential applied to the input terminal 254, respectively. At the same time, when a control signal is input to the input terminal 243, the switch element 64 becomes conductive,
The reference voltage applied to the input terminal 244 is
Are connected to the other electrodes of the capacitors 66, 67, 68,. The reference voltage to be applied to the input terminal 244 is a value determined by the state of the switch element array 70 at this time. For example, among the switch elements configuring the switch element array 70, the reference voltage is applied to the input terminal 254 to which a low potential is applied. Switch elements 72, 74, 7 connected
When only 6,..., 78 are set to be in the conductive state, it is appropriate that the reference voltage applied to the input terminal 244 is equal to the low potential applied to the input terminal 254. is there. Thereafter, the switch element 64 is turned off, and the switch elements 71, 72, 73, 74, 75, 76,...
By switching between 77 and 78, the potential appearing at input terminal 255 changes. In particular, the capacitances 66, 67, 68,..., 69 constituting the capacitance array 65 are 2 _n (n = N
-1, N-2, N-3,..., 2, 1, 0), the switch elements connected to the capacitors 66, 67, 68,. By making the control correspond to each bit of an arbitrary binary number, a voltage corresponding to the binary number is generated at the input terminal 255. For example, capacity 6
6, the switch element 71 conducts and the high potential is connected, and the capacitors 67, 68,..., 69 conduct the switch elements 74, 76,. In this case, the input terminal 255 has a binary number “1”.
00... 0 appears. In this way, the circuit shown in FIG. 10 operates as a D / A converter. However, the input to the capacitance array type D / A converter changes. Then, the longest time until the output voltage reaches the voltage corresponding to the input data is the maximum amount of charge transfer due to the principle of operation involving the charge and discharge of the charge accumulated in the capacitor, that is, the longest time. The time when the upper bit changes is the longest, and becomes shorter as the lower bit becomes smaller.
Now, bits of weight 2 ⁿ (n = N−1, N−1,...,
Assuming that the time from the switching time of (1, 0: N is the total number of bits) to the time when the output voltage converges to 0.5 times or less the error of the least significant bit is T, T is given by the following equation.

[0005]

In the above equation, C _n and R _n are the capacitance corresponding to the least significant bit in the capacitance array and the resistance value of the switch element. As shown in the above equation, the time constant C _n
Even if R _n is constant, the successive approximation processing cycle is sequentially shortened from the most significant bit (n = N-11) to the least significant bit (n = 0), so that the conversion can be performed without lowering the conversion accuracy. Time can be reduced.

On the other hand, if there is an error in the comparison judgment due to shortage of comparison time or noise in the comparator for comparing the analog input voltage and the reference voltage, the conventional successive approximation type A / D converter is not used. However, there is a problem that the bit once determined on the successive approximation register cannot be corrected. As a means for solving this problem, two levels of reference voltage and an analog input voltage set so that the determination ranges overlap each other are determined in parallel or in a time-division manner. There is a known means for correcting an erroneous determination in a subsequent successive approximation sequence (for example, JP-A-3-46414). This successive approximation type A
In the / D converter, as shown in the block diagram of FIG. 11 and the determination range of the comparator in FIG. 12, in FIG. 11, the reference voltages for comparators 79 and 80 are set so that the respective determination ranges overlap. , The reference voltage generated by the reference voltage generation circuit 83 is applied. In the determination of the n-th bit, even though the input voltage should be determined to belong to the range “H” shown in FIG. , The determination range of the (n-1) th bit is the nth
Since the bit overlap range is included, the input voltage does not go out of the determination range, and the correction in the subsequent successive approximation sequence becomes possible.

[0008]

In the conventional successive approximation type A / D conversion circuit described above, the conversion time of the D / A converter and the determination time of the comparator are required to reduce the A / D conversion time. In addition, it is necessary to reduce the data update time of the successive approximation register and the like, and there is a problem that most of the determination time in the comparator consumes most of the time in order to improve the conversion accuracy. However, in the method of reducing the conversion time of the D / A converter, which is one of the measures against the above-described problem, there is no effect of reducing the determination time of the comparator, which occupies most of the conversion time. There is a disadvantage that the effect of shortening the entire conversion time is small.

Further, in the method of FIG. 11 which enables correction of the determined bit, since the erroneous judgment in the comparator is allowed to some extent, it is possible to reduce the judgment time of the comparator. However, when performing parallel processing, the comparator is 2
And the comparator itself is usually configured as an analog circuit with a large occupied area, so that it has a large effect on the circuit scale of the successive approximation type A / D converter circuit, and furthermore, the characteristics vary due to manufacturing variations. It has the disadvantage that it is also greatly affected. In addition, when the same method is used as the time division processing, there is a disadvantage that the effect of shortening the conversion time is reduced.

[0010]

SUMMARY OF THE INVENTION A successive approximation type A of the present invention is provided.
The / D conversion circuit receives an analog input voltage to be A / D converted and a reference voltage of a predetermined level, and compares the potential levels of these two voltages with each other. After receiving the comparison result,
A successive approximation register controlled by a predetermined timing control signal and having an operation function including operation, holding and output of digital data of a predetermined number of bits for each bit of the digital data; and the successive approximation register D / A conversion means for receiving an output of the digital data, generating an analog voltage corresponding to the digital data and outputting the analog voltage as the reference voltage, and a digital / analog converter for storing the digital data held in the successive approximation register And timing control means for generating and outputting the timing control signal for controlling the operation for each bit at a predetermined time, and outputting the digital data of the successive approximation register in accordance with the input of the timing control signal. No, from the most significant bit to the least significant bit according to the comparison result output from the voltage level comparing means. In successive approximation A / D conversion circuit is sequentially bit manipulation to bits, the successive approximation register
The star is a continuous block of two or more bits of the digital data.
Arithmetic addition or addition of predetermined data to bits
Means for performing arithmetic subtraction processing, wherein
In doing so, the determination of one particular bit is
"1" is arithmetically added, and the reference voltage and the
The relationship with the analog input voltage is that the reference voltage is
When the input voltage is smaller than the input voltage, “1” is further added to the bit.
Arithmetic addition, the reference voltage is higher than the analog input voltage
When greater, the first to arithmetically subtract "1" from the bit
Performing a sequential bit operation and performing the first sequential bit operation
After that, the reference voltage and the analog input voltage at this time are
And the reference voltage is smaller than the analog input voltage.
At this time, the bit and the higher bit
The contents are left as is and the lower bits
Proceed with the decision, when the reference voltage is the analog input voltage
After arithmetically subtracting “1” from the bit,
In this configuration, the lower bits are determined.

[0011]

[0012]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, in the present embodiment, a comparator 1 corresponds to an input terminal 201 and an output terminal 202.
And a successive approximation register 2 including a constant generator 3, an adder / subtractor 4, and a register 5, a D / A converter 6, and a timing control circuit 7.

In FIG. 1, an analog voltage externally input via an input terminal 201 is input to one input terminal of a comparator 1 and is output from the D / A converter 6 to the other input terminal. Is input. On the other hand, predetermined data corresponding to the most significant bit is previously selected in the successive approximation register 2 including the constant generation unit 3, the addition / subtraction unit 4 and the register unit 5 and having a constant generation function and an addition / subtraction function. A control operation for the D / A converter 6 for generating the reference voltage is performed according to the data. First, a first reference voltage corresponding to the most significant bit is output from the D / A converter 6 and input to the comparator 1. In the comparator 1, the analog voltage input from the input terminal 201 is
It is compared with the first reference voltage corresponding to the most significant bit output from the D / A converter 6, and the comparison result is output as a digital value of "1" or "0". Is done. In the successive approximation register 2,
Controlled by the timing control signal output from the timing control circuit 7, the operation of updating the most significant bit according to the digital value of "1" or "0" input from the comparator 1 is performed. Then, predetermined data is set in the second bit and the following bits. Thereby, the comparison processing for the most significant bit is completed, the second reference voltage corresponding to the second bit is output from the D / A converter 6 and input to the comparator 1, and the conversion for the second bit is performed. Move on to processing. The analog voltage is compared with the second reference voltage output from the D / A converter 6 in the comparator 1, and the comparison result is similarly output as a digital value of “1” or “0”. Then, it is input to the successive approximation register 2. In the successive approximation register 2,
Under the control of the timing control signal, an operation is performed to determine whether or not to update the second bit in accordance with the digital value of “1” or “0” input from the comparator 1. Predetermined data is set in bits below the bit. As a result, the comparison process for the second bit is completed, and the D / A converter 6 outputs the third bit corresponding to the third bit.
Is output to the comparator 1 and the process proceeds to the conversion process for the third bit. Hereinafter, through the same conversion sequence, the D / A converter 6 outputs the third, fourth,.
Are output to the comparator 1 and the bits in the successive approximation register 2 are successively updated from the highest order. However, the timing generation circuit 7 generates and outputs a short-period timing control signal for high-speed successive approximation processing during the successive approximation sequence from the most significant bit to a predetermined bit. In the high-speed successive approximation processing, if the difference between the reference voltage input to the comparator 1 and the voltage of the analog input signal is not sufficiently large, a determination error may occur. Processing continues with the error included.

When the successive approximation processing up to a predetermined bit is completed as described above, the timing control circuit 7
In, a timing control signal having a long cycle for the detailed comparison process is generated and output, and the process proceeds to the detailed comparison process. The important point here is that successive comparison processing and bit manipulation are performed twice on the first bit after the transition to the detailed comparison processing. By the second bit operation on the same bit, it is possible to correct the comparison error up to that time. However, when the bit operation on the same bit is repeated, a problem arises when “1” is further added to the bit in which “1” is set in the first bit operation, and “0” is added in the first bit operation. Is a case where "1" is further subtracted from the bit in which is set. In order to solve this problem, in the successive approximation register 2 according to the present invention, a constant generator 3, an adder / subtractor 4
And a register section 5, thereby realizing an arithmetic addition function with carry and an arithmetic subtraction function. That is, as in the case of the successive approximation register in the conventional A / D conversion circuit, in order to set “1” to the bit in the register unit 5 where “0” is set, the constant generation unit 3 Generates a constant in which only the relevant bit is “1”, and adds this value and the data in the register section 5 to the adder / subtracter 4
, The data in the register section 5 is updated. Further, in a case specific to the present invention, that is, when adding “1” to a bit in which “1” is set in the register section 5, the constant generation section 3 sets only the relevant bit in the same manner. A constant of “1” is generated, and the value of the register unit 5 is updated by adding this value and the data of the register unit 5 in the adder / subtractor 4.
In the case of subtraction, the function of the adder / subtractor 4 is switched to the subtraction function. Thereafter, when the normal successive approximation processing up to the least significant bit is completed, the successive approximation register 2 finally holds a digital value corresponding to the voltage of the analog signal input from the input terminal 201. By reading this digital value, a desired A / D conversion result is obtained.

FIG. 2 is a flowchart focusing on data manipulation of the successive approximation register 2 in order to facilitate understanding of the operation described above. In FIG. 2, x is the value of the data on the successive approximation register 2, N is the total number of bits, n is the number representing the bit corresponding to the weight ²ⁿ , and k is the value of n when the detailed comparison process is started. is there.

First, in step 101, the bit number n to be bit-operated is set to N-1 meaning the most significant bit, and at the same time, the data in the successive approximation register 2 is set to 0, thereby executing the high-speed successive approximation processing. to go into. First, in step 102, "1" is provisionally set to a bit to be bit-operated in the successive approximation register 2. This operation is x = x
+2 _n . If it is the first time, x = x + 2
_(N-1) . The value x of the successive approximation register 2 set in this way is D / A-converted by the D / A converter 6 and then compared with the input voltage in the comparator 1, and the step is performed only when the input voltage is lower. At 102, the temporarily set "1" is canceled. This processing is performed in steps 103 and 104. Next, in step 105, the bit to be bit-operated is shifted down by one bit. Step 102 to step 105
In the processing up to, the bit number n to be bit-operated is
The process is repeated until a preset value k is reached. When n = k, the process branches at step 106 to shift to the detailed successive approximation process. In the detailed successive approximation processing, "1" is provisionally set to a bit to be operated on in the successive approximation register 2 in step 107, and the value x of the successive approximation register 2 is input to the comparator 1 after D / A conversion. If the input voltage is lower, the tentatively set “1” is canceled in step 107. Conversely, if the input voltage is higher, the bit operation target of the successive approximation register 2 is canceled. "1" is added to the bit that becomes This processing includes step 108,
This is performed at 109 and 110. Thereafter, the value x of the successive approximation register 2 is again subjected to D / A conversion and then compared with the input voltage in the comparator 1. Only when the input voltage is lower, the value x of the operation target bit of the successive approximation register 2 becomes “1”. Is reduced. This operation is performed in step 11
1 and 112. In the processing from step 107 to step 112, two operations are performed on the same bit, whereby the error generated during the high-speed successive approximation processing is corrected. Next, the bit to be bit-operated is shifted down by one bit, and the processing from step 113 to step 117 is repeated until the bit becomes the least significant bit. The details of the operations performed in the processing from step 113 to step 117 are basically the same as the processing from step 102 to step 105, but the processing from step 113 to step 117 is performed for the detailed sequential comparison processing. There is a difference that errors do not enter. It is determined in step 117 that the processing up to the processing of the least significant bit is completed.
It is performed in.

Next, the operation of the present invention will be described using a 6-bit A / D conversion circuit as an example. In this example of the 6-bit A / D conversion circuit, it is assumed that the absolute value of the determination error in the high-speed successive approximation processing is smaller than 1.5 times the voltage corresponding to the least significant bit. Also, it is assumed that the absolute value of the determination error in the detailed successive approximation processing is smaller than 0.5 times the voltage corresponding to the least significant bit. 3 and 4 show the D / A in the A / D conversion circuit.
5 is a graph showing a change in a reference voltage generated in the converter 6 over one A / D conversion sequence.

In FIG. 3, at time t = 0, "100000" is set in the successive approximation register 2,
At time t = 1, the comparison in the comparator 1 is performed.
At this time, since the difference between the analog input voltage and the reference voltage generated in the D / A converter 6 is within the error range of the comparator 1, the most significant bit is erroneously set to “0”. Assume that In this case, in the successive approximation process from the second bit to the fourth bit, there is no erroneous determination because the value is out of the comparison error range. It is determined, and then “1” is added to the fifth bit, and the value of the successive approximation register 2 becomes “011110”. From the fifth bit, the process proceeds to the detailed successive approximation processing, and the comparison is performed at time t = 6. As a result, the analog input voltage is higher in the D / A converter 6.
Since the reference voltage is higher than the reference voltage generated in the above, “1” set in the fifth bit is determined to be valid.
Here, "1" is again added to the fifth bit. However, since the fifth bit is already "1", a state equivalent to performing no operation by the conventional bit operation is obtained. Become. However, in the present invention, since the successive approximation register 2 has an addition / subtraction function, the value of the successive approximation register 2 is “100,000”.
Becomes Similarly, in the comparison result at t = 8,
Since the analog input voltage is higher than the reference voltage generated in the D / A converter 6, "1" added to the fifth bit is determined to be valid. As a result, the value of the successive approximation register 2 becomes “100001”, and in the comparison result at time t = 10, the analog input voltage is higher than the reference voltage generated in the D / A converter 6. It is determined that “1” added to the lower bits is valid, and a series of conversion sequences ends. In FIG. 3, the dotted line is a graph showing the same characteristics in the conventional successive approximation type A / D converter circuit, and the conversion end time is t = 12. Thus, in the case of this example, it can be seen that the conversion time for one round of the conventional successive approximation processing is reduced by the present invention.

In FIG. 4, at time t = 0, "100000" is set in successive approximation register 2 and at time t = 0
= 1, the comparison in the comparator 1 is performed. At this time, since the difference between the analog input voltage and the reference voltage generated in the D / A converter 6 is outside the error range of the comparator 1, the most significant bit is definitely determined to be "1". Next, “1” is added to the second bit, and the value of the successive approximation register 2 becomes “110000”. At time t = 2, it is correctly determined to be “0”, and the second bit is set to “0”.
Is returned to "101000". Next, at time t = 3
In the above, since the difference between the analog input voltage and the reference voltage generated in the D / A converter 6 is within the error range of the comparator 1, the third bit is erroneously determined to be "1". Suppose In this case, the third bit "1"
Is valid, and the value of the successive approximation register 2 is “10110
0 ". Next, at time t = 4, since the difference between the analog input voltage and the reference voltage generated in the D / A converter 6 is outside the error range of the comparator 1, the fourth bit <br>/> Is definitely determined to be "0" and the fourth bit is "0".
And the value becomes “101010”. From the fifth bit thereafter, the process proceeds to the detailed successive approximation processing, and at time t
A comparison is made at = 6. As a result, since the analog input voltage is lower than the reference voltage generated in the D / A converter 6, "1" set in the fifth bit is determined to be invalid and returned to "0". It is. Next time t
At = 8, since the analog input voltage is lower than the reference voltage generated in the D / A converter 6, "1" is subtracted from the fifth bit. At this time, since the fifth bit is “0”, a state equivalent to performing no operation by the conventional bit operation is obtained. However, in the present invention, since the successive approximation register 2 has an addition / subtraction function, the value of the successive approximation register 2 is “100111”. Similarly, in the comparison result at t = 10, the analog input voltage is higher than D
Since it is higher than the reference voltage generated in the / A converter 6, "1" added to the least significant bit is determined to be valid, and a series of conversion sequences ends. In FIG. 4, a dotted line indicates a conventional successive approximation type A /
5 is a graph showing similar characteristics in the D conversion circuit, and the conversion end time is t = 12. As described above, in the case of this embodiment, as in the case of the above-described embodiment, the conversion time for one round of the conventional successive approximation processing is reduced by the present invention.

FIG. 5 is a circuit diagram showing a first embodiment of the successive approximation register 2 included in the present invention. As shown in FIG. 5, in the present embodiment, the input terminals 203, 20
4, 205, 206, 207, 208, 209, 21
0, 211, 212 and output terminals 213, 214, 2
15, 216, 217, and 218, the OR circuit 8
11 to 19, 24, AND circuits 13 to 18, full adders 25 to 29, and latch circuits 30 to 35. The input terminals 203 to 209 are input terminals to which bit control signals are input, and the input terminal 210 is an input terminal to which the comparison result of the comparator 1 is input. Input terminals 211 and 212 are input terminals for a timing signal and a reset signal, respectively, and output terminals 213 to 218 are output terminals for A / D conversion results of the successive approximation register 2 respectively.

FIGS. 6 (a), (b), (c),
(D), (e), (f), (g), (h), (i),
(J) and (k) are timing charts showing signals of respective parts in the successive approximation register 2 of FIG.
Input terminals 212, 211, 203, 204, 205, 2
06, 207, 208, 209 and 210 and the waveforms of the respective signals at the output terminals 213 to 218 are shown.

In this embodiment, the latch circuits 30 to 35 are reset by a reset signal input from the input terminal 212 (see FIG. 6A), and then the input terminal 2
03 to 209, “1” is sequentially input as a bit control signal from the most significant bit to the least significant bit. At this time, the levels of the bit control signals input to the input terminals 203 to 209 are controlled so as not to be "1" at the same time (FIGS. 6C to 6I).
reference). During the high-speed successive approximation processing, the input terminal 20
"1" is input to 3 to 207 as a bit control signal, and is input to the full adders 25 to 29 of the corresponding bits via the OR circuits 19 to 23. At 29, a value obtained by adding "1" to the corresponding bit of the registers 30 to 34 is output. Also,
The OR circuits 8, 9, 10, and 11, the AND circuits 13, 14, 15, and 16, and the inverter 12 input the full adders corresponding to the higher-order bits of the bits among the full adders 25 to 29. According to the comparison result of the comparator 1 input to the terminal 210, either data of which all bits are "0" or data of which all bits are "1" is supplied. Here, it should be noted that when data of all bits “0” is added to the upper side of the bit, “1” added to the upper bit in the immediately preceding cycle is stored, and When data in which all bits are "1" are added to the upper bit, "1" added to the upper bit in the immediately preceding cycle is canceled. The OR circuit 24 is directly connected to the latch circuit 35 without passing through a full adder.

As described above, at the timing when the bit control signal "1" is input to the input terminal 207 as the processing operation proceeds sequentially, the processing shifts to the detailed successive comparison processing once the processing for the latch circuit 34 is completed once. Thereafter, the period of the timing control signal (see FIG. 6B) input from the input terminal 211 becomes longer. In the first transition to the detailed successive approximation processing, the bit control signal “1” is input to the input terminal 207 again, and thereafter, the input terminal 2
“1” is sequentially input to 08 and 209 as a bit control signal (see FIGS. 6G, 6H, and 6I), and the A / D conversion processing ends. Here, the processing for the latch circuit 34 is performed twice.
This is performed to correct an error that has occurred during the previous high-speed successive approximation processing.

FIG. 7 is a circuit diagram showing a second embodiment of the successive approximation register 2 according to the present invention. As shown in FIG. 7, in the present embodiment, the input terminals 219, 220,
221, 222, 223, 224, 225, 226, 2
27, 228, 229, 230, 231, 232, 23
3 and 230, output terminals 235, 236, 237, 2
38, 239 and 240, the OR circuit 36,
43, 49 to 53, AND circuits 44 to 48, full adders 38 to 42, and latch circuits 54 to 59. The input terminals 219, 221, 222, 22
3, 224, 225, 226, and 227 are terminals to which bit control signals are input, respectively.
8 to 233 are input terminals of a timing signal for each bit, and the input terminal 220 is a terminal to which the comparison result of the comparator 1 is input. The input terminal 234 is an input terminal for a reset signal, and the output terminals 235 to 240
Are output terminals of the A / D conversion result of the successive approximation register. 8 (a), (b), (c),
(D), (e), (f), (g), (h), (i),
(J), (k), (l), (m), (n), (o),
(P), (q) and (r) are timing charts showing signals of respective parts in the successive approximation register of FIG. 7, and input terminals 234, 233, 232, 231, and 23, respectively.
0, 229, 228, 227, 226, 225, 22
4, 223, 222, 221, 220 and output terminal 2
Waveforms of respective signals at 35 to 240 are shown.

In FIG. 7, an input terminal 234 (FIG. 8)
(See FIG. 8A) and the latch circuit 54 in response to the reset signal input from the input terminals and the timing signal of each bit input from the input terminals 228 to 233 (see FIGS. 8B to 8G).
Are reset, and then the high-speed successive approximation processing is started. During the high-speed successive approximation processing, the input terminal 22
Bit control signals that do not become “1” at the same time are sequentially input to 7 to 223, and are input to corresponding bit latch circuits 55 to 59 via OR circuits 49 to 53. As a result, "1" is set in the corresponding bit of each of the latch circuits 55-59. At the same time, the bit set in the immediately preceding cycle in each latch circuit is updated to the comparison result of the comparator 1 input from the input terminal 220 via the AND circuits 44 to 48. As described above, the processing operation sequentially proceeds, the bit control signal “1” is input to the input terminal 223, and when the processing for the latch circuit 55 is completed once, the processing proceeds to the detailed successive approximation processing. , Input terminal 233
To 238, the period of the timing control signal is increased.

In the first time of the detailed successive approximation processing, the bit operation on the latch circuit 55 is performed again. However, in this case, when the bit control signal is input to the input terminal 221, the full adders 38 to 42 are connected to the latch circuits 55 to 59 via the AND circuits 44 to 48, and furthermore, The point that the bit control signal is input to the terminal 219, “1” is added in the full adder 38, which is different from the processing contents up to now. In the next cycle, the input terminal 22
When the bit control signal “1” is input to “2”, “1” is set in the latch circuit 54. At the same time, the second comparison result corresponding to the latch circuit 55 is input via the input terminal 220. At this time,
The bit control signal input to the input terminal 221 becomes “1”, and the full adders 38 to 42 are connected to the latch circuits 55 to 59. Thereafter, the comparison result of the comparator 1 with respect to the latch circuit 54 is set, and the A / D conversion processing is completed. Here, the processing for the latch circuit 55 is performed twice, but the second processing is performed as in the case of the first embodiment.
This is performed to correct an error generated during the high-speed sequential processing up to that time.

[0028]

As described above, the present invention is applied to a successive approximation type A / D conversion circuit including a successive approximation register, and the successive approximation register is provided with an addition / subtraction function. The successive approximation processing up to a predetermined bit is performed at a high speed, and the predetermined bit operation is repeated twice, thereby correcting an erroneous decision made during the high-speed successive approximation processing. There is an effect that the conversion processing time can be shortened without impairing.

Further, unlike the analog circuit, the circuit newly added in the present invention is different from the analog circuit, and is entirely constituted by digital circuits. This has the effect of being avoided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of the present invention.

FIG. 2 is a flowchart showing a data operation in a successive approximation register of the present invention.

FIG. 3 is a diagram showing a time change of a reference voltage output from a D / A converter included in the present invention.

FIG. 4 is a diagram showing a temporal change of a reference voltage output from a D / A converter included in the present invention.

FIG. 5 is a circuit diagram showing a first embodiment of a successive approximation register according to the present invention.

FIG. 6 is a timing chart in the first embodiment of the successive approximation register.

FIG. 7 is a circuit diagram showing a second embodiment of the successive approximation register according to the present invention.

FIG. 8 is a timing chart in the second embodiment of the successive approximation register.

FIG. 9 is a block diagram showing a conventional example.

FIG. 10 is a block diagram showing a conventional capacitance array type D / A conversion circuit.

FIG. 11 is a block diagram showing another conventional successive approximation type A / D conversion circuit.

FIG. 12 is a diagram showing a determination range in a comparator of the capacitance array type D / A conversion circuit.

[Explanation of symbols]

 1, 60, 79, 80 Comparator 2, 61, 81 Successive approximation register 3 Constant generation unit 4 Addition / subtraction unit 5 Register unit 6, 62, 82 D / A converter 7, 63, 84 Timing control circuits 8-11, 19 OR circuit 12, 37 Inverter 13-18, 44-48 AND circuit 25-29, 38-42 Full adder 30-35, 54-59 Latch circuit 64, 71-78 Switch element 65 Capacity array 66-69 capacity 70 switch element array

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-53-46259 (JP, A) JP-A-56-31225 (JP, A) JP-A-3-147425 (JP, A) 86328 (JP, U) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03M 1/00-1/88

Claims (1)

(57) [Claims] 1. An analog input voltage to be subjected to A / D conversion and a reference voltage of a predetermined level are input, and voltage level comparing means for comparing and comparing potential levels of these two voltages, and output from the voltage level comparing means In response to the result of the comparison, controlled by a predetermined timing control signal, the digital data of a predetermined number of bits has an operation function including an operation, holding, and output for each bit of the digital data. A comparison register; D / A conversion means for receiving the digital data output from the successive approximation register, generating an analog voltage corresponding to the digital data, and outputting the analog voltage as the reference voltage; Generating and outputting the timing control signal for controlling a bit-by-bit operation of digital data held at a predetermined time. And a timing control means for controlling the successive approximation register.
A successive approximation type A / D conversion circuit in which data is sequentially bit-operated from the most significant bit to the least significant bit in accordance with a comparison result output from the voltage level comparing means in response to the input of the timing control signal. Wherein the successive approximation register stores two digital data
Predetermined data is calculated for consecutive bits of
Means for performing an arithmetic addition process or an arithmetic subtraction process,
When performing sequential bit operations, the determination of one specific bit is
Arithmetic addition of "1" to the specific bit is performed.
The relationship between the reference voltage and the analog input voltage is
When the voltage is smaller than the analog input voltage,
Is further arithmetically added to the reference voltage, and the reference voltage is
When it is larger than the log input voltage, "1" is calculated from the bit.
Performing a first sequential bit operation to perform an arithmetic subtraction,
After performing the bit operation, the reference voltage and the
The reference voltage is compared with the analog input voltage.
If it is smaller than the input voltage,
Leave the contents of the higher order bits
The determination of the lower-order bit proceeds, and the reference voltage is
For log input voltage, arithmetically subtract "1" from the bit
A successive approximation type A / D conversion circuit , wherein, after performing the determination, a bit lower than the bit is advanced .