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JP3008887U - IC pitch conversion board - Google Patents

IC pitch conversion board

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Publication number
JP3008887U
JP3008887U JP1994009385U JP938594U JP3008887U JP 3008887 U JP3008887 U JP 3008887U JP 1994009385 U JP1994009385 U JP 1994009385U JP 938594 U JP938594 U JP 938594U JP 3008887 U JP3008887 U JP 3008887U
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Japan
Prior art keywords
hole
pitch conversion
pattern
board
conductor
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JP1994009385U
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Japanese (ja)
Inventor
定雄 伊藤
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昭英電機株式会社
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Abstract

(57)【要約】 【目的】 ICのリード端子を接続する導体パターンを
表面に、裏面に主回路基板に接続する複数の接続ピンを
植設したICピッチ変換基板をできるだけ小さくすると
ともに、ICピッチ変換基板により占められる主回路基
板の無効面積をできるだけ少なくするICピッチ変換基
板を提供することを目的とする。 【構成】 ICのリード端子5を接続する導体パターン
を多層基板1の表面に形成し、上記導体パターンを多層
基板の共通スルーホールと内層パターンを介してピン挿
通用スルーホールに接続し、上記ピン挿通用スルーホー
ルには接続ピンを植立し、ピン先端を多層基板の裏面に
突出してなることを特徴とする。
(57) [Abstract] [Purpose] An IC pitch conversion board having a conductor pattern for connecting the lead terminals of the IC on the front surface and a plurality of connection pins for connecting to the main circuit board on the back surface is made as small as possible and the IC pitch is It is an object of the present invention to provide an IC pitch conversion board that minimizes the ineffective area of the main circuit board occupied by the conversion board. A conductor pattern for connecting a lead terminal 5 of an IC is formed on a surface of a multilayer substrate 1, and the conductor pattern is connected to a through hole for pin insertion through a common through hole and an inner layer pattern of the multilayer substrate, and the pin It is characterized in that connection pins are set up in the insertion through holes and the tips of the pins are projected to the back surface of the multilayer substrate.

Description

【考案の詳細な説明】[Detailed description of the device]

【0001】[0001]

【産業上の利用分野】[Industrial applications]

この考案は、ICの高集積化と多ピン化に対応して、ICと主回路基板の間に 介在し、ICのピン間隔を主回路基板のピン間隔に拡大変換して接続するICピ ッチ変換基板に関するものである。 This invention is an IC pin that is interposed between the IC and the main circuit board to expand the IC pin interval to the pin interval of the main circuit board for connection in response to high integration and high pin count of the IC. H conversion substrate.

【0002】[0002]

【従来の技術】[Prior art]

近来、高集積化されたICにおいては、そのパッケージ外周からリード端子を 水平に突出しさらにGULL−WING状に折り曲げて形成し、このリード端子 を通して電源および信号の入出力を行うQFP型ICや、あるいはリード端子を 下方に折曲げさらに内側に折返して形成し、ICの占有面積を縮小したPLCC 型ICが多く用いられている。 高集積化が進むにつれてICのチップサイズが小さくなり、また入出力信号リ ード端子の数が増え、主回路基板上に形成される導体パターンの間隔も狭まり、 また導体パターンから引き出されるリードパターンの間隔も狭まっている。 このためICを主回路基板に直接はんだ付けするには、はんだによる短絡や回 路のパターン断線やパターン剥離等の問題が生じ、他の回路パターンの引き回し も制約される。 また、ICのピン間を通過するリードパターンの数も限定されるため、このよ うなICを搭載するには主回路基板を多層化しなければならない。 さらに、導体パターンの寸法精度や導体パターンの熱安定性に対応するため、 主回路基板を高価なガラスエポキシ積層板で形成しければならず、コスト高の一 因となっている。 Recently, in highly integrated ICs, a lead terminal is horizontally projected from the outer periphery of the package, and is further formed by bending it into a GALL-WING shape, and a QFP type IC that inputs and outputs a power supply and a signal through the lead terminal, or A PLCC type IC in which the lead terminal is bent downward and then folded back inward to reduce the area occupied by the IC is often used. As the degree of integration increases, the IC chip size decreases, the number of input / output signal lead terminals increases, the spacing between conductor patterns formed on the main circuit board also decreases, and the lead patterns extracted from the conductor patterns are reduced. Is also narrowing. Therefore, when the IC is directly soldered to the main circuit board, problems such as short circuit due to solder, circuit pattern disconnection and pattern peeling occur, and routing of other circuit patterns is also restricted. Further, since the number of lead patterns passing between the pins of the IC is limited, the main circuit board must be multi-layered to mount such an IC. Furthermore, in order to support the dimensional accuracy of the conductor pattern and the thermal stability of the conductor pattern, the main circuit board must be formed of an expensive glass epoxy laminated plate, which is one of the reasons for the high cost.

【0003】 従来、この対策として、ICと主回路基板との間に2層印刷回路基板からなる ICピッチ変換基板を介装することが行われている。その例としてICピッチ変 換基板1の表面を図8に、裏面を図9に示す。 ICピッチ変換基板1の表面に、IC11(図10)の複数のリード端子11 aに合わせて四角形の四辺に沿って複数の導体パターン2を配列する。 そしてこの導体パターン2の外側に所定の間隔を空けて複数のピン挿通用スル ーホール4を碁盤目状(本例では4行13列)に形成する。 次に、導体パターン2からピン挿通用スルーホール4に向けて、リードパター ン3を基板表面に形成するか、或いはスルーホール13を介して基板裏面に信号 路を出し、基板裏面に形成したリードパターン3により所定のピン挿通用スルー ホール4まで延長して接続し、さらにピン挿通用スルーホール4に接続ピン5を 植立し、接続ピン5を主回路基板(図示せず)に挿通する。 ピン挿通用スルーホール4の隣接間隔は、少なくともリードパターン3が2本 通ることが出来る巾の間隔に形成する。そして四角形の上辺の左端から1番目の 導体パターン2よりリードパターン3を四角形状に配置された導体パターン2の 内側に引き出し、このリードパターン3の先端にスルーホール13aとランドを 形成し、スルーホール13aから基板裏面に回り、最外周列のピン挿通用スルー ホール4aに接続するリードパターン3aを形成する。Conventionally, as a countermeasure against this, an IC pitch conversion substrate composed of a two-layer printed circuit board is interposed between the IC and the main circuit board. As an example, the front surface of the IC pitch conversion substrate 1 is shown in FIG. 8 and the back surface is shown in FIG. On the surface of the IC pitch conversion substrate 1, a plurality of conductor patterns 2 are arranged along the four sides of the quadrangle so as to match the plurality of lead terminals 11 a of the IC 11 (FIG. 10). Then, a plurality of through holes 4 for inserting pins are formed in a grid pattern (in this example, 4 rows and 13 columns) outside the conductor pattern 2 at a predetermined interval. Next, lead patterns 3 are formed on the front surface of the board from the conductor pattern 2 toward the through holes 4 for inserting pins, or a signal path is formed on the back surface of the board through the through holes 13 to form leads on the back surface of the board. The pattern 3 is extended to a predetermined pin insertion through hole 4 for connection, and the connection pin 5 is set in the pin insertion through hole 4, and the connection pin 5 is inserted into a main circuit board (not shown). The pin insertion through-holes 4 are formed adjacent to each other so that at least two lead patterns 3 can pass therethrough. Then, the lead pattern 3 is pulled out from the first conductor pattern 2 from the left end of the upper side of the quadrangle to the inside of the conductor pattern 2 arranged in a quadrangle, and the through hole 13a and the land are formed at the tip of this lead pattern 3, and the through hole is formed. A lead pattern 3a is formed from 13a to the back surface of the substrate and connected to the pin insertion through hole 4a in the outermost peripheral row.

【0004】 ついで、2番目の導体パターン2bをリードパターン3によりピン挿通用スル ーホール4bに、3番目の導体パターン2cをリードパターン3によりピン挿通 用スルーホール4cに、4番目の導体パターン2dをリードパターン3により最 内側のピン挿通用スルーホール4dにそれぞれ接続する。 以下同様に、導体パターン2の4個一組ごとに、対応するピン挿通用スルーホ ール4に接続し、ICのリード端子11aを導体パターン2、スルーホール13 及びリードパターン3を経てピン挿通用スルーホール4に接続する。 これによりリードパターン3の間隔とリードパターン3の巾を広くし、はんだ 付けによるリードパターン3間の短絡や、リードパターン3の断線およびパター ン剥離等の問題を未然に防止している。Next, the second conductor pattern 2b is attached to the pin insertion through hole 4b by the lead pattern 3, the third conductor pattern 2c is attached to the pin insertion through hole 4c by the lead pattern 3, and the fourth conductor pattern 2d is attached. The lead patterns 3 are connected to the innermost pin insertion through holes 4d, respectively. Similarly, every four sets of the conductor patterns 2 are connected to the corresponding through holes 4 for pin insertion, and the lead terminals 11a of the IC are inserted through the conductor patterns 2, the through holes 13 and the lead patterns 3 for pin insertion. Connect to the through hole 4. This widens the space between the lead patterns 3 and the width of the lead patterns 3 to prevent problems such as short circuit between the lead patterns 3 due to soldering, disconnection of the lead patterns 3 and peeling of the pattern.

【0005】 しかし、この従来例では、IC11のパッケージよりも外側に沢山のピン挿通 用スルーホール4を形成するため、図10に示すようにICピッチ変換基板1の サイズが大きくなり、その結果ICピッチ変換基板1を取付ける主回路基板にも 同等の面積を必要とし、ICピッチ変換基板1のコスト低減と主回路基板の小形 化の障害になっていた。However, in this conventional example, since many pin insertion through holes 4 are formed outside the package of the IC 11, the size of the IC pitch conversion substrate 1 becomes large as shown in FIG. The same area is required for the main circuit board on which the pitch conversion board 1 is mounted, which is an obstacle to the cost reduction of the IC pitch conversion board 1 and the downsizing of the main circuit board.

【0006】[0006]

【考案が解決しようとする課題】[Problems to be solved by the device]

上記の問題点を解決するために、本考案ではICピッチ変換基板のリードパタ ーンの巾と間隔を広く取るとともに、ICピッチ変換基板の大きさをできるだけ 小さくすることを目的とする。 In order to solve the above problems, it is an object of the present invention to make the width and interval of the lead pattern of the IC pitch conversion board wide and to make the size of the IC pitch conversion board as small as possible.

【0007】[0007]

【課題を解決する手段】[Means for solving the problem]

上記目的を達成するため本考案は、ICのリード端子接続用の導体パターンを 多層基板の表面に形成し、上記導体パターンを多層基板の共通スルーホールと内 層パターンを介してピン挿通用スルーホールに接続し、ピン挿通用スルーホール には接続ピンを植立し、ピン先端を多層基板の裏面に突出するようにした。 In order to achieve the above object, the present invention forms a conductor pattern for connecting a lead terminal of an IC on a surface of a multi-layer board, and the conductor pattern is a through hole for inserting a pin through a common through hole of the multi-layer board and an inner layer pattern. Connection pins were set up in the through holes for pin insertion, and the tips of the pins were projected to the back surface of the multilayer substrate.

【0008】[0008]

【作用】[Action]

以上のように構成することにより、ICの複数のリードに対応する複数の導体 パターンから複数の接続ピンに至る信号経路を多層基板のスルーホールと内層パ ターンを介して各層に分離して配置し、それぞれ絶縁層を介して各信号経路のパ ターン間隔を拡げて充分な絶縁間隔を確保し、複数の接続ピンをICの搭載面裏 側やその外側直近に分けて配置することにより、ICピッチ変換基板の大きさを 縮小し、同時にICピッチ変換基板による主回路基板の無効面積を縮小し、主回 路基板の有効な利用を図ることができる。 With the above configuration, the signal paths from the plurality of conductor patterns corresponding to the plurality of leads of the IC to the plurality of connection pins are separately arranged in each layer through the through holes and the inner layer patterns of the multilayer board. , The pattern pitch of each signal path is expanded through the insulating layer to secure a sufficient insulation interval, and the multiple IC pins are placed on the back side of the IC mounting surface and on the outer side of the IC mounting surface to divide the IC pitch. The size of the conversion board can be reduced, and at the same time, the ineffective area of the main circuit board by the IC pitch conversion board can be reduced, so that the main circuit board can be effectively used.

【0009】[0009]

【実施例】【Example】

本考案の実施例を図面を参照して詳細に説明する。 図1は、本考案実施例のICピッチ変換基板の平面図でその表側を示し、図2 はその裏側を示す。 ICピッチ変換基板1は4層の積層回路基板からなり、ICを実装する基板表 面には136PのPLCCに対応して各辺34個の四角形に沿って導体パターン 2を形成する。 さらに、導体パターン2の外側には、基板外縁に沿って各辺13個の計52個 のピン挿通用スルーホール4を形成する。Gはグランド用スルーホールである。 導体パターン2の内側(即ちICのパッケージ底面に接触する部分)には、84 個の共通スルーホール6とグランド用スルーホールGを形成する。 そして、このピン挿通用スルーホール4、共通スルーホール6およびGグラン ド用スルーホールは、積層回路基板の層間を貫通している。 Embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a plan view of an IC pitch conversion substrate according to an embodiment of the present invention, showing its front side, and FIG. 2 shows its back side. The IC pitch conversion board 1 is composed of a 4-layer laminated circuit board, and the conductor pattern 2 is formed on the surface of the board on which the ICs are mounted along the 34 quadrangles corresponding to the 136P PLCC. Further, on the outer side of the conductor pattern 2, a total of 52 through holes 4 for pin insertion are formed along the outer edge of the substrate, 13 on each side. G is a through hole for ground. Eighty-four common through holes 6 and ground through holes G are formed inside the conductor pattern 2 (that is, a portion that contacts the bottom surface of the IC package). The pin insertion through hole 4, the common through hole 6 and the G ground through hole pass through the layers of the laminated circuit board.

【0010】 ICピッチ変換基板1の裏面には、内側に上記の84個の共通スルーホール6 と52個のピン挿通用スルーホール4が貫通する。 そしてこの52個のピン挿通用スルーホール4の内側に、さらに各辺2列に2 1個計84個のピン挿通用スルーホール44(ブラインド)を形成し、これらの 合計136個のピン挿通用スルーホール4、44にそれぞれ接続ピン5を挿入し 植立する。ここで接続ピン5の内端は、図5に示すように、基板1の表面に達し ない。 ピン挿通用スルーホール44は、積層接着する前の第2の基板の所定位置にス ルーホール孔を穿孔し、この状態でスルーホールメッキによりピン挿通用スルー ホール4を形成し、その後で第1の基板と積層接着してブラインドスルーホール として形成する。On the back surface of the IC pitch conversion substrate 1, the above-described 84 common through holes 6 and 52 pin insertion through holes 4 penetrate through. Inside the 52 through holes 4 for pin insertion, a total of 84 through holes 44 (blinds) for 21 pins are formed in two rows on each side, for a total of 136 pin insertion holes. Insert the connection pins 5 into the through holes 4 and 44 and plant them. Here, the inner ends of the connection pins 5 do not reach the surface of the substrate 1 as shown in FIG. The through hole 44 for pin insertion is formed by forming a through hole at a predetermined position on the second substrate before laminating and adhering, and in this state, the through hole 4 for pin insertion is formed by through hole plating. A blind through hole is formed by laminating and adhering to the substrate.

【0011】 図3はICピッチ変換基板1にIC(PLCC)11を搭載した状態を示す側 面図で、接続ピン5はIC11(PLCC)の大きさとほとんど同じ面積に収ま ってICピッチ変換基板1に植立され、主回路基板(図示せず)に取付けた時に 占有する基板面積を狭くできる。FIG. 3 is a side view showing a state in which the IC (PLCC) 11 is mounted on the IC pitch conversion board 1, and the connection pin 5 fits in an area almost the same as the size of the IC 11 (PLCC). 1, the area occupied by the board when mounted on the main circuit board (not shown) can be reduced.

【0012】 図4は本考案のICピッチ変換基板の積層状態を示す拡大断面図で、この基板 は表面の部品側より、順次、第1導体レイヤーL1、ガラスエポキシ樹脂層7お よび第2導体レイヤーL2からなる第1の積層板と、第3導体レイヤーL3、ガ ラスエポキシ樹脂基材10、第4導体レイヤーL4からなる第2積層板を、プリ プレグ層8により絶縁板9とボンデイングシート12を介して積層接着して構成 する。FIG. 4 is an enlarged cross-sectional view showing a laminated state of the IC pitch conversion substrate of the present invention. This substrate is the first conductor layer L1, the glass epoxy resin layer 7 and the second conductor in this order from the component side of the surface. The first laminated plate composed of the layer L2, the third conductive layer L3, the glass epoxy resin base material 10, and the second laminated plate composed of the fourth conductive layer L4 are used as the insulating plate 9 and the bonding sheet 12 by the prepreg layer 8. It is constructed by laminating and bonding via.

【0013】 図5はICピッチ変換基板1の要部断面拡大図で、予め第1積層板および第2 積層板には、各導体レイヤーごとに所定の回路パターンをエッチングにより形成 した後、プリプレグ層8により積層接着する。接着後に第1層L1 の導体パター ン2を除いて全面に絶縁被膜(レジスト)塗装を行う。 積層接着した状態で、基板の中央部に複数の共通スルーホール用の孔を、また 周縁部に複数のピン挿通用スルーホール用の孔をそれぞれ穿孔し、スルーホール メッキにより共通スルーホール6とピン挿通用スルーホール4を形成する。 共通スルーホール6は、スルーホールメッキ前にあらかじめ各層導体レイヤー の所定位置に導体ランドを形成して置く。そして、この導体ランドを介してスル ーホールメッキを行い、スルーホール内に確実に連結した導体層を形成する。 第1導体レイヤーL1の表面には、導体パターン2、この導体パターン2に連 なるリードパターン3、及び共通スルーホール6のランドを形成する。FIG. 5 is an enlarged cross-sectional view of an essential part of the IC pitch conversion substrate 1. In the first laminated plate and the second laminated plate, a predetermined circuit pattern is formed for each conductor layer by etching, and then the prepreg layer is formed. 8 is laminated and adhered. After bonding, an insulating coating (resist) is applied on the entire surface except the conductor pattern 2 of the first layer L1. In the state where they are laminated and adhered, a plurality of holes for common through holes are formed in the central part of the board and a plurality of holes for through holes for pin insertion are formed in the peripheral part, and the common through holes 6 and the pins are formed by through hole plating. The through hole 4 for insertion is formed. The common through-hole 6 is formed by forming a conductor land at a predetermined position on each conductor layer in advance before the through-hole plating. Then, through-hole plating is performed through the conductor land to form a surely connected conductor layer in the through hole. On the surface of the first conductor layer L1, the conductor pattern 2, the lead pattern 3 connected to the conductor pattern 2, and the land of the common through hole 6 are formed.

【0014】 図5の区画aおよび区画bに、導体パターン2から接続ピン5に到る接続方法 の異なる例を示し、これらを以下に説明する。 区画aでは、導体パターン2aよりリードパターン3aを経て共通スルーホー ル6aに接続する。そして共通スルーホール6aの第2導体レイヤーL2よりリ ードパターン3aaを経て共通スルーホール6aaに接続し、さらに共通スルー ホール6aaの第3導体レイヤーL3よりリードパターン3aaaを経てピン挿 通用スルーホール4aに接続する。接続ピン5aはピン挿通用スルーホール4a の内周の導体被膜に密着しこれに接続する。 区画bでは、導体パターン2bよりリードパターン3bを経て共通スルーホー ル6bに接続し、共通スルーホール6bの第3導体レイヤーL3からリードパタ ーン3bbに、さらに、ピン挿通用スルーホール4bの側面の導体被膜を通して 接続ピン5bに接続する。 外縁のピン挿通用スルーホール4については、上記の接続方法ではなく導体パ ターン2から第1層のリードパターン3により直接ピン挿通用スルーホール4に 接続する。Different examples of the connecting method from the conductor pattern 2 to the connecting pin 5 are shown in section a and section b in FIG. 5, and these will be described below. In the section a, the conductor pattern 2a is connected to the common through hole 6a via the lead pattern 3a. Then, the second conductor layer L2 of the common through hole 6a is connected to the common through hole 6aa via the lead pattern 3aa, and further, the third conductor layer L3 of the common through hole 6aa is connected to the pin insertion through hole 4a via the lead pattern 3aa. To do. The connection pin 5a is in close contact with the conductor coating on the inner periphery of the through hole 4a for pin insertion and is connected thereto. In the section b, the conductor pattern 2b is connected to the common through hole 6b through the lead pattern 3b, the third conductor layer L3 of the common through hole 6b is connected to the lead pattern 3bb, and the conductor on the side surface of the pin insertion through hole 4b is further connected. Connect to the connecting pin 5b through the coating. The pin insertion through hole 4 on the outer edge is directly connected to the pin insertion through hole 4 by the lead pattern 3 of the first layer from the conductor pattern 2 instead of the above connection method.

【0015】 以上のように、ICピッチ変換基板1に4層以上の多層印刷配線板を用い、導 体パターン2から接続ピン5に接続することにより、接続ピン5を基板1のIC 搭載面の裏面にも配置することができ、ICピッチ変換基板1の寸法を縮小する とともに、主回路基板の搭載面積も併せて縮小できる。As described above, a multi-layer printed wiring board having four or more layers is used for the IC pitch conversion board 1, and the connection pattern 5 is connected to the connection pin 5, so that the connection pin 5 is connected to the IC mounting surface of the board 1. It can also be arranged on the back surface, and the size of the IC pitch conversion substrate 1 can be reduced, and the mounting area of the main circuit substrate can also be reduced.

【0016】 図6および図7は、このように接続ピン5を基板1のIC搭載面の裏面に配置 した場合の実施例で、図6はICピッチ変換基板1に96ピンのQFP−ICを 搭載した状態の側面図、図7はその裏面を示す。 ICピッチ変換基板1に4層の積層基板を用いて、導体パターン2と接続ピン 5を積層基板の各層レイヤーと共通スルーホールにより連結することにより、接 続ピン5の間隔を近接して設け、図7に示すように、ピンをIC搭載面の裏面に 集中して配置し、これによりICピッチ変換基板1を小さくし、殆どICの外形 寸法に近い大きさにすることができる。FIGS. 6 and 7 show an embodiment in which the connection pins 5 are arranged on the back surface of the IC mounting surface of the substrate 1 as described above. FIG. 6 shows a 96-pin QFP-IC on the IC pitch conversion substrate 1. FIG. 7 shows a side view of the mounted state, and FIG. A four-layer laminated substrate is used for the IC pitch conversion substrate 1, and the conductor pattern 2 and the connecting pin 5 are connected to each layer of the laminated substrate by a common through hole, thereby providing the connection pins 5 in close proximity to each other. As shown in FIG. 7, the pins are concentrated on the back surface of the IC mounting surface, whereby the IC pitch conversion substrate 1 can be made small, and the size can be made almost close to the external dimensions of the IC.

【0017】[0017]

【考案の効果】[Effect of device]

以上のように、本考案ではICピッチ変換基板に多層基板を用い、ICのリー ド端子をはんだ付けする導体パターンを多層基板の共通スルーホールと内層パタ ーンを介してピン挿通用スルーホールに接続し、挿通用スルーホールに植立した 接続ピンにより主回路基板に連結することにより、接続ピンの相互間隔を狭め、 ICピッチ変換基板の大きさを縮小するとともに、主回路基板のIC取付面積を 縮小して、トータルコストダウンを図ることができる。 また、ICが絡んだ主回路基板の故障修理の時に、ICピッチ変換基板の接続 ピンのはんだ付けを外しICピッチ変換基板ごと交換することにより、現場で容 易にICを交換でき、サービス業務の作業性を改善することができる。 As described above, in the present invention, the multi-layer substrate is used as the IC pitch conversion substrate, and the conductor pattern for soldering the lead terminal of the IC is formed on the common through hole of the multi-layer substrate and the through hole for pin insertion through the inner layer pattern. By connecting and connecting to the main circuit board by connecting pins set up in the through holes for insertion, the mutual space between the connecting pins is narrowed, the size of the IC pitch conversion board is reduced, and the IC mounting area of the main circuit board is reduced. Can be reduced to reduce the total cost. In addition, when repairing the main circuit board with the IC entangled, you can easily replace the IC on the spot by unsoldering the connection pins of the IC pitch conversion board and replacing the IC pitch conversion board. Workability can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本考案実施例のICピッチ変換基板の平面図で
ある。
FIG. 1 is a plan view of an IC pitch conversion substrate according to an embodiment of the present invention.

【図2】本考案実施例のICピッチ変換基板の底面図で
ある。
FIG. 2 is a bottom view of an IC pitch conversion board according to an embodiment of the present invention.

【図3】本考案実施例のICピッチ変換基板にICを搭
載した状態の側面図である。
FIG. 3 is a side view showing a state in which an IC is mounted on the IC pitch conversion substrate of the embodiment of the present invention.

【図4】本考案実施例のICピッチ変換基板の積層構造
を示す拡大断面図である。
FIG. 4 is an enlarged sectional view showing a laminated structure of an IC pitch conversion substrate according to an embodiment of the present invention.

【図5】本考案実施例のICピッチ変換基板の要部拡大
断面図である。
FIG. 5 is an enlarged sectional view of an essential part of an IC pitch conversion board according to an embodiment of the present invention.

【図6】本考案の他の実施例のICピッチ変換基板にI
Cを搭載した状態の側面図である。
FIG. 6 shows an IC pitch conversion board according to another embodiment of the present invention.
It is a side view of a state where C is mounted.

【図7】図6のICピッチ変換基板の底面図である。7 is a bottom view of the IC pitch conversion substrate of FIG.

【図8】従来のICピッチ変換基板の平面図である。FIG. 8 is a plan view of a conventional IC pitch conversion substrate.

【図9】従来のICピッチ変換基板の底面図である。FIG. 9 is a bottom view of a conventional IC pitch conversion substrate.

【図10】従来のICピッチ変換基板にICを搭載した
状態を示す側面図である。
FIG. 10 is a side view showing a state in which an IC is mounted on a conventional IC pitch conversion substrate.

【符号の説明】[Explanation of symbols]

1 ICピッチ変換基板 2 導体パターン 3 リードパターン 4 ピン挿通用スルーホール 5 接続ピン 6 共通スルーホール 7 ガラスエポキシ樹脂層 8 プリプレグ層 9 絶縁板 10 ガラスエポキシ樹脂基材 11 IC 12 ボンデイングシート 13 スルーホール L1 第1層導体レイヤー L2 第2層導体レイヤー L3 第3層導体レイヤー L4 第4層導体レイヤー 1 IC Pitch Conversion Board 2 Conductor Pattern 3 Lead Pattern 4 Through Hole for Inserting Pin 5 Connection Pin 6 Common Through Hole 7 Glass Epoxy Resin Layer 8 Prepreg Layer 9 Insulating Plate 10 Glass Epoxy Resin Base Material 11 IC 12 Bonding Sheet 13 Through Hole L1 1st conductor layer L2 2nd conductor layer L3 3rd conductor layer L4 4th conductor layer

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】 ICのリード端子接続用の導体パターン
を多層基板の表面に形成し、上記導体パターンを多層基
板の共通スルーホールと内層パターンを介してピン挿通
用スルーホールに接続し、上記ピン挿通用スルーホール
には接続ピンを植立し、当該ピン先端を多層基板の裏面
に突出してなるICピッチ変換基板。
1. A conductor pattern for connecting a lead terminal of an IC is formed on a surface of a multi-layer substrate, and the conductor pattern is connected to a through hole for pin insertion through a common through hole and an inner layer pattern of the multi-layer substrate to form the pin. An IC pitch conversion board in which connection pins are set up in the through holes for insertion and the tips of the pins are projected on the back surface of the multilayer board.
JP1994009385U 1994-07-08 1994-07-08 IC pitch conversion board Expired - Lifetime JP3008887U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1994009385U JP3008887U (en) 1994-07-08 1994-07-08 IC pitch conversion board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1994009385U JP3008887U (en) 1994-07-08 1994-07-08 IC pitch conversion board

Publications (1)

Publication Number Publication Date
JP3008887U true JP3008887U (en) 1995-03-20

Family

ID=43144702

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1994009385U Expired - Lifetime JP3008887U (en) 1994-07-08 1994-07-08 IC pitch conversion board

Country Status (1)

Country Link
JP (1) JP3008887U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998043295A1 (en) * 1997-03-21 1998-10-01 Sony Chemicals Corp. Circuit board and production method thereof
US7479016B2 (en) 2005-07-26 2009-01-20 Yamaichi Electronics Co., Ltd. Semiconductor device socket

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998043295A1 (en) * 1997-03-21 1998-10-01 Sony Chemicals Corp. Circuit board and production method thereof
US7479016B2 (en) 2005-07-26 2009-01-20 Yamaichi Electronics Co., Ltd. Semiconductor device socket

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