JP3005456B2 - Vector processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector processing device.

[0002]

2. Description of the Related Art In general, a vector processing device simultaneously controls a plurality of data from a vector operation unit at the same timing in order to process a large amount of data between a main storage device and a register or an arithmetic unit at a high speed. It is supplied continuously to the unit to achieve high speed.

Conventionally, as shown in FIG. 2, this type of vector processing apparatus has four input ports for each vector element request, input registers 21a to 21d for each input port, Buffers 22a to 22a operating in the same manner for buffering when a port conflict occurs.
22d, buffer read registers 23a to 23d,
An arbiter 26 for detecting port conflicts, performing buffer control and crossbar control, a crossbar 24 for selecting an input element of each output port according to a control signal of the arbiter 26, and output registers 25a to 25d corresponding to the output ports.

In this conventional vector processing device, the main storage device is interleaved with 8 bytes as one port, the minimum access unit is 8-byte access, and
The byte memory access instruction is also performed in units of 8 bytes.

FIG. 3A shows an address of each vector element (hereinafter referred to as an element) at the time of a vector load / store instruction for explaining the conventional example and the present invention, and a port to which each element is output for each element. Shown in In FIG. 3A, assuming that the base address of the vector instruction is “0” and the distance is “4”, elements 0, 1, element 2, 3,.
It can be seen that two consecutive elements become output ports.

Next, the operation of the conventional vector processing apparatus (FIG. 2) at the time of the vector instruction of FIG. 3A will be described.
First, each of the input registers 21a to 21d has an element 0
, And sequentially stored for every four elements. At a certain timing, the arbiter 26 detects a port conflict with respect to the elements 0 to 3 stored in the read registers 23a to 23d. In this case, the elements 0 and 1 are directed to the output port 0, and the elements 2 and 3 are directed to the output port 1, so that port conflict occurs. When a port conflict occurs, the arbiter 26 detects the element having the highest priority (element having the smallest element number) of the conflicting element, and the selector for the output port 0 of the crossbar 24 selects the element 0 of the read register 23a and the element of the crossbar 24. In the selector for the output port 1, the element 2 of the read register 23c is selected and stored in the output registers 25a and 25.

At this time, the arbiter 26 issues a hold request due to the occurrence of the conflict, and the read registers 23a to 23d hold and the buffers 22a to 22d
Holds the read address of the buffer and maintains that state until the hold request is released. That is, the elements input to the input registers 21a to 21d in the continuous liquid are buffered in the buffers 22a to 22d, and requests at the same timing are buffered in the same word in each buffer. This is a process performed to maintain the order of memory access to the same address between elements in the same instruction or between instructions.

For the elements 1 and 3 remaining due to the contention, the contention is detected at the next timing. Since no port contention occurs, the hold request from the arbiter 26 is released and the read register 23a 23d stores four elements of elements 4 to 7 at the next timing. Or later,
Similar processing is performed until the end of all elements.

FIG. 5A is a timing chart showing the above operation, and shows the output port arrival timing of each element when the timing when the elements 0 and 2 arrive at the output ports 25a to 25d is set to 1. . Also, the port conflict detection target element and the number of output port register arriving elements at one timing are shown. In the case of the vector instruction shown in FIG. 3A, it can be seen that output 2 is an element for each input of four elements at each timing due to port conflict. This results in a maximum throughput of １ ／.

FIG. 3B is a diagram for explaining the conventional example and the present invention, in which each vector element at the time of a vector load / store instruction when only the distance is 12 with respect to the case of FIG. And the output port to which each element is output for each element.

FIG. 5B is a timing chart of the conventional example of FIG. 2 in the case of FIG. 3B.

[0012]

In the above-described conventional vector processing apparatus, the throughput becomes 1/2 of the maximum value in a 4-byte vector load / store instruction (in the case where the distance is an odd multiple of 4 bytes). As a result, there is a disadvantage in that the performance of the main memory access time of the vector load and store instructions is seriously degraded.

[0013]

A vector processing apparatus according to the present invention has a plurality of vector operation units for performing a vector operation for each vector element, a memory having a plurality of banks and a plurality of ports which can be accessed independently. A vector comprising: a plurality of main storage units configured as modules; and a memory access control unit that can independently perform a plurality of data transfers between the vector operation unit and the main storage unit in byte width units of each port in the main storage unit. In the processing device, n (n ≧ 2) input registers for holding vector element requests in the order of element numbers in vector element units input in a pipeline manner from the vector operation section to the memory access control section. And n input buffers for storing held contents corresponding to the input registers, and vectors read from the input buffers N read registers for storing requests in elementary units, and even number arbiters, odd number arbiters, and even number arbiters for competing and arbitrating element numbers for the n vector element requests held in the read registers. Each of the contention arbitrated vector element request data is sent to an output port designated by the address of the vector element request by an even crossbar, an odd crossbar, and up to two vector element request data from the even crossbar and the odd crossbar.
A vector processing device, wherein an output buffer corresponding to the output port is provided, which is capable of storing even-numbered crossbar data at the same time, so that the output order is first.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. This vector processing apparatus can transfer data in parallel in units of 8 bytes.

In FIG. 1, four input registers 11a are provided.
Reference numerals 11d denote registers for receiving vector load / store requests from a vector operation unit (not shown). A plurality of (for example, four elements) requests for each element are transferred to the input ports 0 to 3 in the order of element numbers.

The four buffers 12a to 12d are buffers for continuously buffering requests issued from the vector operation unit when queuing due to output port contention occurs, and all buffers have read addresses and write addresses. Common and perform the same operation.

Four read registers 13a to 13d
Is a register for reading out the buffers 12a to 12d, and is a target of output port conflict detection.

The input port of the even-numbered port arbiter 16a is an even number (ports 0, 2,..., Readout registers 13a, 13a).
This is an output port conflict arbitration circuit for only the element c), and the odd-numbered port arbiter 16b has an odd-numbered input port (ports 1, 3,... read-out registers 13b, 13d).
And an arbiter that operates independently. This is because even if the request of the vector element of input port 0 and the request of the vector element of input port 1 are directed to the same output port, the arbiter is different, so that it seems that no strong man has occurred, and output port conflict is detected. No, it means that both requests can be output.

If the output port conflict is detected in either of the even port arbiter 16a and the odd port arbiter 16b, the read register 1
The read addresses of the buffers 3a to 13b and the buffers 12a to 12d are held until all output port conflicts are eliminated, and the arbiter participation of subsequent requests is suppressed.
This is a process for maintaining the order of accessing the same address between elements in an instruction or between elements between instructions.

The even port crossbar 14a is controlled by the even port arbiter 16a, and transfers only the vector element request of the even input port to the output port (four ports in the example) according to the output port contention arbitration result. The odd-numbered crossbar 14b is similarly connected to the odd-numbered port arbiter 16
b, and transfers only the vector element request of the odd input port to the output port.

Output buffers 15a to 15d are provided corresponding to the respective output ports, and one output buffer simultaneously receives a maximum of two vector element requests sent from each of the even port crossbar 14a and the odd port crossbar 14b. The buffer is a storable buffer and always stores a vector element request from an even-numbered port crossbar with priority so that the output order is first.

FIG. 3 is used again to explain the operation of this embodiment.

FIG. 4A shows a vector element according to the present invention under the relationship between the address of each vector element at the time of the vector load / store instruction shown in FIG. 3A and the output port from which each element is output. Indicates the output status of the request. This operation will be described in detail with reference to FIG.

Elements 0 to 3 are input ports 0 to 3
And stored in the input registers 11a to 11d in the order of element numbers. At the next timing, four elements of elements 4 to 7 are sent to the input port. Thereafter, at each timing, four elements are continuously sent by the pipe run method and sequentially stored in the input registers 11a to 11d. .

The first four elements, elements 0-3, are buffer 1
Readout registers 13a to 13d via 2a to 12d
Are stored in the order of element numbers. Until that time, valid elements were not stored in the read registers 13a to 13d. Here, output port conflicts are checked by the odd port arbiter 16a and the even port arbiter 16b. The even port arbiter 16a checks the output ports of the elements 0 and 2 stored in the even ports (ports 0, 2,... 13a, 13c) of the read register. In this case, since the element 0 is the output port 0 and the element 2 is the output port 1 from FIG. 3 (A), no output port conflict occurs.
Element 0 controls port 0 and element 2 controls output port 1. On the other hand, the odd port arbiter 16b is an odd port (ports 1, 3...
The output ports of the elements 1 and 3 stored in (b, 13d) are checked.

In this case, since the element 1 is the output port 0 and the element 3 is the output port 1 from FIG. 3 (A), no output port contention occurs. Therefore, the elements 1 and 3 are each connected to the output port by the crossbar 14b. 0, element 3 controls sending to output port 1. Here, even port arbiter 1
6a and the odd-numbered port arbiter 16b do not detect an output port conflict, respectively. Therefore, no hold occurs, and the subsequent elements 4 to 7 are stored in the read registers 13a to 13d at the next timing. .

On the other hand, the element 0 is sent from the even-numbered crossbar 14a and the element 1 is sent from the odd-numbered crossbar to the output buffer 15a corresponding to the output port 0. Here, the output buffer 14
“a” stores the element 0 from the even-numbered port crossbar in the order of output, and stores the element 1 from the odd-numbered port crossbar in the order following the element 0. Similarly, output buffer 1 corresponding to output port 1
The element 2 is sent from the even crossbar 14a and the element 3 is sent from the odd crossbar to 5b. Here, the output buffer 14b
Stores the element 2 from the even-numbered port crossbar in the output order first, and stores the element 3 from the odd-numbered port crossbar in the order following the element 0. Then, at the next timing, element 0 from output port 0,
The element 2 outputs from the output port 1, and the elements 1 and 3 output at the next timing.

Similarly, the following elements 4 to 7 are arbitrated by the even port arbiter, but no output port conflict is detected. As can be seen from the output ports of the respective elements in FIG. 3A, the output elements are not detected, and four elements are read out by the read register 13 at each timing.
a to 13d, and are processed. This state is shown in FIG. 3 (C). If the timing at which the elements 0 and 2 are output is 1, the elements 1 and 3 remaining in the output buffers 15a and 15b are output at the timing 2 and at the same time, the subsequent elements 4 and 6 are output. After the output of the first two elements, four elements are output at each timing.
Timing 7 is when all the elements are output. This is a significant improvement in throughput as compared with the conventional configuration, and it can be seen that the larger the element, the closer to the maximum throughput (four element output per timing).

FIG. 4B is a timing chart of the present embodiment in the case of FIG. 3B. By comparing with FIG. 5B, the present invention has a much higher throughput than the conventional configuration. As can be seen, the present invention improves the throughput of vector memory access instructions. In the embodiment, four input ports and four output ports are used. However, it is apparent that any number of ports can be used in the same manner. Further, the distance is 4 bytes (4 bytes × 1) in FIG. 3A and 12 (4 bytes × 3) bytes in FIG. 3B, but the distance of the 4-byte memory access instruction is (4 bytes × odd number). ) Also improves the throughput over the prior art.

[0031]

As described above, according to the vector processing apparatus of the present invention, the contention arbitration is performed on the even-numbered port arbitration circuit and the odd-numbered port arbitration circuit so as to suppress the occurrence of the output port contention of the vector load and store instructions. The division into the target contention arbitration circuit suppresses a drop in the contention in the contention arbitration, thereby improving the throughput. For example, in the case of a 4-byte vector memory access instruction, the throughput is improved about twice.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a vector processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a conventional vector processing device.

FIG. 3 is a timing chart for explaining the operation of the present invention.

FIG. 4 is a timing chart for explaining the operation of the embodiment of the present invention.

FIG. 5 is a timing chart for explaining the operation of the conventional example.

[Explanation of symbols]

 11a to 11d Input register 12a to 12d Input buffer 13a to 13d Read register 14a Even port crossbar 14b Odd port crossbar 15a to 15d Output buffer 16a Even port arbiter 16b Odd port arbiter 21a to 21d Input register 22a to 22d Input buffer 23a to 23d Read Register 24 Crossbar 25a-25d Output register 26 Arbiter

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 17/16 G06F 12/06

Claims (1)

(57) [Claims] 1. Perform a vector operation for each vector element
It has multiple vector operation units and multiple banks,
Memory module having a plurality of accessible ports
A plurality of main storage units, and the vector operation unit
A plurality of data transfers between the main storage units are stored in the main storage unit.
Memory access that can be performed independently for each port
Access controlWhenIn a vector processing device comprising:
The memory access control unit includes:Requires vector element request
In prime orderN (n ≧ 2) input registers to be stored;These n Input registerThe vector element like from
EstToRespectivelyN input buffers to store;These n Input bufferThe vector element fromRiku
EstRespectivelyN read registers to be stored, and n read registers held in the read registersSaidvector
Element requestConflicts only with elements whose input ports are even
An even port arbiter for arbitration, N vectors stored in the read register
Conflicts only with elements with odd input ports in element requests
An odd port arbiter for arbitration,  The even arbiterEach vector element that has been arbitrated by
Request is forwarded to the specified output port by address
An even port crossbar to Each vector element contention arbitrated by the odd arbiter
Request is forwarded to the specified output port by address
An odd port crossbar to The even port crossbar and the odd port crossbar
Of up to two vector element requests transferred from
The vector transferred from the even port crossbar.
The two vectors so that the elementary request is output first
Stores element requests Output buffer
And a vector processing device.