JP3000941B2 - Distributed logic simulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a distributed logic simulator, and more particularly, to a distributed logic in which a logic description of a model to be simulated is distributed to a plurality of simulation processors for performing a logic simulation by distributing the logic description of the model to the simulation processor. It is about a simulator.

[0002]

2. Description of the Related Art As a conventional distributed simulation method for a logic circuit, there is a method disclosed in Japanese Patent Application Laid-Open No. 3-252870, and FIG. 10A shows an example thereof. To briefly describe this example, a method in which a plurality of simulation terminals 101 to 10n are connected to a host computer 100 is used.

In this method, as shown in the flow chart of FIG.
The simulation is performed based on a command from 00, and the simulation result is returned to the host computer 101. The simulation results of all terminals are once collected in the host computer, new data is created from the host computer, sent to the terminal, and the next simulation is instructed.

In this method, the reference clock and input / output pin information for the simulation are managed by the host computer 100, and each of the terminals 101 to 10n simulates data given from the host computer 100 and only returns the result to the host. It only has the function of. In addition, since the simulation model is created and managed by each terminal, the simulation load among the terminals is not equalized.

[0005]

The first problem is that since the connection between the host computer and each terminal is in a star system, the communication traffic of the host computer becomes enormous as the number of terminals increases. For this reason, in a network having a large communication latency, each terminal waits for a response from the host computer, and the efficiency of distributed processing deteriorates.

[0006] The second problem is that the host computer needs a processing capacity in proportion to the increase in the scale of the simulation, and each terminal operates between the end of the processing of each terminal and the end of the processing of the host computer. The point is that it is not possible to start the next process. This is a factor that reduces the degree of parallelism in the distributed processing. When the degree of parallelism decreases, the effect of the number of terminals decreases, leading to a reduction in simulation speed.

A third problem is that the simulation load of each terminal becomes uneven because model creation is closed at each terminal. When the load of a certain terminal is higher than that of another terminal, in the simulation, the processing of that terminal is rate-determining, and the processing cannot be delegated to a lightly loaded terminal.

Due to the above problems, there is a practical limit to the host computer system that supervises the simulation in order to simulate a large-scale logic description of several millions to tens of millions of gates.

SUMMARY OF THE INVENTION The present invention has been made in view of such problems of the prior art, and it is an object of the present invention to completely disperse the simulation of a simulation target model to each of the above-described simulation processors as terminals. Another object of the present invention is to provide a distributed logic simulation in which parallel processing is performed.

[0010]

According to the present invention, a logical description of a model to be simulated is distributed to a plurality of simulation processors connected to each other via a network and performing a logic simulation, by performing the distributed processing. A distributed logic simulator comprising: a model distributing means for distributing and assigning a logical description of the simulation target model to each of the simulation processors;
And a running procedure dispersion means the execution procedure of the simulation each dispersed allocated to each of said simulation processors based on this model the dispersion result, the motor
The Dell dispersion means is configured to execute a
Logical rules for each unit that composes this model based on the logical description
Means for calculating the amount of memory required for simulation
And the unit mutual of each unit based on the logical description.
Means for calculating the inter-dependency, and the simulation program
A performance parameter indicating the performance of each of the processors,
Model, memory size, and inter-unit dependence.
Each unit cost according to the calculated cost formula
Means for calculating the minimum cost for each unit
For this simulation processor
Logical description of the corresponding unit for the translation processor
And means for allocating each of said simulation processors is configured to perform the simulation in parallel in accordance with the assigned distribution model and distributed execution procedure, each distributed execution of its simulation of the simulation processor There is provided a distributed logic simulator characterized in that means for distributing and storing results are provided, and necessary results among the distributed execution results of these simulation processors are collected and edited.

[0011]

[0012]

Further, the performance parameters include a communication capacity and a communication speed of the network.

The operation of the present invention will be described. In the present invention, in order to disperse the simulation, the dispersion of the simulation model and the dispersion of the simulation procedure are mainly performed. First, in the distributed processing of the simulation model, the model that maximizes the efficiency of the distributed processing is divided with reference to the distributed parameter information file. This distribution parameter information file describes information that is key to the efficiency of distributed processing, such as the processing capacity of each processor, the communication capacity and communication speed of the network, and the like.

Further, by generating a simulator specialized for a model by translating the distributed model information, it becomes unnecessary to read and interpret model information, which is indispensable for a general-purpose simulator, and a higher-speed simulation can be executed. Moreover, since the individual processors translate the distributed model information in parallel, the execution time of the translation process is extremely short.

Next, in the distribution of the simulation procedure, since the information of the distribution model is created by the above-mentioned model distribution processing, the simulation procedure described by the user is executed based on the information of the distribution model. Is converted into one control information. Each simulator receives its own control information and executes the simulation. Therefore, the centralized management by the host computer system is not required, and the individual processors independently execute the distributed simulation.

Note that, in addition to the above-described model distribution and procedure distribution, simulation record distribution is also performed. In this distribution of the simulation record, each simulator individually records the execution result of the simulation. The user selects only the necessary results, gives instructions to edit and retrieve the information to the result editing process, and the result editing process communicates with the processor holding the necessary execution results,
Receives the result, edits it in the format desired by the user, and displays it.

[0018]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a system block diagram of one embodiment of the present invention. In FIG. 1, a processor 10 and processors 11 to 1n are connected by a network 51,
It is possible to communicate with each other. Each processor:
The communication processing 31 communicates with another processor via the network 51.

In the processor 10, a model distribution process 32 and a control information process 33 are operating. Processors 11 to 1n are simulation processors for performing each simulation of the distribution model. In each of these processors, a simulator generation process 35 is operating. are doing.
The simulator 40 generated by the simulator generation process 35 is executed by the processors 11 to 1n.

In order to refer to the simulation result from the terminal 52, a result editing process 34 is operated by the processor 10.

A user creates a logic description file 21 to be simulated and an execution procedure file 22 for the simulation, and the processor 10 performs processing.

The logical description file 21 is subjected to model distribution processing and processor load distribution processing by a model distribution process 32, and is transferred to the processors 11 to 1n as a distributed model description file 23. At this time, the model distribution process 32 reads the distribution parameter description file 27 and performs processing in consideration of the distribution processing efficiency. Further, the model distribution process 32 describes the distribution information of the model in the distribution model information file 26 and transfers the model to the control information process 33.

The distributed model description file 23 is processed by the simulator generation process 35 on the processors 11 to 1n, and a distributed simulator 40 is created.

On the other hand, the simulation procedure file 22
Are controlled by the control information generation process 33.
1n is converted into a distributed control information file 24 to be provided to the distributed simulator 40 on 1n. At this time, the distribution model allocation information and the like in the distribution model information file 26 are referred to.

The distributed simulator 40 executes a simulation in accordance with the procedure described in the distributed control information file 24. The execution result of the simulation is written in the result file 25.

The user refers to the terminal 52 on the result of the completed simulation. The user instructs the result editing process 34 from the terminal 52, and the result editing process 3
4 extracts necessary information from the result file 25 on the processors 11 to 1n based on the instruction, edits it, and displays it on the terminal 52.

In FIG. 1, the result editing process 34 is executed by the processor 10 for the sake of convenience. However, it is not always necessary to execute the result editing process 34. The terminal 52 is directly connected to the network 51 and the result editing process 34 is executed. May be executed on the terminal 52.

Next, an example of the operation of the embodiment of the present invention will be described. FIG. 2A is an example of a simulation model. This is a model of a multi-CPU configuration in which a processing device (CPU) 61, a processing device (CPU) 62, and a storage device (MEM) 63 are connected by a system bus (BUS) 64.

FIG. 2B shows an example of a simulation execution procedure. Load instructions 71 and 72 to MEM 63
And an execution instruction 73 of the CPU 61, an execution instruction 74 of the CPU 62, and a stop instruction 75 of the simulation. FIG. 3 is an equivalent block diagram equivalent to FIG. 1, in which processors 11 to operate the simulators 40-1 to 40-3.
13 shows a case where there are three units.

First, the simulation model is processed by the model distribution process 32 and divided into processors. Here, for convenience, the CPU 61 is the processor 11, the CPU 6
2 is divided into the processor 12 and the MEM 63 is divided into the processor 13. The system bus (BUS) 64 is a line connecting each block and does not need to be assigned to a processor. From the viewpoint of a model and a simulator, the network 51 plays a role of a system bus. This model assignment is recorded in the distributed model information file 26 and passed to the control information generation process 33.

Next, the control information generation process 33 processes the execution procedure of the simulation shown in FIG. MEM6
Instructions 71 and 72 for 3 are sent to processor 13 by CPU
Instruction 73 to 61 is sent to processor 11 by CPU 62.
Are stored in each control information file 24 to the processor 12. The command 75 means the stop of the simulation, and all the control information files 24
Is stored in

Each control information file 24 is sent to the processors 11 to 13, and the simulation is started.
Simulator 40-3 (MEM) on processor 13 executes instructions 71 and 72. The execution of the processing (TH1) loaded into the MEM by the instruction 71, that is, the execution of the instruction 73 is performed by the simulator 40-1 (CPU 61) on the processor 11.
It is. Simulator 40-1 of processor 11 (CPU6
1) reads out and executes the processing (TH1) from the simulator 40-3 (MEM) of the processor 13 via the network 51.

In the same procedure, the simulator 40-2 (CPU 62) on the processor 12 executes the process (TH2), that is, executes the instruction 74. The simulation ends when each processor executes the instruction 75, that is, the stop of the simulation. The result of the simulation is written to the result file 25 of each processor.

When the simulation is completed, the user calls the result editing process 34 from the terminal 52 and instructs the display of the simulation result. Result editing process 34
Extracts necessary information from each result file 25 and displays it on the terminal 52. The user sees it and the CPU
When the instruction to display the detailed simulation results at 61 is issued, the result editing process 34 extracts the detailed information from the result file 25 on the processor 11 and performs the detailed display in the format specified by the user.

The above example is for a simulation target model having a simple configuration as shown in FIG. 2. However, when this model is a complex computer system as shown in FIG. Will be described in detail. Note that, depending on the purpose, configuration, and the like of the logic circuit model to be simulated, the division algorithm and the function formula for cost calculation described later may be changed as appropriate, but a typical example is shown here.

FIG. 4 shows an example of a vector processing computer. A scalar processor (SPU) 81 and a vector processor (VPU) 82 perform vector calculation, and exchange data with a register file (RF) 84. The instruction execution unit (IEU) 83 stores an instruction cache (I
C) The instruction is taken out from 85 and executed.

The data cache (DC) 86 temporarily stores data.
6 is connected to a main memory (MEM) 89 via a memory control unit (MMU) 87. Also, not shown I /
It is assumed that the O system is connected via an input / output control unit (IOP) 88.

The logic circuit model shown in FIG. 4 is executed by the simulator having the configuration shown in FIG. FIG. 5 shows the simulation processor (PROC) 11-1n of FIG.
And a communication network 5 connecting these processors
In this example, there are seven simulation processors 11 to 17, and there are crossbars NET-A, B, optical fiber NET-C, and Ethernet NET-D as communication networks. Shall be.

The processors 11 to 14 are connected to the network NE.
The processor 1 is connected to the TA and the network NET-D.
5 and 16 are network NET-B and network N
In ET-D, the processor 17 is connected to the network NET-D.
It is connected to the. In addition, network NET-A, B
Are interconnected by a network NET-C.

The processor 17 is composed of the other processors 11 to 1
6, the disk 90 has a larger capacity than that of the processor 6, and only the disk 90 of the processor 17 is shown.

FIG. 6 is a flowchart showing the flow of the operation of the model distribution processing 32 shown in FIG. 1. The model distribution processing when the model of FIG. 4 is executed by the simulator having the configuration of FIG. 5 will be described below. .

First, the model distribution process 32 receives the logical description 21 (see FIG. 1) of the model shown in FIG. 4 (step S1), and calculates data for each unit of the model and the degree of dependence between units. Thus, a data table as shown in FIG. 7 is obtained (steps S2 and S3).

In FIG. 7, the logic scale is the gate scale (the number of gates, unit K thereof) of the logic circuit constituting each unit;
1,000), and the required memory indicates the amount of memory required for the simulation. The connection ratio (inside the unit: outside the unit) indicates the dependency of the logic inside the unit on the external input and the cost associated with division.

The inter-unit connection speed rate and the inter-unit connection dependency rate are shown in the upper and lower portions of the oblique lines for each unit for each other unit.

The inter-unit connection speed ratio indicates a transfer speed ratio between the units. For example, the ratio of RF to DC is "0.5".

The inter-unit connection dependency ratio indicates the connection dependency to each unit. For example, RF is 35% for SPU, 35% for VPU, and 5% for IEU.
%, 25% for DC (100% in total), and 0% for other units.

Next, the model distribution process 32 is executed by the simulation processor 11 to 17 and the communication network N shown in FIG. 5 from the distribution parameter file 27 (see FIG. 1).
A parameter indicating each performance of ET-A to ET-D is input (step S4).

As this parameter, FIG.
Each value is described in the table shown in FIG. As shown in FIG. 8A, the parameters of the simulation processors 11 to 17 are the names of the CPUs (P5, P5,
6), a clock indicating the operating speed of the CPU, the memory capacity of the processor, and the disk capacity of the processor.

For each communication network, as shown in FIG. 8B, its transfer capacity, transfer delay between connection units, network system, and connection unit name of the network are described respectively. I have.

Next, the distributed processing 32 calculates a simulation cost for each unit based on each data shown in FIGS. 7 and 8 (step S5). It is assumed that a function as an equation for this calculation is defined in advance as shown in FIG. 9A, for example.

This function is for calculating the unit calculation cost, the unit division cost, and the unit communication cost of the simulation based on the data obtained in FIGS.

The unit calculation cost is proportional to the unit size fcu and inversely proportional to the processor capacity fcp. The unit division cost is proportional to the intra-unit connection division cost fdu and inversely proportional to the network capability fdp. The unit communication cost is proportional to the unit connection cost fxu and inversely proportional to the network capability fxv.

An example of the calculation result obtained in this way is VP
U is shown in FIG. 9 (B). With this result,
It can be seen that the cost is lowest when VPUs are allocated to the processors 11 and 12. Note that the communication cost varies depending on how other units are allocated, but the value in FIG. 9B shows the minimum value, that is, the case where the allocation with the lowest communication cost is performed.

The cost calculation is similarly performed for the other unit assignments, and the assignment is determined so that the cost is minimized (step S6).

In the control information generation process 33 shown in FIG. 1, the simulation procedure 22 is allocated and distributed to the simulation processors (simulators) corresponding to the distributed units based on the model information 26 thus distributed. The distributed processing method in this case is shown in FIG.
A method similar to the method described in (B) is used.

[0057]

The first effect is that the large-scale logic simulation is completely distributed and executed efficiently. When distributing the model, the distributed parameter information file is referred to, the processing of the model is performed in consideration of the processing capacity of each processor, the communication capacity and the communication speed of the network, etc. Distributed processing in consideration of the communication processing efficiency. In addition, the translation of the distributed model information is executed in a distributed manner.

Also, by converting the simulation control information into information adapted to each simulator in advance, the control of the simulation is dispersed, and the individual simulator performs independent simulation. In addition, since each processor holds the simulation result, useless communication does not occur in the network, and only data required by the user can be extracted.

The second effect is to speed up the simulation. Since the translation process of the model is performed in a distributed manner, the execution time of the translation process is extremely short. In addition, by generating a simulator specialized for a model by translating the distributed model information, it is not necessary to read and interpret model information, which is indispensable for a general-purpose simulator, and a higher-speed simulation can be executed.

Further, there is no need for a processor for controlling the whole, such as the host computer, and there is no need for each processor to stop uselessly for processing by the host computer.

[Brief description of the drawings]

FIG. 1 is a system block diagram of an embodiment of the present invention.

FIG. 2A is a diagram illustrating an example of a simulation target model, and FIG. 2B is a diagram illustrating an example of a simulation execution procedure;

FIG. 3 is a diagram illustrating a distribution example of the target model in FIG.

FIG. 4 is a diagram showing another example of a simulation target model.

FIG. 5 is a diagram illustrating a configuration example of a simulator.

FIG. 6 is a flowchart showing an operation of a model distribution process 32 of FIG. 1;

FIG. 7 is a diagram showing, as a table, data of each unit of the model of FIG. 4 and a degree of dependence between units;

FIG. 8 is a diagram showing an example of a distribution parameter file 27 of FIG.

9A is a diagram illustrating an example of a calculation formula of a simulation cost, and FIG. 9B is a diagram illustrating an example of a calculation result of a simulation cost in the case of a VPU.

FIG. 10A is a block diagram of a conventional distributed logic simulator, and FIG. 10B is an operation flowchart thereof.

[Explanation of symbols]

 Reference Signs List 10 processor 11 to 1n simulation processor 21 logic description file 22 simulation procedure file 23 model description file 24 control information file 25 result storage file 26 distributed model information file 31 communication processing 32 model distributed processing 33 control information generation processing 34 result editing processing 35 simulator Generation processing 40 Simulator

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 17/50 G06F 11/26

Claims (2)

(57) [Claims] 1. A logical stain connected to each other via a network.
Simulation processors for simulation
Before the logical description of the model to be simulated
Distributed processing by assigning to each simulation processor
A distributed logic simulator configured to execute the simulation for each of the simulation processors.
Divide the logical description of the model to be simulated
Means for distributing the model, and the simulation program
Run the simulation for each of the processors
Execution procedure distributing means for distributing and allocating each,The model distributing means is configured to control the simulation target model.
Based on the logical description of the
Calculate the logic scale and the amount of memory required for simulation
Means for each unit based on the logical description.
Means for calculating the interdependence rate, and the simulation
Performance parameters indicating the performance of each of the
Based on logical scale, amount of memory, and inter-unit dependency ratio,
Each of the units according to a predetermined cost calculation formula
Means for calculating cost, and cost calculated for each unit
For a simulation processor that minimizes
On the corresponding unit for the simulation processor
Means for assigning a logical description,  Each of the simulation processors,Assigned
In accordance with the distributed model and distributed execution procedure
A simulation of each of the simulation processors.
Means for distributed storage of the distribution execution results of the
These are the results of distributed execution of each simulation processor.
It is characterized by collecting necessary results and making it editable
Distributed logic simulator. 2. The distributed logic simulator according to claim 1, wherein the performance parameters include a communication capacity and a communication speed of the network.