JP3099398B2 - Constant current circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a constant current circuit formed on a semiconductor integrated circuit by MOS transistors.

[0002]

2. Description of the Related Art A conventional constant current circuit is disclosed in
No. 83, a constant current source MOS transistor having a drain connected to an electronic circuit, and a constant current source MOS transistor.
And a bias circuit for applying a sum of the threshold voltage of the MOS transistor having the same polarity as the transistor and the output of the constant voltage source between the gate and the source of the constant current source MOS transistor.

A constant voltage source is a MOS having the same polarity and the same geometric size.
Different threshold voltages are generated by implanting ions (channel doping) into one of the gate channel portions of the transistor pair, and a difference voltage between the threshold voltages is output.

[0004]

In the above-mentioned prior art, the MOs different from each other due to variations in the channel doping amount or the like.
The fact that the difference voltage between the threshold voltages of S-transistors fluctuates is not taken into account, and the current value flowing through the constant current source MOS transistor consequently fluctuates according to manufacturing variations in the threshold voltage of the MOS transistor. There was a problem to do.

An object of the present invention is to use a general manufacturing process for manufacturing one type of each of an N-channel and a P-channel MOS transistor, to have a simple configuration and to be less affected by manufacturing variations in the threshold voltage of the MOS transistor. It is to provide a current circuit.

[0006]

In order to achieve the above-mentioned object, the present invention provides an M transistor having the same polarity as a constant current source MOS transistor.
A plurality of OS transistors are vertically stacked at a specific size ratio between a power supply and a ground, and a voltage of a sum of a threshold voltage of a MOS transistor having the same polarity as the constant current source MOS transistor and a divided voltage of a power supply voltage is applied to the OS transistor. It is provided between the gate and the source of the constant current source MOS transistor.

[0007]

According to the configuration of the present invention, the output of the bias circuit is the sum of the threshold voltage of the MOS transistor having the same polarity as the constant current source MOS transistor and the divided voltage of the power supply voltage. The current when the constant current source MOS transistor operates in the saturation region is proportional to the square of the difference between the output of the bias circuit and the threshold voltage, and consequently is proportional to the square of the power supply voltage.

[0008]

An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 shows an example in which a bias circuit is an N-channel MOS.
This is an embodiment in which transistors (hereinafter abbreviated as NM) 1, 2, and 3 are vertically stacked in three stages. When the size ratio of NM1, NM2, NM3 is set so as to satisfy Expression (1), the relationship of Expression (2) is established.

[0010]

(Equation 1)

(Β ₁ : conductance coefficient of NM1;
β ₂ : conductance coefficient of NM2, β ₃ : conductance coefficient of NM3)

[0012]

(Equation 2)

(Vt: NM threshold voltage, I ₁ : NM1
Drain current) bias circuit output Vb (constant current source MO
The gate-source voltage of the S-transistor) is given by equation (2)
It can be expressed by equation (3).

[0014]

(Equation 3)

(V _DD : power supply voltage) The current I when the constant current source NM4 operates in the saturation region is given by the equation (4) from the equation (3).
Becomes

[0016]

(Equation 4)

(Β ₄ : conductance coefficient of NM4) From the above, according to the present embodiment, a constant current is obtained which is less affected by manufacturing variations in the threshold voltage of the N-channel MOS transistor.

FIG. 2 shows that the bias circuit is a P-channel MOS.
This is an embodiment in which transistors (hereinafter abbreviated as PM) 6, 7, 8, and 9 are vertically stacked in four stages. When the size ratio of PMs 6, 7, 8, and 9 is set so as to satisfy Expression (5), a constant current that is less affected by manufacturing variations in the threshold voltage of the P-channel MOS transistor can be obtained as in FIG. .

[0019]

(Equation 5)

(Β ₆ : conductance coefficient of PM6,
(Β ₇ : conductance coefficient of PM7, (β ₈ : conductance coefficient of PM8, (β ₉ : conductance coefficient of PM9))

[0021]

According to the present invention, the N channel and the P channel M
Using a general process of manufacturing one OS transistor at a time, a constant current circuit that is not easily affected by manufacturing variations in the threshold voltage of the MOS transistor can be formed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a constant current circuit according to the present invention in which a bias circuit is formed by vertically stacking three stages of N-channel MOS transistors.

FIG. 2 is a diagram illustrating a constant current circuit according to the present invention in which a bias circuit is formed by vertically stacking four stages of P-channel MOS transistors.

[Explanation of symbols]

1, 2, 3, 4 ... N-channel MOS transistors, 5 ...
Electronic circuit, 6, 7, 8, 9, 10: P-channel MOS transistor, V _DD : Power supply, Vb: Bias circuit output
(Gate-source voltage of constant current source MOS transistor
Pressure) .

Claims (2)

(57) [Claims] 1. A constant current source MOS transistor having a drain connected to an electronic circuit and determining a current flowing through the electronic circuit, and a MOS transistor having the same polarity as the constant current source MOS transistor and having a gate and a drain commonly connected to each other. While grounding, three units are stacked vertically from the power supply side at a size ratio of 1:16:16, and the sum of the threshold voltage of the MOS transistor having the same polarity as the constant current source MOS transistor and the divided voltage of the power supply voltage is obtained. A constant current circuit, comprising: a bias circuit for applying a voltage between a gate and a source of the constant current source MOS transistor. 2. A constant current source MOS transistor having a drain connected to an electronic circuit and determining a current flowing through the electronic circuit, and a MOS transistor having the same polarity as the constant current source MOS transistor and having a gate and a drain commonly connected to a power source. Four pieces are vertically stacked at a size ratio of 9: 9: 1: 1 from the power supply side between the ground, and a threshold voltage of the MOS transistor having the same polarity as the constant current source MOS transistor and a divided voltage of the power supply voltage. A constant current circuit comprising: a bias circuit for applying a sum voltage between a gate and a source of the constant current source MOS transistor.