JP3082175B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus which operates with low current consumption, and more particularly to a portable information processing apparatus such as a notebook personal computer.

[0002]

2. Description of the Related Art Due to recent technical innovations, small and lightweight portable personal computers have become mainstream. When such a portable personal computer is used outdoors, power is usually supplied from an internal battery such as a battery. However, since the internal battery mounted on a portable personal computer is limited to a small one,
The time that a computer can be used on a single charge is very small. For this reason, many portable personal computers make various efforts to reduce current consumption.

[0003]

By the way, CMOS (Complement), which is often used for a portable personal computer, is used.
(ary MOS) ICs have a correlation between voltage, frequency and current consumption. The higher the voltage, the higher the speed of operation, but the higher the current consumption. For this reason, in a device such as a portable personal computer that requires both high processing speed and low current consumption at the same time, inconsistency occurs at the device level.

[0004] It is an object of the present invention to solve such a contradiction and to provide an information processing apparatus capable of simultaneously increasing the processing speed and reducing the current consumption.

[0005]

In order to solve the above-mentioned problems, an information processing apparatus according to the present invention operates in a low-speed mode operating at a low frequency clock and a low voltage, and operates at a high frequency clock and a high voltage. And a high-speed mode.
Switching means for switching between a low-speed mode and a high-speed mode for a predetermined period when a specific factor including an O access signal or an interrupt signal occurs, and switching between the modes is automatically performed without using software. When switching from the high-speed mode to the low-speed mode, the switching means switches the voltage from the high voltage to the low voltage by the voltage switching signal after a predetermined time has elapsed after switching the clock from the high frequency to the low frequency by the frequency switching signal. Is switched. Another information processing apparatus according to the present invention has a low-speed mode operating with a low-frequency clock and a low voltage, and a high-speed mode operating with a high-frequency clock and a high voltage. A switching means for switching between a low-speed mode and a high-speed mode for a predetermined period when a specific factor consisting of an interrupt signal occurs; a device that requires a refresh signal to be input in a predetermined cycle; And a malfunction preventing means for transmitting a refresh signal to the device for each certain voltage during a voltage change period switched between the voltage and the voltage, and each mode is automatically switched without using software. It is characterized by the following.

[0006]

According to the information processing apparatus of the present invention, normal processing that does not require high-speed operation is executed under a low-speed clock and a low voltage, thereby reducing current consumption. The specific processing requiring high-speed operation is executed at high speed for a certain period by switching to a high-speed clock and a high voltage. As described above, since the clock and the voltage are switched according to the processing content, reduction in current consumption can be realized without reducing the speed of the processing requiring high-speed operation.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a circuit configuration diagram of an information processing apparatus according to one embodiment of the present invention. In the information processing apparatus of the present embodiment,
A CPU block 10 for controlling the entire apparatus;
An input / output block 110 for controlling the LCD 70, a video block 210 for controlling the liquid crystal display device 290, and a power supply 310 for supplying power to these blocks are provided. Further, the video block 210 is supplied with a frequency switching signal from the CPU block 10,
10 is supplied with a voltage switching signal from the CPU block 10. The voltage value of the power supplied from the power supply device 310 to each block can be switched by the voltage switching signal. As described above, the switching between the low-speed mode operating with the low-speed clock and the low voltage and the high-speed mode operating with the high-speed clock and the high voltage are performed by the frequency switching signal and the voltage switching signal issued from the CPU block 10.

Next, regarding the configuration of the CPU block 10, the input / output block 110 and the video block 210,
This will be described with reference to FIGS. FIG. 2 shows the CPU block 1.
FIG. The CPU block 10 includes a CPU 20 for controlling the entire apparatus, a coprocessor 30 such as a floating-point arithmetic processor, a crystal oscillator 40 for generating a clock pulse having a frequency of 40.0 MHz,
A crystal oscillator 50 for generating a clock pulse having a frequency of 2.0 MHz, and a main RAM 6 storing an operating system and application programs.
0 and EP in which BIOS (basic I / O system) is stored
A ROM 70 and a control unit 80 that exchanges signals with the input / output block 110 and the video block 210 are provided. Further, the control unit 80 includes a CP.
U20, a CPU controller 81 for controlling the main RAM 60 and the system bus, and a CPU controller 81
The voltage value of the signal from the crystal oscillators 40 and 50 given to
A voltage converter 82 for converting V to 3V and a voltage converter 83 for converting a voltage value of an output signal from the CPU controller 81 to the input / output block 110 and the video block 210 from 3V to 5V are provided. Further, voltage converter 83 outputs a frequency switching signal to video block 210 and a voltage switching signal to power supply device 310. C
PU 20, coprocessor 30, main RAM 60, EP
The voltage values of the ROM 70 and the CPU controller 81 are
When the voltage switching signal is supplied to the power supply device 310, the voltage changes between 3V and 5V in real time. All operations of the apparatus main body are determined in synchronization with the frequency of the clock signal to the CPU 20. Therefore, just drop the frequency of the clock signal to the CPU before dropping the voltage,
It is possible to synchronously drop the clock frequency of all other devices. For this reason, all control signals are output via the CPU block 10.

FIG. 3 is a block diagram of the input / output block 110. The input / output block 110 has a crystal oscillator 12 for generating a clock pulse having a frequency of 20.0 MHz.
0, a crystal oscillator 130 that generates a clock pulse having a frequency of 16.0 MHz, a VFO circuit 140 that is a variable frequency generation circuit, and a real-time clock 15.
0 and a control unit 160 for controlling the external device 170
And a control unit 164. The control unit 160 includes an input / output controller 161 that performs DMA (direct memory access) control, FDD (floppy disk device) control, interrupt control, printer control, and the like, and a signal that is supplied to the input / output controller 161 from the CPU block 10 and the like. A voltage converter 162 for converting a voltage value from 5V to 3V, and an input / output controller 161
The voltage value of the output signal to the external device 170 from 3V to 5
And a voltage converter 163 for converting the voltage to V. The control section 164 includes a timer control circuit or an RS-232C control circuit. Further, the external device 170 includes an FDD, a printer, a mouse,
RS-232C and keyboard. The external device 170 has a 5V interface for compatibility with conventional devices. Therefore, a voltage conversion circuit 163 is provided so that the signal voltage to the external device 170 does not change even when the internal voltage changes. The voltage value of the input / output controller 161 changes between 3 V and 5 V in real time when a voltage switching signal from the CPU block 10 is supplied to the power supply device 310. Clock signal lines such as the real-time clock 150,
A VFO circuit 140 for FDD based on a circuit system in which voltage characteristics are related in an analog circuit such as an LL circuit,
It must be operated at a constant voltage. Therefore, these interfaces are 5 V level interfaces. Even when the voltage becomes 3 V, the controller section 160 operates normally because the signal from the CPU block 10 has a low frequency. However, the controller section 164 includes a circuit whose frequency must not be changed in real time, such as a timer control circuit and an RS-232C control circuit. Therefore, since the voltage cannot be reduced to 3V, the operation is performed at a voltage of 5V.

FIG. 4 is a block diagram of the video block 210. The video block 210 includes a crystal oscillator 22 for generating a clock pulse having a frequency of 21.0 MHz.
0, a frequency selector 230 that receives a frequency switching signal from the CPU block 10 and converts the frequency of a clock pulse generated by the crystal oscillator 220, an SRAM 240 that stores text data, and a DRAM 250 that stores graphic data. , A CG (character generator) 260 that converts data from the CPU block 10 into a character pattern, a GDC (graphic display controller) 270 that controls screen display, and a control unit 280 that controls a liquid crystal display 290. . The control unit 280 includes an SRAM
240, and a frequency selector 230 provided to the video controller 281.
Voltage converter 282 for converting the voltage value of the signal from CPU and the signal from CPU block 10 from 5V to 3V, and the voltage value of the output signal to liquid crystal display 290 from 3V to 5V.
And a voltage converter 283 for converting the voltage to V. A frequency switching signal is sent from the CPU block 10 to the video block 210. This is video block 2
It is necessary to reduce the frequency while the voltage VDD in 10 is 3V. Further, if the clock frequency given to the video block 210 and the value of the frequency given to the CPU block 10 are significantly different, the video block 210 may malfunction. Therefore, CPU block 1
If the frequency given to 0 is dropped, video block 2
The frequency given to 10 is also dropped. S
RAM240, DRAM250, CG260, GDC2
70 and the video controller 281 have a voltage value of CP
When the voltage switching signal from the U block 10 is supplied to the power supply device 310, the voltage changes between 3V and 5V in real time. Further, the crystal oscillator 220 always operates at a voltage of 5V. This is because the output is not stabilized when the voltage fluctuates. Further, the interface with the outside such as the CPU block 10 is a single 5 V in order to make the bus specifications the same as the conventional one. Therefore, the voltage value of the external signal is converted from 5V to 3V by the voltage converter 282.

The feature of this embodiment is that normal processing is performed under a low-speed clock and low voltage, and when a specific factor such as an I / O access or an interrupt occurs, a high-speed operation is performed for a predetermined time. Switching to clock and high voltage. This is because if a certain IC operates at 5V, the delay time from input to output is 10ns, and if it operates at 3V, the delay time increases to 20ns. Therefore, in order to operate normally at 3 V, the frequency must be reduced as compared with the case of operating at 5 V. The frequency is proportional to the current consumption, and the square of the voltage is proportional to the power consumption. For this reason, in the present embodiment, an epoch-making low power consumption is realized by simultaneously lowering the frequency and the voltage. The switching of the clock is completely performed only by the circuit, and the timing of the switching is adjusted to the refresh period. This is because the bus is released during the refresh period, and the bus always occurs at regular intervals. At the time of voltage switching, the level of the interface between the ICs also changes at the same time. Usually, it takes several ms to several tens ms to change the voltage.
For a signal line changing in the s order, the change in voltage is negligibly small. However, it should be noted that when abnormal noise occurs in the voltage or when the change time is too short to be ignored, the level may be reversed between the interfaces. In this embodiment, the lowest frequency that can be switched is set to the clock frequency corresponding to the lowest performance of the conventional model. As for the voltage value, the value corresponding to the lowest frequency is set as the lowest voltage value. With such considerations, it is possible to operate with a current consumption corresponding to the minimum clock and the minimum voltage that does not impair compatibility with the conventional model.

In this embodiment, the switching of the voltage value and the frequency is completely controlled by hardware without the intervention of software, so that there is no need to change an existing program. FIGS. 5A and 5B show circuit examples in which the voltage value of the power supplied from the power supply device 310 to each block is switched by hardware. In FIG. 5A, the terminal 350 is used.
A voltage signal of 7 V to 15 V (usually output from a Ni-Cd storage battery) supplied from
351 causes the voltage to drop to a maximum of 3 V, and the terminal 35
2 output. Then, the voltage signal output from the terminal 352 is sent to each block. More specifically, a voltage from the control IC 353 is applied to the gate of the FET 351 at certain intervals, and the voltage value output from the terminal 352 is adjusted. Further, a feedback signal is given to the control IC 353, and the interval of the voltage applied to the FET 351 is adjusted.
This feedback signal changes according to the resistance value ratio between the resistors 354 and 355. That is, the resistors 354 and 355
The voltage value of the voltage signal output from the terminal 352 is switched according to the resistance value ratio. Therefore, the resistor 35
A resistor 356 is provided in parallel with the terminal 5 to change the value of the feedback signal by applying a voltage switching signal to the gate of the FET 357, thereby switching the voltage value of the voltage signal output from the terminal 352. A problem with such a circuit is that noise such as undershoot occurs between outputs in an intermediate state where the feedback signal is changing. To solve this problem, FIG.
As shown in (a), a capacitor 35 is connected to the other end of the resistor 354.
8 may be set. FIG. 5B shows another circuit example in which noise does not occur. In FIG. 5B, the terminal 3
A 5 V voltage signal from the power supply 310 and a 3 V voltage signal from the three-terminal regulator 362 are supplied to the FET 60 and selected by the FET 361, and one of the voltage signals is output from the terminal 363. A voltage switching signal is supplied to the gate of the FET 361, and the voltage value of the voltage signal output from the terminal 363 is switched in a time period of about several ms. In this circuit, noise such as that generated in the circuit of FIG. 5A does not occur. That is, as shown in the waveform diagram of FIG. 6, the voltage switching signal that causes the voltage signal to change in real time is instantaneously switched ON / OFF, so that noise such as undershoot does not occur. As in the graphic DRAM 250 in the video block 210 of FIG.
In the case of AM, it is necessary to pay sufficient attention to change the voltage such as + 5V to + 3V. This is because the DRAM stores data based on whether or not the charge of the MOSFET is charged with electric charge, and the DRAM must be periodically refreshed. Therefore, as shown in FIG. 8, a refresh signal is input for each constant voltage during the voltage change period. Conversely, a refresh signal (usually about 16 us) generated once during a period determined for each constant voltage
Occurs once. ), That is, a voltage change time that is sufficiently longer than the refresh signal (at least 5 times).
(About 0 us or more). Thus, the voltage can be changed also in the DRAM.

Further, the timing of voltage switching and frequency switching will be described with reference to FIG. The switching of the clock signal can be performed in the order of ns, but the switching of the voltage takes about 5 ms to 20 ms. Therefore, even if the switching of the voltage is performed too frequently as in the case of the switching of the frequency of the clock, there is a possibility that the voltage fluctuation is increased and the effect is rather reversed. Therefore, the time for switching the frequency (ms to several s) and the time for switching the voltage are changed,
The time for switching the voltage is set to several seconds to several tens of seconds. Specifically, in order to reduce the voltage from 5 V to 3 V, the voltage switching signal is lowered to a low level after a few seconds or more after the frequency switching signal becomes a low level. Further, in order to increase the voltage from 3V to 5V, the voltage is increased after the frequency switching signal becomes high level, and the actual frequency is not increased until the voltage is completely increased. However, when increasing the voltage in this way, even if high-speed processing is required immediately, it is necessary to wait until the voltage is completely increased. This time can cause performance degradation. Therefore, a voltage monitoring IC is provided as shown in FIG.
When the voltage becomes 4.5 V at which high-speed operation is possible, a frequency high-speed permission signal 372 which becomes a high level is output.
The frequency fast enable signal 372 allows the system to quickly become faster and minimize performance degradation. By switching in this way, it is possible to always have the highest performance and the lowest power consumption during various application operations.

Further, the clock frequency at the low speed in the power save mode as the first mode uses a clock frequency corresponding to the lowest performance of the conventional model, and maintains compatibility with existing programs. If the frequency is further reduced, a malfunction may occur depending on an existing program. With these considerations,
The CPU 20 can be operated with the minimum clock that does not impair compatibility, and the current consumption of the information processing device can be reduced. And when switching the frequency from low to high, instead of switching to the highest frequency,
The CPU controller 81 functions to return to the clock frequency specified in advance. By this switching, compatibility of the existing program at a high frequency can be maintained. In addition, the L for display is displayed in a different color for each frequency so that the user can grasp at what frequency the CPU 20 is currently operating.
ED (diode) is lit. For example, 16MH
Is green at 10 MHz, orange at 5 MH, and red at 5 MH. In addition, if the user
When z is set, the low voltage operation is automatically performed. FIG. 10 shows a schematic diagram of such a display LED. The LED 402 for displaying the clock frequency is laid out second from the left. When the LED 402 is turned off, it is in a power-off state or in a power save mode and operating at a low speed. When the power is off, all other LEDs 401, 403 to 4
Since 08 is also turned off, the user can grasp the power save mode by displaying the LED 402. That is, the user operates the information processing apparatus in the power save mode when, for example, the rightmost LED 408 indicating the remaining battery level is on and the LED 402 indicating the clock frequency is off. You can see that.

The information processing apparatus of the present embodiment normally operates at a low speed clock and low voltage and operates at a high speed clock and high voltage for a certain period according to a specific factor. A normal mode (second mode) operating with a clock and a high voltage can be selected. These modes are set in advance in the system environment table so that they are automatically initialized when the information processing apparatus is powered on. In addition, even when the information processing apparatus is operating, it can be changed by a desired combination of keys of the keyboard device.
That is, during operation in the power save mode, for example, “C
By pressing the "TRL" key / "GRPH" key / "P" key, the mode is changed to the normal mode. Conversely, during the operation in the normal mode, the same key operation can be performed to change to the power save mode. As described above, since such a mode change is performed during the refresh period, no error occurs even when the mode is changed during the execution of the application program.

Next, the power save mode will be described in detail. The power save mode is different from the conventional power management in that the CPU clock is switched in a short time (in units of seconds) and the voltage is switched.
This is a method for reducing power consumption. In the power save mode, the device normally operates at a low clock frequency and low voltage, and switches to a high clock frequency and high voltage only when a specific factor such as a key input occurs. This is because word processing software or the like needs to operate at a high clock frequency only at the time of conversion and key input, and a low clock frequency is sufficient for the time when text is considered. In the power save mode, power consumption is reduced by providing a minimum clock frequency and a low voltage at which an application program or the like can operate without any problem. Certain factors that change the clock frequency and voltage include I / O
There are O access, interrupt, and the like. First, the I / O access will be described. A typical application program used by a user is analyzed to extract an I / O access requiring an operation at a high clock frequency. Then, only when the extracted I / O access occurs, the clock frequency is increased for a certain period. Next, the interrupt will be described. Since only a specific interrupt cycle such as a keyboard device, an RS-232C, a hard disk device, etc., the information processing device is operated at a high clock frequency for a certain period of time even after a return (EOI) command is returned. is there.

[0018]

According to the information processing apparatus of the present invention, normal processing that does not require high-speed operation is executed under a low-speed clock and a low voltage, thereby reducing power consumption. The specific processing requiring high-speed operation is executed at high speed for a certain period by switching to a high-speed clock and a high voltage. As described above, since the clock and the voltage are switched according to the processing content, reduction in power consumption can be realized without reducing the speed of the processing requiring high-speed operation.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a CPU block.

FIG. 3 is a circuit configuration diagram of an input / output block.

FIG. 4 is a circuit configuration diagram of a video block.

FIG. 5 is a circuit diagram of a voltage switching circuit.

FIG. 6 is a waveform chart showing voltage fluctuation.

FIG. 7 is a waveform chart showing voltage fluctuation.

FIG. 8 is a waveform chart showing voltage fluctuation.

FIG. 9 is a circuit diagram of a monitoring IC.

FIG. 10 is a schematic diagram showing LEDs for display.

[Explanation of symbols]

 10 CPU Block 110 Input / Output Block 170 External Equipment 210 Video Block 290 Liquid Crystal Display 310 Power Supply

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 1/32 G06F 1/04

Claims (2)

(57) [Claims] 1. A low-speed mode that operates with a low-frequency clock and a low voltage, and a high-speed mode that operates with a high-frequency clock and a high voltage, wherein a specific factor consisting of an I / O access signal or an interrupt signal is used. A switching unit for switching between the low-speed mode and the high-speed mode for a predetermined period when the error occurs, the switching between the modes is performed automatically without using software; When switching from the high-speed mode to the low-speed mode, after switching the clock from the high frequency to the low frequency by the frequency switching signal, and after a lapse of a predetermined time, switching the voltage from the high voltage to the low voltage by the voltage switching signal. An information processing apparatus characterized by the above-mentioned. 2. A low-speed mode that operates with a low-frequency clock and a low voltage, and a high-speed mode that operates with a high-frequency clock and a high voltage, wherein a specific factor consisting of an I / O access signal or an interrupt signal is used. A switching means for switching between the low-speed mode and the high-speed mode for a predetermined period when a signal is generated; a device which needs to input a refresh signal in a predetermined cycle; and a voltage between the low voltage and the high voltage. And a malfunction prevention means for transmitting a refresh signal to the device at every constant voltage during the voltage change period switched in the above, wherein the switching of each mode is performed automatically without using software. Characteristic information processing device.