JP3057698B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a semiconductor device such as a CMOS.

<Prior Art> Conventionally, a CM formed on a generally known N-type substrate
As a semiconductor device including an OS semiconductor device (hereinafter, simply referred to as CMOS), for example, there is a semiconductor device as shown in FIG.

In FIG. 5, reference numeral 41 denotes an N-type substrate. On the main surface of the N-type substrate 41, a P ^{+ type} diffusion layer 42, an N ^{+ type} diffusion layer 43, and three P wells 44, 45, 111 are formed. .

One end of the P ^{+ type} diffusion layer 42 is connected to the input terminal 54, and the other end is connected to the wiring 58. The N ^{+ type} diffusion layer 43 is connected to the power supply voltage V _DD
It is connected to the.

An N ^{+ type} diffusion layer 47 is formed on the main surface of
Connected to 58. A part at one end of the P-well 44 is the P ⁺ diffusion layer 46 in contact with the N-type substrate 41 is formed, is connected to the low-level voltage V _SS.

An N ^{+ type} diffusion layer 48 is formed on the main surface of the P well 45, and a polycrystalline silicon layer 51 is formed on the N ^{+ type} diffusion layer 48 via an insulating film 49.
Is formed. The polycrystalline silicon layer 51 is the wiring 58, N ⁺ form diffusion layer 48 are connected to the low-level voltage V _SS.

On the main surface of the P well 111, N ^{+ -type} diffusion layers 112 and 113 as N-MOS source and drain are formed, and further, a P ^{+ -type} diffusion layer 119 is formed. N ^{+ type} diffusion layer 112 and P ^{+ type} diffusion layer
119 is connected to the low potential voltage V _SS . Also, P well 111
At the position sandwiched between the N ^{+ type} diffusion layers 112 and 113 on the main surface of
Polycrystalline silicon layer as gate electrode via insulating film 49
116 is formed. Furthermore, a P-MOS is provided on the main surface of the N-type substrate 41.
P ^{+ -type} diffusion layers 114 and 115 are formed as drains and sources, and an N ^{+ -type} diffusion layer 120 is further formed. N ^{+ type} diffusion layer 1
20 and P ^{+ type} diffusion layer 115 are connected to power supply voltage V _DD . In addition, a polycrystalline silicon layer 117 as a gate electrode is formed on the main surface of N-type substrate 41 at a position between P ^{+ -type} diffusion layers 114 and 114 via insulating film 49. N ^{+ type} diffusion layer 113 and
P ^{+ type} diffusion layer 114 is connected to output terminal 118. The polycrystalline silicon layers 116 and 117 are connected to the wiring 58. 52 is a silicon oxide film as an element isolation region.

FIG. 6 shows an equivalent circuit of the semiconductor device having the above structure. A resistance 53 is formed by the internal resistance of the P ^{+ type} diffusion layer 42, and its resistance value is set to several hundred kΩ. The first diode is formed by the PN junction between the P ^{+ type} diffusion layer 42 and the N type substrate 41.
A second diode 56 is formed by a PN junction between the P well 44 and the N ^{+ type} diffusion layer 47. Further, a capacitor 57 is constituted by a MOS capacitor including an N ^{+ type} diffusion layer 48 as a lower electrode, an insulating film 49 and a polycrystalline silicon layer 51 as an upper electrode. In addition, a filter circuit is configured by the capacitor 57 and the resistor 53.

The gate electrodes of the P-MOS and the N-MOS forming the CMOS are connected in an array to the wiring 58, and the P-MOS and the N-M forming the CMOS are connected.
The connection point between the drains of the OS is connected to the output terminal 118.

Then, during normal operation, a signal input from the input terminal 54 is transmitted to the polysilicon layers 116 and 117 which are the gate electrodes of the CMOS via the resistor 53. At this time, the first and second diodes 55 and 56 are both reverse biased and are in a non-conductive state.

Next, when noise or the like having a voltage higher than the power supply voltage V _DD is input from the input terminal 54, the first diode 55 is forward-biased, and the noise passes through the N-type substrate 41 and is supplied to the power supply voltage V _DD.
Bypassed to _DD .

When noise of a voltage lower than the low potential voltage V _SS is input, the second diode 56 is forward-biased, and the noise is bypassed to the low potential voltage V _SS through the P well 44.

Furthermore, when high-frequency noise is superimposed on the signal input from the input terminal 54 and input, the resistor 53 and the capacitor
The filter circuit composed of the filter 57 eliminates noise having a cycle shorter than a time constant determined by the product of the resistance value and the capacitance, thereby preventing malfunction of the CMOS.

<Problems to be solved by the invention> However, the above-described conventional example has the following problems.

That is, when noise or the like having a voltage higher than the power supply voltage V _DD is input from the input terminal 54, the P ^{+ type} diffusion layer 42 and the N type substrate 41
The first diode 55 formed by the PN junction with the first transistor 55 is forward-biased.

At this time, a large amount of holes are injected from the P ^{+ type} diffusion layer 42 toward the N type substrate 41. Some of the injected holes diffuse in the N-type substrate 41 to form another P-well (here,
(P well of N-MOS constituting CMOS).

As shown in FIG. 7, a CMOS formed on an N-type substrate 41
, A parasitic transistor is formed. That is, P ⁺
Emitter form diffusion layer 115, based on N-type substrate 41, the collector of PNP transistor Q ₁ and N-type substrate 41 and the collector of the P-well 111, based on P-well 111, N ⁺ form diffusion layers 1
12 is an NPN type transistor Q ₂ to the emitter. FIG. 8 shows an equivalent circuit of the connection relationship between the parasitic transistors Q ₁ and Q ₂ . R ₁ is distributed resistance of the N-type substrate 41, R ₂ is a distributed resistance of the substrate and P-well 111.

Here, as shown in FIG. 9, when some of the holes diffused in the N-type substrate 41 reach the vicinity of the P well 111, the holes are injected into the P well 111. This is because the potential of the P-well 111 is lower than the potential of the N-type substrate 41, so that the depletion layer near the junction surface between the N-type substrate 41 and the P-well 111 has a direction from the N-type substrate 41 toward the P-well 111. This is because a built-in electric field is generated. This hole is P well 11
Reaches the medium 1 in the through connexion P-type diffusion layer 119 flows to the low-level voltage V _SS.

In this process, due to the internal resistance with the P-well 111, the potential of the hole of the path is higher than farther low-level voltage V _SS from the P ⁺ diffusion layer 119. At this time, the N ^{+ type} diffusion layer 1
When the potential rise near 12 (shaded area in the figure) becomes about 0.6 to 0.65 V, the junction between the P well 111 and the N ^{+ type} diffusion layer 112 becomes forward biased. Thus, Figure 8 or the base of the parasitic transistor Q ₂ in FIG. 9 - a current flows between the emitter, the parasitic transistor Q ₂ is turned ON. for that reason,
Parasitic transistor Q ₂ of the emitter of the parasitic transistor Q ₁ by the collector current - between the base is forward biased, the parasitic transistor Q ₁ is turned ON. As a result, a conduction state is established between the power supply voltage V _DD and the low potential voltage V _SS , and a very large current flows. This excessive current continues to flow unless the power is turned off. This is a so-called "ratch-up phenomenon", in which the CMOS is destroyed due to an excessive current flowing through the latch.

In order to prevent the occurrence of the latch-up phenomenon, it is necessary to prevent holes diffusing in the substrate from reaching other P-wells and to make the operation of the parasitic bipolar transistor and the like difficult to perform. It is necessary to take measures such as forming the CMOS and the P ^{+ -type} diffusion layer 42 at a sufficiently distant position on the N-type substrate 41 in FIG. 5, thereby increasing the chip area and hindering the high integration. There was a problem of becoming.

<Means for Solving the Problems> The present invention has been made in view of the above problems, and has an input terminal, a semiconductor substrate of a first conductivity type, an internal circuit formed on a main surface of the semiconductor substrate, and A second conductivity type well region formed on the surface of the semiconductor substrate; a first conductivity type diffusion region formed on the surface of the well region and having a higher impurity concentration than the semiconductor substrate; A second conductivity type semiconductor having an impurity concentration higher than that of the semiconductor substrate, the semiconductor substrate having one end connected to the input terminal and the other end connected to the internal circuit; Wherein the semiconductor substrate, the well region, and the diffusion region have the same potential.

<Operation> During normal control, a signal input from an input terminal is input to an internal circuit via a semiconductor region to operate the internal circuit. At this time, it is composed of a diffusion region and a semiconductor region.
The PN junction is reverse biased, and a depletion layer spreads on the PN junction surface. In the present application, since the semiconductor region and the diffusion region are configured to be in contact with each other on one side, the depletion layer is also formed on one side, and the thickness of the depletion layer is constant over the entire area. Even when the voltage fluctuates and an electric field higher than the withstand voltage is applied, the electric field does not concentrate on a part of the depletion layer and the circuit is not broken. In addition, when a positive high voltage is applied to the input terminal, the present application makes the above PN junction forward bias,
That is, it becomes a diode, and in addition to the transistor composed of the semiconductor region, the diffusion region, and the well region, this path also absorbs carriers generated by high voltage. At this time, in the present application, since the diffusion region has a higher concentration than the substrate, the resistance of the diffusion region is low. Therefore, even when a high voltage is input from the input terminal, the voltage drop at the input terminal side and the other end side is small, so that the carrier can be pulled out from the other end side very efficiently, and the circuit is destroyed. Absent.

Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1 to 4. FIG. 1 shows a semiconductor device of this embodiment. In the figure, reference numeral 41 denotes an N-type substrate.
Two P-wells 102, 44, 45 and 111 are formed. P-well
A P ^{+ -type} diffusion layer 103 and an N ^{+ -type} diffusion layer 101 whose one end is in contact with the N-type substrate 41 are formed on the main surface of 102, and both are connected to the power supply voltage _VDD . On the main surface of the N ^{+ type} diffusion layer 101, a P ^{+ type} polycrystalline silicon layer 100 is formed by CVD, one end of the P ^{+ type} polycrystalline silicon layer 100 is connected to the input terminal 54, and the other end is connected to the wiring 58. ing.

An N ^{+ type} diffusion layer 47 is formed on the main surface of
Connected to 58. At one end of the P well 44, a P ^{+ type} diffusion layer 46 is formed so that a part thereof is in contact with the N type substrate 41,
Connected to low potential voltage V _SS .

An N ^{+ type} diffusion layer 48 is formed on the main surface of the P well 45, and a polycrystalline silicon layer 51 is formed on the N ^{+ type} diffusion layer 48 via an insulating film 49.
Is formed. The polycrystalline silicon layer 51 is the wiring 58, N ⁺ form diffusion layer 48 are connected to the low-level voltage V _SS.

On the main surface of the P well 111, N ^{+ -type} diffusion layers 112 and 113 as N-MOS source and drain are formed, and further, a P ^{+ -type} diffusion layer 119 is formed. N ^{+ type} diffusion layer 112 and P ^{+ type} diffusion layer
119 is connected to the low potential voltage V _SS . Also, P well 111
At the position sandwiched between the N ^{+ type} diffusion layers 112 and 113 on the main surface of
Polycrystalline silicon layer as gate electrode via insulating film 49
116 is formed. Furthermore, a P-MOS is provided on the main surface of the N-type substrate 41.
P ^{+ -type} diffusion layers 114 and 115 are formed as drains and sources, and an N ^{+ -type} diffusion layer 120 is further formed. N ^{+ type} diffusion layer 1
20 and P ^{+ type} diffusion layer 115 are connected to power supply voltage V _DD . Further, a polycrystalline silicon layer 117 as a gate electrode is formed on the main surface of N-type substrate 41 at a position between P ^{+ -type} diffusion layers 114 and 115 via insulating film 49. N ^{+ type} diffusion layer 113 and
P ^{+ type} diffusion layer 114 is connected to output terminal 118. The polycrystalline silicon layers 116 and 117 are connected to the wiring 58. 52 is a silicon oxide film as an element isolation region.

FIG. 2 shows an equivalent circuit of the semiconductor device having the above structure. A resistor 61 is formed by the internal resistance of the P ^{+ -type} polycrystalline silicon layer 100, and its resistance value is set to several hundred kΩ.

P ^{+ type} polycrystalline silicon layer 100 is used as an emitter, and N ^{+ type} diffusion layer 101 is used.
A PNP transistor 60 having a base-collector short circuit is constructed using the P-well 102 as a base and the P-well 102 as a collector. A diode 56 is formed by a PN junction between the P well 44 and the N ^{+ type} diffusion layer 47. A capacitor 57 is formed by a MOS capacitor including an N ^{+ -type} diffusion layer 48 as a lower electrode, an insulating film 49, and a polycrystalline silicon layer 51 as an upper electrode. Further, a filter circuit is configured by the capacitor 57 and the resistor 61.

The gate electrodes of the P-MOS and the N-MOS constituting the CMOS are connected in parallel to a wiring 58, and the P-MOS and the N-M constituting the CMOS are connected.
The connection point between the drains of the OS is connected to the output terminal 118.

The power supply voltage V is applied from the input terminal 54 to the semiconductor device having the above configuration.
FIG. 3 shows a case where noise of a voltage higher than _DD is input. At this time, the PN junction formed by the P ^{+ -type} polycrystalline silicon layer 100 and the N ^{+ -type} diffusion layer 101 becomes a forward bias. Therefore, holes are injected from the P ^{+ -type} polycrystalline silicon layer 100 into the N ^{+ -type} diffusion layer 101. The injected holes form the N ^{+ type} diffusion layer 10
Most of them disappear due to recombination with electrons in 1, and a part is injected into the P-well 102 by a built-in electric field generated in a depletion layer at the junction surface.

The holes injected into the P well 102 reach the P ^{+ type} diffusion layer 103 by propagation and are bypassed to the power supply voltage _VDD . Some of the holes reach the vicinity of the junction between the P-well 102 and the N-type substrate 41, but are pushed back from the N-type substrate 41 to the P-well 102 due to the built-in electric field generated in the depletion layer. It is.

As described above, the holes are bypassed to the power supply voltage _VDD via the N ^{+ type} diffusion layer 101 and the P well 102.

Further, according to the configuration of the present embodiment, the P ^{+ type} polycrystalline silicon layer
By the 100, N ^{+ type} diffusion layer 101 and the P well 102, the base-collector short-circuited bipolar transistor 60 is formed in a parasitic manner. Generally, such a transistor has better rising characteristics and better switching characteristics than the diode 55 (which can be regarded as an open collector transistor) as shown in the conventional example. For this reason, in the bipolar transistor 60 of the configuration of the present embodiment, the rate at which high-voltage noise or the like applied from the input terminal 54 is bypassed to the power supply voltage V _DD is higher than that of the diode 55 of the conventional configuration. .

By the way, in this embodiment, the P ^{+ type} polycrystalline silicon layer 100, N ⁺
Although a parasitic thyristor is formed by the N-type diffusion layer 101, the P-well 102 and the N-type substrate 41, since the N ^{+ type} diffusion layer 101, the P-well 102 and the N-type substrate 41 are connected to the same potential, the thyristor is There is no rattling.

A method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIG.

As shown in FIG. 4 (a), the N-type substrate 41 has a CVD
To form a SiN (silicon nitride) film, and selectively perform etching. P-wells 102, 44, 45, and 111 are formed by ion-implanting and thermally diffusing the etched portions. Thereafter, the SiN (silicon nitride) film on the main surface of the N-type substrate 41 is removed by etching.

As shown in FIG. 4 (b), the N-type substrate 41 has a CVD
To form a SiN (silicon nitride) film, and selectively perform etching. An etched portion of the N-type substrate 41 is thermally oxidized to form an oxide film 52. Thereafter, the SiN (silicon nitride) film on the main surface of the N-type substrate 41 is removed by etching.

As shown in FIG. 4C, heat is further applied to the N-type substrate 41 to form a thin oxide film (insulating film 49) on the main surface.
Next, after depositing a polycrystalline silicon layer on the main surface of the insulating film 49 by CVD, ion implantation of POCl ₃ (phosphorus oxychloride) is performed. The polycrystalline silicon layer is selectively etched to form polycrystalline silicon layers 116 and 177.

As shown in FIG. 4 (d), after masking except for predetermined positions of the main surfaces of the P-wells 44, 45, 111 and the main surface of the N-type substrate 41, ion implantation of As (arsenic) as an N-type impurity is performed. (Shown by ○ in the figure).

As shown in FIG. 4 (e), after performing masking except for a predetermined position, P-type impurities B (boron) are formed on the main surfaces of the P-wells 102 and 111, one end of the P-well 44, and the main surface of the N-type substrate 41.
(Indicated by x in the figure). Next, after depositing a polycrystalline silicon layer on the main surface of the insulating film 49 by CVD, the POCl
₃ Perform ion implantation of (phosphorus oxychloride). The polycrystalline silicon layer is selectively etched to form a polycrystalline silicon layer 51.

As shown in FIG. 4 (f), after masking is performed on the main surface of the P-well 102 except for a portion where one end is in contact with the N-type substrate 1, As (arsenic) as an N-type impurity is ion-implanted (FIG. (Shown in the middle).

As shown in FIG. 4 (g), after removing the oxide film 49 on the main surface of the P well 102 into which As (arsenic) has been ion-implanted, a polycrystalline silicon layer is deposited by CVD. Next, ions of B (boron) as a P-type impurity are implanted into the polycrystalline silicon layer. The polysilicon layer is selectively etched to form a P ⁺ -type polysilicon layer 100.

As shown in FIG. 4 (h), heat is applied at 900 to 1,000 ° C. for 10 to 20 minutes to diffuse the implanted ions, and the N ^{+ type} diffusion layer 10 is formed.
1,47,48,112,113,120 and P ^{+ type} diffusion layers 103,46,119,114,
Form 115.

Finally, as shown in FIG. 4 (i), wiring is performed by aluminum printing as follows. P ^{+ type} polycrystalline silicon layer 10
0 is connected to the input line 54, and the other end of the polycrystalline silicon layer 100, the N ^{+ type} diffusion layer 47, the polycrystalline silicon layer 51, and the polycrystalline silicon layers 116 and 117 which are CMOS gate electrodes are connected to the wiring 58. . Connect the P ⁺ diffusion layer 103 and 115 and the N ⁺ form diffusion layers 101,120 to the power supply voltage V _DD, connecting the P ⁺ diffusion layer 46,119 and the N ⁺ form diffusion layers 48,112 to low-level voltage V _SS. Then, P ^{+ type} diffusion layer 114 and N ^{+ type} diffusion layer 113 are connected to output terminal 118.

The process of forming the N ^{+ -type} diffusion layer is divided into the two processes of (d) and (f) because the impurity concentration and type of the N ^{+ -type} diffusion layer 101 are different from those of the other N ^{+ -type} diffusion layers. This is to increase the degree of freedom of the operation performance of the bipolar transistor 60 including the N ^{+ -type} diffusion layer 101 as one of the constituent elements. Therefore, when the type and concentration of impurities of the N ^{+ -type} diffusion layer 101 are made the same as those of the other N ^{+ -type} diffusion layers, the steps (d) and (f) can be integrated.

Incidentally, the illustration of the insulating film 49 is shown in FIGS.
7 and 9, the oxide film 52 is not shown in FIG.
It is omitted in FIG. 9 and FIG.

As described above, in the present embodiment, CMOS as an internal circuit is formed on the main surface of the N-type substrate 41, and P-type CMOS is formed on the main surface of the N-type substrate 41.
A well 102 is formed, and an N ^{+ type} diffusion layer 101 is formed on the main surface of the P well 102.
And one end is connected to the input terminal 54 on the main surface of the N ^{+ type} diffusion layer 101.
To form a P ^{+ -type} polycrystalline silicon layer 100 having the other end connected to the polycrystalline silicon layers 116 and 117 which are the CMOS gate terminals. The potential of the N ^{+ -type} diffusion layer 101 and the potential of the P well 102 are changed to the N-type. The configuration was made to be equal to the potential of the substrate 41. Therefore, holes are effectively prevented from reaching the P-well 111 of the CMOS, and a parasitic transistor or a parasitic thyristor is not rushed, thereby preventing malfunction of the CMOS. As a result, CMOS and P ^{+ type} polycrystalline silicon layer 100, N ^{+ type} diffusion layer 101, P
The interval between the wells 102 can be shortened, and the chip area can be reduced.

In this embodiment, the P well 102 and the N ^{+ type} diffusion layer 1
01 is formed by thermal diffusion, and a P ^{+ type} polycrystalline silicon layer 100 is formed.
Was formed by CVD, but the present invention is not limited to this. That is, a P-type impurity region, an N-type impurity region, and a P ^{+ -type} polycrystalline silicon layer 100 may be sequentially deposited on the N-type substrate 41 main surface, or the P-well 102 is thermally diffused on the N-type substrate 41 main surface. And an N-type impurity region, P-type
To ⁺ may be sequentially deposited in the form polycrystalline silicon layer 100, also the P-well 102, N ⁺ form diffusion layer 101 by connexion formed thermally diffused N-type substrate 41 major surface, N ⁺ form diffusion layer 101 A P-type impurity region may be formed on the main surface by thermal diffusion.

The conductivity type of the semiconductor is not limited to that of the present embodiment. The N-type substrate 41 is a P-type, the P-well 102 is an N-type, the N ^{+ -type} diffusion layer 101 is a P-type, and a P ^{+ -type} polycrystalline silicon layer. 100 may be N-type, and the N-well and P ^{+ -type} diffusion layer may be connected to the low potential voltage V _SS together with the P-type substrate. In this case, noise or the like having a voltage lower than the low potential voltage V _SS input from the input terminal 54 is removed.

Further, in this embodiment, CMOS is applied as the internal circuit, but a logic circuit or the like using other elements may be used. Also wiring
Although 58 is connected to the CMOS gate electrode, the wiring 58 may be connected to any input terminal of the internal circuit.

<Effects of the Invention> The present invention provides an input terminal, a first conductivity type semiconductor substrate,
An internal circuit formed on the main surface of the semiconductor substrate, a well region of the second conductivity type formed on the surface of the semiconductor substrate, and an impurity concentration higher than that of the semiconductor substrate formed on the surface of the well region. A diffusion region of a first conductivity type, formed on the diffusion region so as to be in contact with the entire surface, and having one end connected to the input terminal and the other end connected to the internal circuit; A semiconductor region of the second conductivity type having a high impurity concentration, and the semiconductor substrate, the well region, and the diffusion region are set to the same potential. Is input to the internal circuit via the semiconductor region to operate the internal circuit. At this time, the PN junction formed by the diffusion region and the semiconductor region has a reverse bias, and the depletion layer spreads on the PN junction surface. In the present application, since the semiconductor region and the diffusion region are configured to be in contact with each other on one side, the depletion layer is also formed on one side, and the thickness of the depletion layer is constant over the entire area. Fluctuates, even when an electric field higher than the breakdown voltage is applied, the electric field does not concentrate on a part of the depletion layer,
Does not destroy the circuit. In addition, when a positive high voltage is applied to the input terminal, the present application provides that the PN junction becomes a forward bias, that is, a diode, in addition to a transistor including a semiconductor region, a diffusion region, and a well region.
This path also absorbs carriers generated by the high voltage. At this time, in the present application, since the diffusion region has a higher concentration than the substrate, the resistance of the diffusion region is low. Therefore, even when a high voltage is input from the input terminal, the voltage drop at the input terminal side and the other end side is small, so that the carrier can be pulled out from the other end side very efficiently, and the circuit is destroyed. No effect.

[Brief description of the drawings]

FIG. 1 is a sectional view showing the structure of a semiconductor device, and FIG.
FIG. 3 is an equivalent circuit diagram of the semiconductor device shown in FIG. 1, FIG. 3 is an operation explanatory diagram showing the movement of holes when high-voltage noise or the like is applied from the input terminal 54, and FIG. FIG. 5 is a sectional view showing a manufacturing process of the semiconductor device shown in FIG. 5, FIG. 5 is a sectional view showing a conventional semiconductor device, FIG. 6 is an equivalent circuit diagram of the semiconductor device shown in FIG. Is a diagram showing a parasitic transistor formed in CMOS, FIG. 8 is an equivalent circuit diagram showing connection of the parasitic transistor, and FIG. 9 is a schematic diagram showing a potential change of a P well. 41: N-type substrate, 100: P ^{+ type} polycrystalline silicon, 101:
N ^{+ type} diffusion layer, 102 ... P well

Claims (1)

(57) [Claims] An input terminal; a first conductivity type semiconductor substrate; an internal circuit formed on a main surface of the semiconductor substrate; a second conductivity type well region formed on the semiconductor substrate surface; A first conductivity type diffusion region formed on the surface of the region and having an impurity concentration higher than that of the semiconductor substrate;
A second conductivity type semiconductor region having one end connected to the input terminal and the other end connected to the internal circuit, the semiconductor region being of a second conductivity type having a higher impurity concentration than the semiconductor substrate. A semiconductor device, wherein the well region and the diffusion region have the same potential.