JP3049108B2 - Switching type DC stabilized power supply - Google Patents
Switching type DC stabilized power supplyInfo
- Publication number
- JP3049108B2 JP3049108B2 JP3094658A JP9465891A JP3049108B2 JP 3049108 B2 JP3049108 B2 JP 3049108B2 JP 3094658 A JP3094658 A JP 3094658A JP 9465891 A JP9465891 A JP 9465891A JP 3049108 B2 JP3049108 B2 JP 3049108B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- power supply
- voltage
- resistor
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Control Of Voltage And Current In General (AREA)
- Control Of Electrical Variables (AREA)
- Dc-Dc Converters (AREA)
- Emergency Protection Circuit Devices (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明はスイッチング式直流安定
化電源に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching type stabilized DC power supply.
【0002】[0002]
【従来の技術】図1及び図2はこの種の従来回路図及び
その各部動作波形図で、図1において、Vinは交流入
力(電圧)、D1は整流用ブリッジでこれにより直流電
源Eを形成する。R1及びSCRは並列接続されてなる
抵抗及びサイリスタで、前記直流電源Eと入力用コンデ
ンサC1間に接続され、前記コンデンサC1の突入電流
を防止する。次にT1は出力トランスで、その1次巻線
n1はスイッチ素子(トランジスタ)Q1と直列接続さ
れてコンデンサC1の両端(直流出力端子)に接続され
る。nsはトランスT1の補助巻線で、一端を前記1次
巻線n1の一端子に接続され、他端をダイオードD2,
コンデンサC2及び抵抗R2を介して前記サイリスタS
CR1のゲートに接続されて、該サイリスタSCR1の
ゲート回路を形成している。n2は2次(出力)巻線、
D3、D4は出力整流用ダイオード、L1,C3は出力
平滑回路を形成するチョークコイル及びコンデンサ、A
は前記トランジスタQ1のスイッチング制御回路で出力
電圧E0に応じてパルス幅制御されたパルス信号を該ト
ランジスタQ1に印加する。2. Description of the Related Art FIGS. 1 and 2 are a conventional circuit diagram of this kind and operation waveform diagrams of respective parts. In FIG. 1, Vin is an AC input (voltage) and D1 is a rectifying bridge, thereby forming a DC power source E. I do. R1 and SCR are resistors and thyristors connected in parallel, and are connected between the DC power supply E and the input capacitor C1 to prevent an inrush current of the capacitor C1. Next, T1 is an output transformer, the primary winding n1 of which is connected in series with the switch element (transistor) Q1 and connected to both ends (DC output terminals) of the capacitor C1. ns is an auxiliary winding of the transformer T1, one end of which is connected to one terminal of the primary winding n1 and the other end of which is a diode D2.
The thyristor S is connected via a capacitor C2 and a resistor R2.
The thyristor SCR1 is connected to the gate of CR1 to form a gate circuit of the thyristor SCR1. n2 is a secondary (output) winding;
D3 and D4 are output rectifying diodes; L1 and C3 are choke coils and capacitors forming an output smoothing circuit;
Applies a pulse signal whose pulse width is controlled by the switching control circuit of the transistor Q1 according to the output voltage E0 to the transistor Q1.
【0003】この回路の動作は交流入力Vin(図2−
a)が投入されると、整流用ダイオードD1を通して直
流電圧Eが発生し、コンデンサC1は抵抗R1により突
入電流を防止され、該抵抗R1により制限されながら充
電され、図2−bに示す如くその充電電圧が上昇する。
そして充電々圧が所定値に達すると、制御回路Aを介し
てトランジスタQ1がスイッチング動作を開始する。同
時に補助巻線nsに発生する電圧によりダイオードD
2、抵抗R2を介してサイリスタSCR1にゲート信号
が送られ、これを導通(ON)せしめるため、該抵抗R
1両端は該サイリスタSCR1により短絡状態になる。
又2次巻線n2側では整流ダイオードD3、D4、平滑
回路L1、C3を通して直流を給電する。なお、制御回
路Aは出力電圧E0に応じてパルス信号をトランジスタ
Q1に与えるため整流用ダイオード及び平滑回路を介し
て安定化直流E0を供給する。The operation of this circuit is based on an AC input Vin (FIG. 2).
When a) is applied, a DC voltage E is generated through the rectifying diode D1, and the inrush current is prevented by the resistor R1, and the capacitor C1 is charged while being limited by the resistor R1, as shown in FIG. The charging voltage increases.
When the charged pressure reaches a predetermined value, the transistor Q1 starts the switching operation via the control circuit A. At the same time, the voltage of the auxiliary winding ns causes the diode D
2. A gate signal is sent to the thyristor SCR1 via the resistor R2, and this is turned on (ON).
One end is short-circuited by the thyristor SCR1.
On the secondary winding n2 side, DC is supplied through rectifier diodes D3 and D4 and smoothing circuits L1 and C3. The control circuit A supplies a stabilized DC E0 via a rectifying diode and a smoothing circuit to supply a pulse signal to the transistor Q1 according to the output voltage E0.
【0004】[0004]
【従来技術の問題点】上記の従来回路においては図2に
示す時間t2において交流入力Vinにが瞬断が生じる
とコンデンサC1は放電を開始する。そしてその電圧が
スイッチングレギュレータのもつ動作可能限界である電
圧まで低下し、時間t3で復電すると、上記状態では補
助巻線nsを通してサイリスタSCR1はゲート信号が
与えられて導通常状態にあるため、該復電によりコンデ
ンサC1は図2−Cに示す如く過大な電流が流れるため
に該コンデンサC1の劣化を来たし、寿命を短くする等
の問題がある。更に出力トランスT1に補助巻線nsを
設けてサイリスタのゲート信号を給電するため、トラン
スT1の大型化を招く等の欠点がある。In the above-mentioned conventional circuit, when a momentary interruption occurs in the AC input Vin at time t2 shown in FIG. 2, the capacitor C1 starts discharging. Then, when the voltage drops to a voltage that is the operable limit of the switching regulator and is restored at time t3, in the above state, the thyristor SCR1 receives a gate signal through the auxiliary winding ns and is in a normal conduction state. As shown in FIG. 2C, an excessive current flows through the capacitor C1 due to the restoration of power, so that the capacitor C1 is deteriorated, and there are problems such as shortening the life. Further, since the auxiliary winding ns is provided in the output transformer T1 to supply the gate signal of the thyristor, there is a disadvantage that the size of the transformer T1 is increased.
【0005】[0005]
【本発明の目的】本発明は入力瞬断時の突入電流の防止
を図ると共にゲート回路を簡略化した突入防止回路を備
えた安定化直流電源の提供を目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to provide a stabilized DC power supply provided with an inrush prevention circuit for preventing an inrush current at the moment of an instantaneous input interruption and simplifying a gate circuit.
【0006】[0006]
【実施例】図3、図4は本発明の一実施例回路図及びそ
の各部動作波形図で従来例と同一符号は同等部分を示
す。本発明の主要構成部は突入電流防止回路Bにおい
て、直流電源(E1)とコンデンサ(C1)の間に電圧
駆動素子(FET)と抵抗(R1)の並列回路を設ける
と共に前記電圧駆動素子(FET)のゲート回路を設
け、又、前記並列回路に流れる電流による電圧降下を検
出して前記ゲート回路を開放するバイパス回路を設け
て、前記電圧駆動素子をオフせしめるようにしたことを
特徴とする。因みにゲート回路は、直流電源間に接続さ
れた抵抗R3及び定電圧ダイオードDZ1の接続点aを
FET(電界効果トランジスタ)のゲートに接続して構
成される。又、バイパス回路は、電圧駆動素子(FE
T)のゲート回路の一端aと前記並列回路の直流電源側
の一端b間にコレクタ、エミッタが接続され、ベースが
定電圧素子DZ2を介して前記並列回路のコンデンサ側
の一端cに接続されるトランジスタQ2により構成され
る。FIGS. 3 and 4 are circuit diagrams of one embodiment of the present invention and operation waveform diagrams of respective parts thereof. The main component of the present invention is that in the inrush current prevention circuit B, a parallel circuit of a voltage driving element (FET) and a resistor (R1) is provided between a DC power supply (E1) and a capacitor (C1), and the voltage driving element (FET) is provided. ), And a bypass circuit for opening the gate circuit by detecting a voltage drop due to the current flowing through the parallel circuit is provided to turn off the voltage driving element. Incidentally, the gate circuit is configured by connecting a connection point a of the resistor R3 and the constant voltage diode DZ1 connected between the DC power supplies to the gate of the FET (field effect transistor). Further, the bypass circuit includes a voltage driving element (FE
T) A collector and an emitter are connected between one end a of the gate circuit and one end b on the DC power supply side of the parallel circuit, and a base is connected to one end c of the parallel circuit on the capacitor side via a constant voltage element DZ2. It is composed of a transistor Q2.
【0007】本発明回路の主回路動作は基本的には従来
例とほぼ同じである。突入電流防止回路Bの動作を説明
すると、図4で時間t=t1の時入力電圧Vinが印加
されると、R3とDZ1によりFETのゲートに電圧が
印加され一度導通するが、C1に電荷を充電するために
突入電流が流れるとR4とシリーズのFETのON抵抗
及びその2つに並列に接続されたR1との合成抵抗(R
X)の両端に発生する電圧降下がDZ2のツェナー電圧
をのり越えると、Q2が導通し、FETをOFFさせ
る。それ以後R1により制限される電流によりC1は充
電され、C1が充分に充電されR1での電圧降下がDZ
2の電圧以下となるとFETは導通し通常電流を流す。
すなわち突入電流はDZ2のツェナー電圧を上記のRX
でわった電流にて制限される。本発明における突入電流
を制限する原理は入力瞬断後復帰の場合にも同様であ
る。時間t=t2にて、入力の瞬断が発生しt3にて復
帰するとVC1の電圧が低下しているためC1を充電す
るための突入電流が流れるが、RXに発生する電圧降下
がDZ2のツェナー電圧を越えるとFETをOFFし、
電流が制限される。以後R1によりC1は充電され、R
1の電圧降下がDZ2以下となるとFETは導通し、通
常電流を流す。本回路においてFETのON抵抗により
突入電流を検出することができれば抵抗R4は不要であ
る。The main circuit operation of the circuit of the present invention is basically the same as that of the conventional example. The operation of the inrush current prevention circuit B will be described. When the input voltage Vin is applied at time t = t1 in FIG. 4, a voltage is applied to the gate of the FET by R3 and DZ1 and the FET is once conducted. When an inrush current flows for charging, the combined resistance of R4 and the series resistor (R1) connected in parallel with the ON resistance of the series FET (R1)
When the voltage drop across X) exceeds the Zener voltage of DZ2, Q2 conducts and turns off the FET. Thereafter, C1 is charged by the current limited by R1, C1 is sufficiently charged, and the voltage drop at R1 becomes DZ
When the voltage becomes equal to or lower than 2, the FET conducts, and a normal current flows.
In other words, the inrush current changes the Zener voltage of DZ2 to the above RX
Current limit. The principle of limiting the inrush current in the present invention is the same as in the case of return after momentary input interruption. At time t = t2, an instantaneous interruption of the input occurs, and when returning at t3, the rush current for charging C1 flows because the voltage of VC1 has dropped. When the voltage is exceeded, the FET is turned off,
Current is limited. Thereafter, C1 is charged by R1, and R1 is charged.
When the voltage drop of 1 becomes equal to or less than DZ2, the FET conducts, and a normal current flows. In this circuit, if the inrush current can be detected by the ON resistance of the FET, the resistor R4 is unnecessary.
【0008】[0008]
【発明の効果】本発明によれば図4−dに示すように入
力瞬断し、又復電した状態であっても過大な突入電流を
防止でき、又、トランスに補助巻線を設ける必要がな
い。従って回路構成が簡単であると同時にコンデンサC
1、整流用ダイオードD1、及び図示しない入力ヒュー
ズ等の破損を防止できる等実用上の効果は大きいAccording to the present invention, an excessive inrush current can be prevented even when the input is momentarily interrupted and the power is restored as shown in FIG. 4D, and it is necessary to provide an auxiliary winding in the transformer. There is no. Therefore, the circuit configuration is simple and the capacitor C
1. Practical effects are large, such as prevention of breakage of the rectifying diode D1 and an input fuse (not shown).
【図1】従来回路図FIG. 1 is a conventional circuit diagram
【図2】従来回路の各部動作波形図FIG. 2 is an operation waveform diagram of each part of the conventional circuit.
【図3】本発明の一実施例回路図FIG. 3 is a circuit diagram of one embodiment of the present invention.
【図4】本発明回路の各部動作波形図 D1 整流用ブリッジダイオード B 突入電流防止回路 C1 入力用コンデンサ T 出力トランス Q1 スイッチ素子(トランジスタ) FET 電界効果トランジスタ(電圧駆動素子)FIG. 4 is an operation waveform diagram of each part of the circuit of the present invention. D1 Rectifier bridge diode B Inrush current prevention circuit C1 Input capacitor T Output transformer Q1 Switch element (transistor) FET Field effect transistor (voltage drive element)
フロントページの続き (51)Int.Cl.7 識別記号 FI H02M 3/28 H02M 3/28 C Continued on the front page (51) Int.Cl. 7 Identification code FI H02M 3/28 H02M 3/28 C
Claims (2)
続された平滑用コンデンサと、前記平滑用コンデンサの
端子間に出力トランスの1次巻線及びスイッチ素子を直
列に接続し、前記スイッチ素子のスイッチング動作を利
用して、前記出力トランスの2次巻線側に変換出力を供
給すると共に、該直流電源の一端と該平滑用コンデンサ
の一端間に電圧駆動素子と抵抗の並列回路を設け、前記
並列回路を介して該平滑用コンデンサの突入電流を制限
するようにしたスイッチング式直流安定化電源におい
て、前記電圧駆動素子のゲート回路を設けると共に前記
ゲート回路を解放するバイパス回路を設け、且つ前記バ
イパス回路は前記ゲート回路の一端aと前記並列回路の
前記直流電源側の一端b間にエミッタ、コレクタが接続
され、ベースが定電圧素子を介して前記並列回路の平滑
用コンデンサの一端cに接続されたトランジスタを含
み、該並列回路の合成抵抗の両端電圧降下を該定電圧素
子により直接検出し、該検出電圧が該定電圧素子のツェ
ナー電圧に達した時、該バイパス回路を介して該電圧駆
動素子をオフせしめるようにしたことを特徴とするスイ
ッチング式直流安定化電源。A first capacitor connected between a DC power supply and an output terminal of the DC power supply; a primary winding of an output transformer and a switching element connected in series between terminals of the smoothing capacitor; A conversion output is supplied to the secondary winding side of the output transformer using the switching operation of the element, and a parallel circuit of a voltage driving element and a resistor is provided between one end of the DC power supply and one end of the smoothing capacitor. A switching type stabilized DC power supply configured to limit an inrush current of the smoothing capacitor via the parallel circuit, wherein a gate circuit of the voltage driving element is provided and a bypass circuit for releasing the gate circuit is provided; and In the bypass circuit, an emitter and a collector are connected between one end a of the gate circuit and one end b of the parallel circuit on the DC power supply side, and the base is a constant current source. A transistor connected to one end of a smoothing capacitor of the parallel circuit via an element, wherein a voltage drop across the combined resistor of the parallel circuit is directly detected by the constant voltage element, and the detected voltage is detected by the constant voltage element. Wherein the voltage driving element is turned off via the bypass circuit when the Zener voltage of the switching type is reached.
列に接続し、前記抵抗と定電圧ダイオードの接続点を電
圧駆動素子のゲートに接続してなるゲート回路を設けた
ことを特徴とする特許請求の範囲第(1)項記載のスイ
ッチング式直流安定化電源。2. A gate circuit comprising a resistor and a constant voltage diode connected in series between a DC power supply, and a connection point between the resistor and the constant voltage diode connected to a gate of a voltage driving element. The switching type stabilized DC power supply according to claim (1).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3094658A JP3049108B2 (en) | 1991-01-29 | 1991-01-29 | Switching type DC stabilized power supply |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3094658A JP3049108B2 (en) | 1991-01-29 | 1991-01-29 | Switching type DC stabilized power supply |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04244730A JPH04244730A (en) | 1992-09-01 |
JP3049108B2 true JP3049108B2 (en) | 2000-06-05 |
Family
ID=14116359
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3094658A Expired - Lifetime JP3049108B2 (en) | 1991-01-29 | 1991-01-29 | Switching type DC stabilized power supply |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3049108B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2022102874A1 (en) * | 2020-11-11 | 2022-05-19 | 전남대학교 산학협력단 | High-speed dc circuit-breaker |
-
1991
- 1991-01-29 JP JP3094658A patent/JP3049108B2/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2022102874A1 (en) * | 2020-11-11 | 2022-05-19 | 전남대학교 산학협력단 | High-speed dc circuit-breaker |
Also Published As
Publication number | Publication date |
---|---|
JPH04244730A (en) | 1992-09-01 |
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