JP3047828B2 - Comparator circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a comparator circuit.

[0002]

2. Description of the Related Art As an example of a conventional comparator circuit composed of MOS transistors, see, for example,
-206756 discloses one example. A circuit diagram of the conventional example is shown in FIG. 4, and switches 26, 27, 30, 31, and 26 constituting a differential chopper type comparator are illustrated.
Capacitors 28, 29, PMOS transistors 32, 33, N
MOS transistors 34 and 35 and a constant current source 36;
PMOS transistor 3 constituting an offset correction circuit
7, 38, switches 39 and 40, NMOS transistors 41 and 42, capacitors 43 and 44, and PMOS transistors 47, 49 and 50 forming a strobe latch circuit.
And NMOS transistors 45, 46, 48, 51,
52. Also, FIG.
6 is an operation timing chart of a control signal φ for switching control of 6, 27, 30, 31, 39, and 40. Timings T ₁ and T ₃ at which the control signal φ is at “H” level correspond to the reset operation state and “L”. "the timing T ₂ of the level corresponding to a comparison operation state.

[0003] In FIG 4, the differential input voltage is input from an external V _in ⁺ and V _in ^- a differential reference input voltage V _ref
^{+ And} V _ref ^- are input to switches 26 and 27 which selectively output one of these differential inputs by a control signal φ. In other words, the switch 26, the differential input voltage V _in
^{+ And the} differential reference input voltage V _ref ⁺ are input,
The switch 27, the differential input voltage V _in ^- and differential reference input voltage V _ref ^- is entered. The comparator circuit is in a reset operation period (timing T ₁ and T ₃ )
, The control signal φ is input at the “H” level as shown in FIG. In the reset operation period, "H" in response to the input of the level of the control signal phi, the switching action of switches 26 and 27, the differential input voltage V _in ⁺ and V _in ^- is selectively outputted. At the same time, switches 30 and 31 are controlled by “H” level control signal φ to be in “contact” state, and the drains of NMOS transistors 34 and 35 are connected to their respective gates. Then, the switches 39 and 40 are also in the "contact" state.

[0004] The differential input is selectively output by the switch 26 and 27 the voltage V _in ⁺ and V _in ^- are inputted via the sampling action by capacitor 28 and 29, to the gate of the corresponding NMOS transistors 34 and 35 . Also, NMOS transistors 34, 35, 4
1 and 42 are diode-connected, so that NM
The offset voltage generated by the mismatch between the threshold voltages of the OS transistors 34 and 35 is applied to the capacitors 43 and 44 via the current mirror circuit constituted by the PMOS transistors 32, 33, 37 and 38, The charge corresponding to the voltage is stored in the capacitors 43 and 44 by being stored. Note that during this reset operation period, the PMOS transistor 47 is turned off because the control signal φ is at “H” level.
And PMOS transistors 49 and 50 and NMOS transistors 45, 46, 48 and 51
The power supply voltage V _DD is not supplied to the strobe latch circuit including the strobe latch circuit 52 and the strobe latch circuit 52. Therefore, the strobe latch circuit does not operate.

Next, during the comparison operation period of the comparator circuit, as shown in FIG.
Entered by level. During this comparison operation period,
When the control signal φ of “L” level is input, the switch 2
6 and 27, the differential input reference voltage V
_ref ⁺ and V _ref ^- are selected and output, and each has a capacitance of 2
Input to the gates of the corresponding NMOS transistors 34 and 35 via 8 and 29. In this case,
The switches 30, 31, 39, and 40 are in the "OFF" state, and one ends of the capacitors 43 and 44 are connected to N
Since the connection is made only to the gates of the MOS transistors 41 and 42, the electric charges accumulated in the capacitors 43 and 44 are held without change during the above-described reset operation period. Therefore,
For the gate terminals of the NMOS transistors 34 and 35, the differential voltage between the input voltage V _in and the input reference voltage V _ref is applied. As a result, a current corresponding to the difference voltage input flows through the PMOS transistors 32 and 33,
Further, the signal is amplified and output by an offset-compensated inverter circuit constituted by the PMOS transistor 37 and the NMOS transistor 41 and an offset-compensated inverter circuit similarly constituted by the PMOS transistor 38 and the NMOS transistor 42. Amplified output of the inverter circuit is amplified and input to the gate of the NMOS transistors 45 and 46, are driven performed with respect to the strobe latch circuit, negative output voltage V _out from the drain of the PMOS transistor 49 ^- or Output A positive output voltage V _out ⁺ is output from the drain of the PMOS transistor 50.

[0006]

In [0008] Conventional comparator circuit described above, in response to the reset operation period and the comparison period, the differential input voltage V _in ⁺ / V _in ^- a differential reference input voltage V _ref ⁺ / V _ref ^- switching, as well except for switches including a circuit switch or the like, a constant current source by counting one transistor, the number of MOS transistors is in need of 17 and more. In particular, in the case of a comparator circuit, although there are various application aspects, for example, in a semiconductor integrated circuit using a large number of comparator circuits such as an integrated circuit for an A / D converter, the increase in the number of elements increases the area of the semiconductor chip. And there is a drawback that high integration is hindered.

In addition, there is a manufacturing defect that the manufacturing cost of a semiconductor chip increases with the increase in the number of elements in a semiconductor integrated circuit that frequently uses a comparator circuit, and the yield decreases.

[0008]

A comparator circuit according to the present invention has a control signal at one end which is supplied to a first input terminal during a reset operation period.
Voltage is applied, and the control signal is set to a first voltage during a comparison operation period.
A first capacitor to which a reference voltage is input;
The second input voltage is applied during the reset operation period.
Wherein the control signal is a second reference voltage during the comparison operation period.
And the other end of the first capacitor is connected to the second capacitor.
1 input terminal, and the other end of the second capacitor is connected to the second input terminal.
Are connected to the first input voltage and the first input voltage.
A difference voltage from the reference voltage, the second input voltage and the second
The first output signal is compared with the difference voltage between the first output signal and the reference voltage.
Comparing means including a differential amplifier for outputting a second output signal
And a third input to which one end is applied with the first output signal.
A third capacitor connected to a terminal, and one end connected to the second output
A fourth capacitor connected to a fourth input terminal to which a signal is applied
And a gate connected to the other end of the third capacitor,
Is the difference between the first output signal and the second output signal.
A first amplified signal generated by amplifying the signal is output
A first transistor connected to the first output terminal;
Is connected to the other end of the fourth capacitor, and the drain is
The difference signal between the first output signal and the second output signal is increased.
A second output in which a second amplified signal generated by the width is output;
And a differential pair connected to the first terminal and the first transistor.
A second transistor to be formed, and a third transistor connected to the third input terminal.
Connected between the second output terminals according to the control signal.
Becomes non-conductive during the reset operation period and the comparison operation period
First switch means for communicating with the fourth input terminal
And the first output terminal, and is connected to the control signal.
The non-conductive state during the reset operation period.
Amplifying means including second switch means passing through the period.
And a step .

[0009]

[0010]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. As shown in FIG. 1, in the present embodiment, switches 1, 2, 7, and
8, capacitances 3, 4, PMOS transistors 5, 6, constant current source 9, NMOS transistors 20, 21, and PMOS transistors 10, 11, N constituting a fully differential amplifier circuit
MOS transistors 12, 13, 16, 17, switches 14, 15, capacitors 18, 19, and a constant current source 22. The NMOS transistors 12 and 13 are fully differential type during the comparison operation period. It functions as a switch for changing circuit connection so that the amplifier circuit performs a latch operation. FIG. 2 is an operation timing diagram of a control signal φ for controlling the switching of the switches 1, 2, 7, 8, 14, and 15. As in the case of the above-described conventional example, the control signal φ is at the “H” level. The timings T ₁ and T ₃ correspond to the reset operation period, and the “L” level timing T ₂ corresponds to the comparison operation period.

[0012] In FIG. 1, as in the conventional example, the differential input voltage V _in ⁺ and V _in is input from the outside ^- and,
The differential input reference voltages V _ref ⁺ and V _ref ^- are input to switches 1 and 2 which selectively output one of these differential inputs by a control signal φ. While the comparator circuit is in the reset operation period (timing T ₁ and T ₃ ), the control signal φ is input at “H” level as shown in FIG. In the reset operation period, it receives the "H" input level of the control signal phi, the switching action of the switch 1 and 2, the differential input voltage V _in
^{+ And} V _in ^- are selectively output. At the same time, switch 7
And 8 are controlled by an “H” level control signal φ to be in “contact” state, and the drains of the PMOS transistors 5 and 6 are connected to their respective gates. Then, the switches 14 and 15 are also in the “contact” state.

[0013] The differential input is selectively output by the switch 1 and 2 voltage V _in ⁺ and V _in ^- via respective sampling action by capacitor 3 and 4, the corresponding NM
Input to the gates of OS transistors 5 and 6. In addition, the PMOS transistors 5 and 6 are diode-connected via the switches 7 and 8 which are in the “contact” state, and similarly, via the switches 14 and 15 which are in the “contact” state, NMOS transistor 1
6 and 17 are also diode-connected. As a result, the offset voltage generated by the mismatch between the threshold voltages of the PMOS transistors 5 and 6 is applied to the capacitors 3 and 4, respectively, and the charges corresponding to the offset voltages are accumulated and held. Similarly, an offset voltage generated due to a mismatch between the threshold voltages of the NMOS transistors 16 and 17 is applied to the capacitors 18 and 19, respectively, and charges corresponding to the offset voltages are accumulated and held. Note that during this reset operation period, the inverted signal φ ^* of the control signal φ is input to the respective gates of the NMOS transistors 12 and 13 functioning as switches, whereby the NMOS transistors 12 and 13 function as switches. 13 is O
The state is FF.

Next, during the comparison operation period of the comparator circuit, as shown in FIG. 2, the control signal .phi.
Entered by level. During this comparison operation period,
When the control signal φ of “L” level is input, the switch 1
And 2, the differential reference input voltage V _ref ⁺
And V _ref ^- are selected and output, and via the capacitors 3 and 4, respectively, the corresponding PMOS transistors 5 and 6
Input to the gate. In this case, switch 7,
8, 14 and 15 are in the "OFF" state, and one ends of the capacitors 3 and 4 are connected to the PMOS transistors 5 and 5, respectively.
6 is connected to only the gates of the PMOS transistors 5 and 6, so that the charges stored in these capacitors 3 and 4 do not change. Therefore, the reference input voltage V _ref ⁺ a reference input voltage V _ref ^- difference voltage is applied. As a result, corresponding to the difference voltage, the current flowing through the PMOS transistors 5 and 6 is changed by the diode-connected NMOS
It flows through transistors 20 and 21 to ground.
In this case, since the inverted signal φ ^* of the control signal φ is at the “H” level, the NMOS functioning as a switch
Transistors 12 and 13 are both turned on,
As a result, the fully differential amplifier circuit has a circuit configuration functioning as an offset-compensated strobe latch circuit using the PMOS transistors 10 and 11 as loads, and a latch operation is performed to enable diode-connected PMOS.
From the drain of the transistor 10, a positive output voltage V _out
⁺ It is output, and a negative output voltage V _out from the same drain of the PMOS transistor 11 of diode-connected ^-
Is output.

As described above, the present embodiment maintains the processing speed and the high-precision operation function substantially equal to those of the conventional circuit,
The number of MOS transistors to be used, excluding the switches, can be reduced to 12 by counting the constant current source as one transistor, and the number is greatly reduced. Regarding the current consumption, during the comparison operation period, the strobe latch circuit enters the latch operation state, so that the operation state of the NMOS transistors 16 and 17 becomes deep or non-operational. Of the NMOS transistors 16 and 1
In both cases, the device operates in the triode region. Therefore, the terminal voltage of the constant current source 22 decreases, and the drain-source voltage of the MOS transistor (not shown) constituting the constant current source 22 decreases. As a result, the current value of the constant current source 22 becomes Dramatically reduced. For this reason, in the comparison operation period, the current value of the consumed current is only the value determined by the constant current source 9, and it is possible to realize low power consumption.

Next, a second embodiment of the present invention will be described. FIG. 3 is a circuit diagram showing the second embodiment. As shown in FIG. 3, in the present embodiment, the switches 1, 2, 7, 8, the capacitors 3, 4, the PMOS transistors 5, 6, the constant current source 9, and the NMOS transistor which constitute the fully differential chopper type comparator 12, 13, 20, 21 and a PMOS transistor 10, which constitutes a fully differential amplifier circuit,
11, 23 to 25, NMOS transistors 16, 17,
Switches 14, 15, Capacities 18, 19 and Constant Current Source 2
2 and an NMOS transistor 1
Similarly to the first embodiment, the switches 2 and 13 function as switches for changing the circuit connection so that the fully differential amplifier circuit performs the latch operation during the comparison operation period. As is clear from the comparison with FIG.
In the present embodiment, PMOS transistors 23 to 25 are newly added, and the PMOS transistors forming the load of the strobe latch circuit in the first embodiment described above.
There is a difference in that a load is formed by PMOS transistors 10, 11, 23, 24 and 25 instead of transistors 10 and 11. In this case,
Since the gate electrodes of the PMOS transistors 23 and 25 are both grounded, they operate in the triode region. The PMOS transistor 24 is ON / OFF controlled by a control signal φ and its inverted signal φ ^* .

In FIG. 3, similarly to the conventional example and the first embodiment, the differential input voltage V
_in ⁺ and V _in ^- and the differential reference input voltages V _ref ⁺ and V _ref ^- are input to switches 1 and 2 that selectively output one of these differential inputs by a control signal φ. While the comparator circuit is in the reset operation period (timing T ₁ and T _{3 in} FIG. 2), the control signal φ
Is input at "H" level. During this period,
In response to the input of the control signal φ of “H” level, the switch 1
And the second switch action, the differential input voltage V _in ⁺ and V _in ^- is selectively outputted. At the same time, switches 7 and 8
Is controlled by an “H” level control signal φ to
And the PMOS transistors 5 and 6 are diode-connected, respectively, and the switches 14 and 15 are also in the "contact" state.
6 and 17 are each diode-connected.

The selected output differential input voltage V _in ⁺ and V _in ^- via respective sampling action by capacitor 3 and 4 is input to the gate of the NMOS transistors 5 and 6. At this time, the offset voltage generated due to the mismatch between the threshold voltages of the PMOS transistors 5 and 6 is applied to the capacitors 3 and 4, respectively, and the charge corresponding to the offset voltage is accumulated and held.
Similarly, an offset voltage generated due to a mismatch between the threshold voltages of the NMOS transistors 16 and 17 is applied to the capacitors 18 and 19, respectively, and charges corresponding to the offset voltages are accumulated and held. During the reset operation period, since the inverted signal φ ^* of the control signal φ is at “L” level, the NMOS transistors 12 and 13 are in the OFF state.

Next, during the comparison operation period, the differential reference input voltage V
_ref ⁺ and V _ref ^- are selected and output, and capacitors 3 and 4 are output.
Are input to the gates of the corresponding PMOS transistors 5 and 6. Switches 7, 8, 14 and 15
Is in a "disconnected" state, one ends of the capacitors 3 and 4 are connected only to the gates of the PMOS transistors 5 and 6, respectively, and the charges stored in the capacitors 3 and 4 do not change. Therefore, as described above, the reference input voltage V _ref ^{+ is} applied between the gates of the PMOS transistors 5 and 6.
Differential voltage is applied ^- the reference input voltage V _ref and. Then, the current flowing through the PMOS transistors 5 and 6 corresponding to the difference voltage flows to the ground through the diode-connected NMOS transistors 20 and 21. On the other hand, since the inverted signal φ ^* of the control signal φ is at the “H” level, both the NMOS transistors 12 and 13 are turned on, and the PMOS transistor 24 is turned off. Thus, the fully differential amplifier circuit includes the PMOS transistors 10, 11, 23, and 25.
, And performs a latch operation, performs a latch operation, outputs a positive output voltage V _out ⁺ from the drain of the diode-connected PMOS transistor 10, and A negative output voltage V _out ^- is output from the drain of the connected PMOS transistor 11. In this embodiment, since the strobe latch circuit is equivalently constituted by two latch circuits, there is an advantage that the comparison operation function as the comparator circuit is further accelerated.

As described above, according to the present embodiment, the number of MOS transistors to be used excluding the switches is reduced while maintaining a higher processing speed and a higher precision operation function than the conventional circuit.
The number of the constant current source is counted as one transistor and is within 15 transistors, and the number is reduced as compared with the conventional example while the effect of improving the processing speed is obtained. As for the current consumption, as in the first embodiment, the strobe latch circuit enters the latch operation state during the comparison operation period, so that the operation state of the NMOS transistors 16 and 17 is deeply operated. State, or in an inactive state, these NMs
Both OS transistors 16 and 17 operate in the triode region. Therefore, the constant current source 2
2, the voltage between the drain and source of the MOS transistor (not shown) constituting the constant current source 22 decreases, and as a result, the current value of the constant current source 22 is greatly reduced. . For this reason, in the comparison operation period, the current value of the consumed current is only the value determined by the constant current source 9, and it is possible to realize low power consumption.

[0021]

As described above, the present invention is applied to a comparator circuit having a reset operation period and a comparison operation period, and compares a level of a differential input voltage with a level of a differential reference input voltage. And a fully-differential amplifying circuit having a differential output of the fully-differential chopper-type comparator as a capacitively-coupled input. By connecting the positive-phase input terminal to the positive-phase output terminal and the negative-phase input terminal to the negative-phase output terminal, the number of semiconductor elements of the comparator circuit and the semiconductor integrated circuit that uses the comparator circuit frequently is reduced. And the effect that the area of the semiconductor chip can be reduced can be obtained, and further, the yield in manufacturing can be improved.

Further, during the comparison operation period, it becomes possible to significantly suppress the actual working current value in the fully differential amplifier circuit, whereby the power consumption of the comparator circuit can be reduced. effective.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart of a control signal in the present embodiment.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a conventional example.

[Explanation of symbols]

1, 2, 7, 8, 14, 15, 26, 27, 30, 3,
1, 39, 40 switch 3, 4, 18, 19, 28, 29, 43, 44 capacity 5, 6, 10, 11, 23 to 25, 32, 33, 37,
38, 47, 49, 50 PMOS transistors 9, 22, 36 Constant current source 12, 13, 16, 17, 20, 21, 34, 35, 4
1, 42, 45, 46, 48, 51, 52 NMOS
Transistor

Claims (3)

(57) [Claims] A control signal is applied to one end during a reset operation period.
1 input voltage is applied, and the control signal is in a comparison operation period.
And a first capacitor to which a first reference voltage is input, and
When the control signal is set to the second input voltage during the reset operation period,
And the control signal is applied to the second reference signal during the comparison operation period.
A second capacitor to which the reference voltage is input, and a second capacitor other than the first capacitor
The other end of the second capacitor is connected to a first input terminal.
Is connected to a second input terminal, and is connected to the first input voltage.
A difference voltage between the first reference voltage and the second input voltage;
Comparing the difference voltage with the second reference voltage,
Ratio including a signal and a differential amplifier that outputs a second output signal
Comparing means, and a third input terminal having one end to which the first output signal is applied.
And a third capacitor connected to the second output signal.
A fourth capacitor connected to a fourth input terminal to which is applied
And a gate connected to the other end of the third capacitor,
Is a difference signal between the first output signal and the second output signal.
The first amplified signal generated by amplifying the signal is output.
A first transistor connected to the output terminal of
Is connected to the other end of the fourth capacitor, and the drain is
Amplifying a difference signal between a first output signal and the second output signal
A second output from which a second amplified signal generated as a result is output
Connected to a terminal to form a differential pair with the first transistor
A second transistor, the third input terminal and the
Connected between the second output terminals, and connected in accordance with the control signal.
It becomes non-conductive during the reset operation period and during the comparison operation period.
A first switch means for passing therethrough, and the fourth input terminal;
Connected between the first output terminals and according to the control signal.
Becomes non-conductive during the reset operation period and the comparison operation period
Differential amplifying means including second switch means passing between them
Comparator circuit comprising a, and. 2. The differential amplifier according to claim 1, wherein a gate of said differential amplifier is
The reset operation period according to the input terminal and the control signal
And the fifth switch becomes non-conductive during the comparison operation period.
And a drain connected to one end of the fifth switch means.
A third terminal connected to the other end of the switch means and the third input terminal.
A transistor and a gate connected to the second input terminal and the control signal in accordance with the control signal;
Conducted during the reset operation period, and turned off during the comparison operation period
It is connected to one end of the sixth switching means which is a drain
Is the other end of the sixth switch means and the fourth input terminal
To form a differential pair with the third transistor.
The comparator circuit according to claim 1 , further comprising: a fourth transistor . 3. The differential amplifier according to claim 1 , wherein
Connected between the gate and drain of the transistor,
Control signal to conduct during the reset operation period, and
A third switch means that is non-conductive during an operation period;
2 connected between the gate and the drain of the transistor
Conducting during the reset operation period according to the control signal.
4. The comparator circuit according to claim 1 , further comprising: a fourth switch means that is non-conductive during the comparison operation period .