JP2901726B2 - Read information signal waveform conversion circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a waveform conversion circuit for a read information signal obtained in a performance device for a recording medium carrying an information signal.

BACKGROUND ART CDs in which information signals such as audio signals and video signals are recorded as digital signals on a disk to obtain information signals
Recording medium playing devices (hereinafter, simply referred to as players) such as players and LDD players are widely known.

By the way, at the time of recording, an information signal is converted into a recording signal, and this conversion needs to be performed so as to satisfy the following conditions.

In order to enable clock extraction during reproduction, the maximum inversion interval of the recording signal is finite.

At the time of reproduction, in order to prevent influence on the servo system such as focus and tracking and to enable removal of low-frequency noise components, the recording signal does not include a DC component.

At the time of reproduction, the recording signal recorded in this manner is read by a pickup, and a read information signal, that is, an RF signal obtained by amplification is converted into a binary (1, 10) digital signal by a waveform conversion circuit including a comparator. Convert to

In this comparator, a threshold voltage (hereinafter simply referred to as a threshold) is provided, and the level of the read information signal is compared with the threshold voltage to perform binarization. By the way, an offset, that is, a DC component may be present in an RF signal, and therefore, it is necessary to automatically adjust the threshold according to the offset.

A conventional waveform conversion circuit will be described with reference to FIG. The RF signal supplied to one input of the comparator 1 is compared with a threshold supplied to the other input, converted into a digital signal, and output. The output digital signal is
Next stage signal processing circuit (not shown) and DC component detection circuit 2
And a threshold value corresponding to the detected DC component is output and supplied to the comparator 1. The DC component detection circuit 2 is constituted by a low-pass filter, and its time constant is set to a value sufficiently larger than the maximum inversion interval.

However, when dropout occurs in the RF signal,
1 (or 0) may continue for a long time to the output of the comparator 1. Then, the DC component detection circuit 2 supplied with this output erroneously detects this as a DC component, so that the threshold value abnormally rises (or falls). In FIG. 7A, the output of the comparator shown in FIG. 7B becomes 1 for a long time due to dropout generated in the RF signal. Therefore, the threshold value changes as shown in FIG. 7 (a), and normal conversion is not performed. Therefore, the seventh
As shown in FIG. 3C, an error signal is generated from the start of the dropout, and the error signal continues for a while after the end of the dropout.

SUMMARY OF THE INVENTION [Object of the Invention] Accordingly, an object of the present invention is to provide a waveform conversion circuit for performing normal binarization immediately after the end of the abnormality even when an abnormality such as a dropout occurs in the read information signal. Is to do.

[Configuration of the invention]

Comparing means for comparing a read information signal obtained from a recording medium carrying an information signal having a predetermined maximum inversion interval with a threshold value and outputting a binary digital signal; detecting and detecting a DC component in the digital signal; A threshold setting unit that sets the threshold according to the DC component, and a dropout detection unit that detects the occurrence of dropout of the read information signal, wherein the dropout is the maximum inversion. An inversion command generating means for generating an inversion command signal at a constant interval as long as it continues beyond the interval, and relaying the digital signal to the threshold setting means while inverting the digital signal in accordance with the inversion command signal It has a configuration including relay means.

[Function of the invention]

When converting a read information signal obtained from a recording medium into a digital signal, if the change of the digital signal is longer than a predetermined time, the waveform conversion circuit of the first invention of the present application inverts the digital signal every predetermined time. Thus, the variation of the threshold value is suppressed within a predetermined range to perform appropriate signal conversion.

When converting a read information signal obtained from a recording medium into a digital signal, the waveform conversion circuit of the second invention of the present application receives a dropout occurrence signal when a dropout occurs in the read information signal, and The threshold is held, and the holding is released when the dropout occurrence signal ends. Thus, even if a dropout occurs, appropriate signal conversion into a digital signal is performed.

Embodiment Hereinafter, an embodiment of the first invention of the present application will be described in detail with reference to the drawings.

In FIG. 1, an RF signal from a player is supplied to one input terminal of a comparator 1, a threshold is supplied to the other input terminal, and the input RF signal is digitized to be an output of the comparator 1. The output of the comparator 1 is supplied to an edge detection circuit 3, where a change in a digital signal is detected. In response to the detection, a reset signal is supplied from the edge detection circuit 3 to the inversion command circuit 4. A clock signal is also supplied to the inversion command circuit 4, and a reset signal is triggered to start counting. When the count value reaches a predetermined count value, a logic "1" is output as an inversion command signal.

This inversion command signal is issued for each predetermined count value unless a reset signal is supplied, and is supplied to the relay circuit 5. On the other hand, the digital signal is also supplied to the relay circuit 5, and is supplied to the DC component detection circuit 2 while being inverted while the inversion command signal is present. In the DC detection circuit 2, the output threshold value is increased or decreased according to the input of 1 or 0 supplied.

FIG. 2 shows a specific circuit example of FIG. The edge detection circuit 3 includes an EXOR gate, a resistor, and a capacitor, and supplies a reset signal pulse to the clear terminal of the inversion command circuit 4 at the rising and falling edges of the supplied digital signal.

The counter circuit 4 has a 16
Advances a binary counter, the player is a clock enable is 1 when playing, when the reset signal is not given to invert the output Q _D a clock signal inputted to each be eight counts. When a reset signal is given during the counting operation, the counting is stopped. In the case of this embodiment, since the pulse width of the reset signal is sufficiently shorter than the cycle of the clock signal, counting is started again from the clock signal immediately after the end of the reset signal.

This is shown in FIGS. 3 (a) to 3 (e). Here, assuming that the maximum inversion interval of the recording signal is four cycles of the clock signal, when the RF signal is normal, the output of the comparator 1 is inverted within the maximum inversion interval, and the reset signal for each inversion is sent to the inversion command circuit 4. Given, the clock count value will not be more than four. However, the output of the period comparator when a dropout occurs is not inverted, counting from O _H as shown in FIG. 3 (d) to F _H, the output Q _D each time eight count is inverted.

Here, 8 is used because the circuit can be easily realized.
The output Q _D are inverted every time number counting, the output Q _D each counts a predetermined number other than greater than 4 8 may be reversed.

The relay circuit 5 includes one EXOR gate. Its two inputs, the counter output Q _D of the comparator output and the drawing of FIG. 3 (b) (e), so that the output of the relay circuit 5 shown in FIG. (F), during the drop-out period predetermined It is inverted for each count value (8) and supplied to the DC component detection circuit 2.

The DC component detection circuit 2 includes a low-pass filter including an inverter, an operational amplifier, a resistor, and a capacitor. The output of the DC component detection circuit 2, that is, the threshold value increases when the input is 1, as shown in FIG.
In the case of, it decreases. Therefore, by appropriately selecting the time constant of the low-pass filter, the fluctuation of the threshold can be set within a certain range.

FIG. 3 (g) shows the variation of the threshold value in an enlarged manner, but when expressed on the same scale as that of FIGS. 7 (a) to 7 (c), it becomes as shown in FIGS. 4 (a) to 4 (c). . As shown in FIG. 11A, the threshold hardly changes during the dropout period, and the error signal disappears immediately after the dropout ends, as shown in FIGS.

Further, since the threshold fluctuation range can be reduced, the time constant of the low-pass filter of the DC component detection circuit 2 can be reduced. As a result, although not as bad as dropout, the response to the fluctuation of the direct current component caused by the contamination of the disk or the like becomes faster.

If the player is not playing, and if not properly reproduced even during a performance mode, a very long period of time or when the output of the comparator will stuck to 0 or 1, the counter output Q duty ratio _D is exactly 50% If not, the threshold value gradually shifts and the power supply or the ground sticks. In such a case, even if the correct RF signal is input, the threshold does not return to the correct value again. In order to prevent this, when the player is not operating normally, the clock enable of the counter 4 is set to 0 to stop counting.

FIG. 5 is a configuration diagram of an embodiment of the second invention of the present application.
In the figure, a threshold hold circuit 5 is provided as a relay between the DC component detection circuit 2 and the comparator 1. When a dropout occurs, the threshold at that time is held and a fixed threshold is supplied to the comparator 1. , Into a digital signal. At the end of the dropout, the hold is released and a normal fluctuation threshold is set. Thus, the threshold is independent of dropout and is not affected.

In this case, the dropout can be detected by the edge detection circuit 3 and the inversion command circuit 4 as in the first embodiment of the present invention, or by other dropout detection means.

As described above, in the waveform conversion circuit according to the first invention of the present application, when converting a read information signal obtained from a recording medium into a digital signal, if the change in the digital signal is longer than a predetermined time, The digital signal is inverted every predetermined time to suppress the fluctuation of the threshold value within a predetermined range, and even when an error occurs in the read information signal such as a dropout, normal binarization is performed immediately after the end of the error. It is.

Furthermore, since the fluctuation range of the threshold can be reduced, the time constant of the DC component detecting means can be reduced, and as a result,
The response to the fluctuation of the direct current component caused by the contamination of the disk or the like becomes faster, and the occurrence of errors can be reduced.

Further, in the above embodiment, since the detection of the drop-out and the generation of the inversion command are realized by one counter, the circuit is very simple. In addition, since all circuits other than the DC component detection circuit are constituted by digital circuits, they are also suitable for IC implementation.

When converting a read information signal obtained from a recording medium into a digital signal, the waveform conversion circuit of the second invention of the present application receives a dropout occurrence signal when a dropout occurs in the read information signal, and The threshold value can be held, and the influence of the dropout on the threshold value can be eliminated. Thereafter, when the dropout occurrence signal ends, the holding thereof is released, and after the end of the dropout, normal binarization is immediately performed.

[Brief description of the drawings]

1 is a block diagram of the first embodiment of the present invention, FIG. 2 is a circuit diagram of FIG. 1, FIGS. 3 (a) to 3 (g) are operation waveform diagrams of FIG. 2, and FIG. FIG. 3 is an operation waveform diagram with different time axes, FIG. 5 is a block diagram of an embodiment of the second invention of the present application, FIG. 6 is a block diagram of a conventional example, and FIG. 7 is an operation waveform diagram of FIG. is there. Description of Signs of Main Parts 1 Comparator 2 DC component detection circuit 3 Edge detection circuit 4 Inversion command circuit 5 Relay circuit

Claims (1)

(57) [Claims] 1. A read information signal obtained from a recording medium carrying an information signal having a maximum inversion interval is compared with a threshold value.
Comparison means for outputting a digital signal of a value, threshold value setting means for detecting a DC component in the digital signal and setting the threshold value in accordance with the detected DC component, and generating dropout of the read information signal. A waveform conversion circuit having a dropout detection means for detecting, wherein the inversion command generation means for generating an inversion command signal at a constant interval as long as the dropout continues beyond the maximum inversion interval; and And a relay means for relaying the digital signal to the threshold value setting means while inverting the digital signal in response to a command signal.