JP2999907B2 - Central processing unit with microprogram control - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a central processing unit of a microprogram control type, and more particularly, to a central processing unit for simultaneously processing a plurality of instructions by a pipeline operation.

[0002]

2. Description of the Related Art Many CPUs today perform a pipeline operation for the purpose of improving the processing speed. The pipeline operation divides the processing of an instruction into several processing stages and terminates the processing in a short period of time by operating each stage independently, thereby improving the processing speed.

[0003] In general, the processing of instructions can be broken down into four main parts: instruction fetch, decode,
Run, store results. If these are divided into four processing stages and the pipeline operates ideally, the processing of the instruction is completed every cycle. However, in actual processing, operation becomes complicated due to read / write of operands, reference of a pointer in a memory at the time of memory indirect addressing, variation in execution time of individual instructions, and the like, and the load is concentrated on a specific pipeline stage However, the expected processing speed cannot be obtained easily.

That is, conventionally, in the case of an instruction accompanied by a memory cycle, during the second clock cycle after the fetch,
The instruction is decoded, and two pieces of information, a vector address which is a start address of the microprogram and an offset address in a part of the instruction code, are stored in a queue, and the ALU is stored.
And so on. In the next third clock cycle, the execution unit calculates the operand address from the offset address, sets the calculated operand address in the address register, and starts the memory system. Then, data from the memory system is read in the fourth clock cycle, and addition and the like are performed in the last fifth cycle.

[0005]

As described above, conventionally, in the case of an instruction accompanied by a memory cycle, three cycles of operand address calculation, operand read, and execution are spent in the execution unit after decoding the instruction. Therefore, there is a method in which instruction processing is further finely divided and a pipeline processing such as five stages or six stages is adopted. However, this approach simply adds to the complexity of the complicated pipeline process and adds cost over processing speed.

Therefore, the present invention realizes an improvement in processing speed by appropriately allocating loads without adding a processing stage in a pipeline.

According to the present invention, there is provided a prefetch control unit for controlling prefetching of an instruction from a memory system, an instruction queue for storing a plurality of prefetched instructions, and address generation means. An instruction decoder that sequentially fetches and analyzes instructions and outputs an analysis result, a micro vector queue that stores analysis results from the instruction decoder, and a CCU that generates various control signals in accordance with the output of the micro vector queue
And an execution unit for executing an instruction, wherein the central processing unit performs pipeline processing, wherein an operand address calculation unit for calculating an operand address from an offset address included in the instruction and an address of the address generation unit; An operand address queue for storing the calculated operand address is provided, and information indicating whether or not the instruction is an instruction accompanied by a memory access is set in a part of the micro vector queue. In the last clock cycle in which the processing of the instruction is completed, when the information from the micro vector queue indicates that the instruction involves a memory access, a memory access request from the prefetch control unit and the execution unit Priority is given to the address of the operand address queue. Provided a memory access arbitration unit for outputting the memory system is intended to solve the above problems.

[0008]

According to the present invention, the operand address is calculated simultaneously with the decoding of an instruction, and in the last clock cycle in which the processing of the preceding instruction is completed, if the next instruction is an instruction involving memory access, the prefetch control unit Even if there is a memory access request from the execution unit, the operand address calculated prior to these requests is output to the memory system, and the operand can be read immediately in the next clock cycle.

[0009]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Reference numeral 1 denotes a memory system comprising a memory for storing programs and data and a read / write control circuit thereof, and 2 denotes an address for the memory system. 3 is a data buffer for inputting / outputting data to / from the memory system 1, and 4 is an address counter PREC for generating an address preceding the instruction address being executed. System 1
A read-ahead control unit for pre-reading control of an instruction from the controller; 6 an instruction queue for storing a plurality of instructions read by the pre-read control unit 4; 7 an address counter for decoding DECC8; An instruction decoder for sequentially taking out and analyzing, a micro vector queue 9 for temporarily storing a vector address as a decoding result, a micro program memory 11 for storing a micro program, and a micro sequencer for generating a micro program address. A computer control unit CCU 12 for generating various control signals, an execution unit including a program counter PC 13, an ALU, and a control register group for executing instructions, and 14 arbitrating access to the memory system 1 and accessing the address register 2 Try to It is a memory access arbitration unit to set the memory address.

Here, as shown in FIG. 2, the instruction decoder 7 includes a 10-bit vector address indicating the start address of a microprogram in which the processing of the instruction is described, and the instruction being an instruction involving memory access. The one-bit information M indicating whether or not there is the data is output as a decoding result, and these vector addresses and 12 bits including the M bits are set in the micro vector queue 9. Further, the instruction decoder 7 outputs a 10-bit offset address in a part of the instruction code.

In this embodiment, an adder circuit for adding the 6-bit address of the decoding address counter DECC8 included in the instruction decoder and the 10-bit offset address being output is provided. An operand address calculator 15 for outputting an address and an operand address queue 16 for storing the output operand address are newly provided.

The address AD1 from the operand address queue 16 is input to the memory access arbitration unit 14 together with the addresses AD0 and AD2 from the prefetch control unit 4 and the execution unit 12, and any one of the addresses AD1 One address is configured to be selected. In particular,
The CCU 10 outputs a signal END indicating the completion of processing in the last clock cycle in which the instruction processing is completed, and outputs a signal ALU-REQ from the CCU 10 when a memory access request occurs in the execution unit 12. Both signals are input to the memory access arbitration unit 14. Further, a signal PRE-RE indicating a memory access request from the prefetch control unit 4 is provided to the memory access arbitration unit 14.
Q and M bits from the micro vector queue 9 are also input.

In response to these control signals, the memory access arbitration unit 14 selects the operand address AD1 from the operand address queue 16 with the highest priority when both the signal END and the M bit are "1", Signal E
When either the ND or M bit is “0”, the request by the signal ALU-REQ is preferentially accepted to select the address AD2 from the execution unit 12 and the signal PRE-RE
The request by Q is accepted in the lowest priority order, and in this case, the address AD0 from the prefetch control unit 4 is selected. Thus, the selected address is set in the address register 2 and becomes the address for the memory system 1.

Next, the operation of this embodiment will be described in detail with reference to FIGS. First, the address output from the prefetch control unit 4 based on the PREC 5 is set in the address register 2 and input to the memory system 1 when the memory access arbitration unit 14 permits the access request. The memory system 1 reads and outputs data corresponding to the input address, and the output data is fetched to the instruction queue 6 via the data buffer 3. Such instruction fetch is performed during one clock cycle.

In the next clock cycle, the instruction decoder 7
Is ready to decode the next instruction, the instruction fetched in the instruction queue 6 is decoded by the instruction decoder 7 and the vector address and M
The bit is set, and the operand address calculation unit 15 performs an addition operation on the address of the DECC 8 and the offset address, and the addition result is set in the operand address queue 16. That is, decoding of the instruction and calculation of the operand address are performed in the same clock cycle.

Now, the instruction decoded by the instruction decoder 7 is the instruction 2, and the instruction preceding it is the instruction 1. In FIG. 3, the instruction 2 is decoded in the a cycle and the execution unit 12 precedes it in the b cycle. Assuming that the execution of the instruction 1 is performed, the b cycle for the instruction 1 is the last clock cycle at which the processing of the instruction is completed, and thus the signal END is output from the CCU 10 as shown in FIG. .

If the instruction 2 is an instruction accompanied by a memory access, the signal M becomes "1" after M bits are set in the micro vector queue 9 in cycle a.
Therefore, when the signal END becomes “1” in the b cycle, the access arbitration unit 14 internally generates an address fetch clock ADCL shown in FIG. The content AD1 is set in the address register 2. Therefore, in the next c clock cycle, the operand address of the instruction 2 is output to the memory system 1 as shown in FIG. 3 (F), and the operand read is performed during this cycle (FIG. 3 (G)). The read data is sent to the execution unit 12 via the data buffer 3. Then, in the next d clock cycle, the instruction 2 is actually executed by the execution unit 12 based on the read data.

In the present embodiment, when there is no preceding instruction, the execution unit 12 always executes the NOP instruction and the CCU 10 outputs the clock cycle signal END, so that the instruction 1 involves memory access. When there is no instruction preceding the instruction, as shown in FIG. 4, both the signals END and M become "1" in the cycle in which the instruction 1 is decoded. 1 is read, and the instruction 1 is executed in the next clock cycle. The cycle of this operand read and execution is shown in FIG.
In the following two cycles c and d, the operand 2 of the next instruction, instruction 2, is read and executed.

In the instruction decoding and execution cycle, no access is made to the memory.
In the execution cycle of (1), the prefetch control unit 4 simultaneously fetches the next instruction 3, and thereafter, the same cycle as that of the instruction 2 is repeated for the instruction 3. Therefore, the instructions are apparently executed sequentially every two cycles.

Of course, some instructions do not involve memory access. In this case, even if the signal END becomes "1" in the last clock cycle of the instruction, the M bit is "0" because the M bit is "0". Does not occur, so that the contents of the operand address queue 16 are not set in the address register 2. At this time, if the request signal PRE-REQ from the prefetch control unit 4 is "1", the signal of the PREC5 The address is set in the address register 2, the instruction is prefetched, and the memory system 1 is used effectively.

The first instruction in the operand address queue 16 is configured to be cleared at the start of the cycle following the cycle in which the END signal is output.

[0022]

According to the present invention, decoding of an instruction and calculation of an operand address can be performed in parallel only by adding a very simple circuit configuration, thereby greatly increasing the cost. And high-speed processing can be realized. Further, the number of processes in the execution unit is reduced, so that the microprogram code itself can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram illustrating an output of an instruction decoder in the embodiment.

FIG. 3 is a timing chart showing a timing of fetching an operand address in the embodiment.

FIG. 4 is an explanatory diagram for explaining a pipeline operation of the embodiment.

[Explanation of symbols]

 Reference Signs List 1 memory system 2 address register 4 prefetch control unit 6 instruction queue 7 instruction decoder 9 micro vector queue 10 CCU 12 execution unit 14 memory access arbitration unit 15 operand address calculation unit 16 operand address queue

Claims (1)

(57) [Claims] A prefetch control unit for controlling prefetching of an instruction from a memory system; an instruction queue for storing a plurality of prefetched instructions; and an address generating means for sequentially extracting and analyzing instructions from the instruction queue. An instruction decoder that outputs an analysis result; a micro vector queue that stores the analysis result from the instruction decoder; a CCU that generates various control signals in accordance with the output of the micro vector queue; and an execution unit that executes the instruction. A central processing unit that performs pipeline processing, wherein an operand address calculation unit that calculates an operand address from an offset address included in the instruction and an address of the address generation unit;
An operand address queue for storing the calculated operand address; and information indicating whether or not the instruction is an instruction accompanied by a memory access is set in a part of the micro vector queue. In the last clock cycle in which the processing of the instruction is completed, if the information from the micro vector queue indicates that the instruction involves memory access, a memory access request from the prefetch control unit and the execution unit And a memory access arbitration unit that outputs an address of the operand address queue to the memory system prior to the central processing unit.