JP2990158B1 - Shift register circuit - Google Patents

Abstract

Abstract: PROBLEM TO BE SOLVED: To identify a missing portion of a cylinder of shift data with a simple circuit, and to speed up analysis and measures for a defect. SOLUTION: N-channel type MOS transistors 22 and 23 are turned on when output data 102 and 103 of flip-flops 2 and 1 are logic "1", respectively. Transistors 26 and 27 are flip-flops 3, 2 respectively.
Are turned on when the output data 104 and 103 are logic "1", respectively, and the transistors 30 and 31 are turned on when the output data 105 and 104 of the flip-flops 4 and 3 are both logic "1". When the pair of transistors 22 and 23, 26 and 27, 30 and 31 are both turned on, a missing data cylinder of logic "1" is detected. Also, a pair of P-channel MOS transistors 20
, 21, 24, 25, 28, and 29 are both turned on, a missing data cylinder of logic “0” is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register circuit for detecting missing data in shifted data.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional shift register circuit 49.
The shift register circuit 49 has four flip-flop circuits 1, 2, 3 and 4 as an example. The flip-flop circuit 1 stores the data 101 input via the input terminal SIN at the rising edge of the clock signal 106, the flip-flop circuit 2 stores the output data 102 of the flip-flop circuit 1 at the rising edge of the clock signal 107, The circuit 3 stores the output data 103 of the flip-flop circuit 2 at the rising edge of the clock signal 108, and the flip-flop circuit 4 stores the output data 104 of the flip-flop circuit 3
The data 105 is stored and output at the rising edge of the data 9.

In the case where clock wiring is physically performed,
Since the load resistance and the stray capacitance occur due to the presence of this wiring, if this is expressed by an equivalent circuit, the original clock signal C
The capacitor 5 is connected as a load between the LK and the clock signal 106 input to the flip-flop circuit 1, and the capacitors 5 and 6 and the resistor 11 are loaded between the original clock signal CLK and the clock signal 107 input to the flip-flop circuit 2. Are connected between the original clock signal CLK and the clock signal 108 input to the flip-flop circuit 3.
10 and resistors 13 and 14 are connected as loads, and capacitors 5, 6, and 7 and resistors 11, 12 are connected between the original clock signal CLK and the clock signal 109 input to the flip-flop circuit 4.
Will be connected as a load.

FIG. 6 is a timing chart showing a case where the shift register circuit 49 operates normally. Here, the original clock signal CLK and the flip-flop circuits 1 to
4, capacitors 5 to 10 and resistors 11 to 14 are connected between the clock signals 106 to 109, respectively. In FIG. 6, the skew of the clock signals 106 to 109 to be input to the flip-flop circuits 1 to 4, respectively. Are shown as identical.

First, a first shift operation timing section T
At 0, all the flip-flop circuits 1 to 4 store the logic “1” in advance. In this state, when a logic “0” is input through the input terminal SIN in the section T0 and a logic “1” is input in the subsequent second section T1, the flip-flop circuit 1 converts the logic “0” input in the section T0. Section T
0, T1 is stored at the rising edge a of the clock signal 106, and the flip-flop circuit 2 outputs the output “0” of the flip-flop circuit 1 to the clock signal 1 between the sections T0, T1.
07 is stored at the rising edge a of the flip-flop circuit 3
Is the output "1" of the flip-flop circuit 2 in the sections T0 and T0.
1 is stored at the rising edge a of the clock signal 108,
The flip-flop circuit 4 stores the output “1” of the flip-flop circuit 3 at the rising edge a of the clock signal 109 between the sections T0 and T1.

Next, in a third section T2, the input terminal S
When the logic “1” is input via IN, the flip-flop circuit 1 converts the logic “1” input to the section T1 into the section T1,
The data is stored at the rising edge b of the clock signal 106 during T2, and the flip-flop circuit 2
Of the clock signal 10 between the sections T1 and T2.
7, the flip-flop circuit 3 stores the output “1” of the flip-flop circuit 2 in the sections T1 and T2.
, And the flip-flop circuit 4 stores the output “1” of the flip-flop circuit 3 at the rising b of the clock signal 109 between the sections T1 and T2.

Next, in a fourth section T3, the input terminal S
When the logic “1” is input via IN, the flip-flop circuit 1 converts the logic “1” input to the section T2 into the section T2,
The data is stored at the rising edge c of the clock signal 106 during T3, and the flip-flop circuit 2
Of the clock signal 10 between the sections T2 and T3.
7, the flip-flop circuit 3 stores the output “0” of the flip-flop circuit 2 in the sections T2 and T3.
, And the flip-flop circuit 4 stores the output “1” of the flip-flop circuit 3 at the rising edge c of the clock signal 109 between the sections T2 and T3.

Next, in a fifth section T4, the input terminal S
When the logic “1” is input via IN, the flip-flop circuit 1 converts the logic “1” input to the section T3 into the section T3,
The data is stored at the rising edge d of the clock signal 106 during T4, and the flip-flop circuit 2
Of the clock signal 10 between the sections T3 and T4.
7, the flip-flop circuit 3 stores the output “1” of the flip-flop circuit 2 in the sections T3 and T4.
, And the flip-flop circuit 4 stores the output “0” of the flip-flop circuit 3 at the rising d of the clock signal 109 between the sections T3 and T4.

Therefore, during a normal operation, the logic "0" input via the input terminal SIN in the first shift operation timing section T0 is synchronized with the rising of the original clock signal CLK by the four flip-flop circuits 1-4. The output 105 of the last-stage flip-flop circuit 4 becomes logic “0” in the fifth section T4.

FIG. 8 shows another conventional shift register circuit. This circuit is IEEE Std 1149.1.
And the test switching signal 400 is a logical "0".
, The boundary scan registers 201 and 20
2, 203 and 204 store the data D input from the input terminal 211 at the rising edge of the test clock signal 300, and store the data D in the boundary scan register 2
05, 206, 207 and 208 each have an internal circuit 2
09 to the test clock signal 300
At the rising edge of

Here, in order to output the data stored by each of the registers 201 to 208 to the test data output terminal TDO, the test switching signal 400 is set to logic "1" and the register 201 is set to the test data input terminal TDI. Is stored at the rising edge of the test clock signal 300 and is output via the output terminal SO. The register 202 stores the scan data 302 from the output terminal SO of the register 201 at the rising edge of the test clock signal 300 and outputs the data. The register 203 stores the scan data 303 from the output terminal SO of the register 202 at the rising edge of the test clock signal 300 and outputs it via the output terminal SO.
4 stores the scan data 304 from the output terminal SO of the register 203 at the rising edge of the test clock signal 300 and outputs it via the output terminal SO.

Next, the register 205 registers the register 204
Scan data 305 from the output terminal SO is stored at the rising edge of the test clock signal 300 and the output terminal SO
The register 206 stores the scan data 306 from the output terminal SO of the register 205 at the rising edge of the test clock signal 300 and outputs the same via the output terminal SO, and the register 207 outputs the scan data 306 from the output terminal SO of the register 206. The scan data 307 is stored at the rising edge of the test clock signal 300 and output via the output terminal SO.
Scan data 308 from O
The data is stored at the rising edge of 00 and the data 309 is output to the test data output terminal TDO via the output terminal SO.

By the way, since the boundary scan registers 201 to 208 have recently become difficult to debug the board due to the miniaturization of the wiring on the board, they must be arranged in an LSI to scan data. The purpose of this is to test the wiring connection on the board, which is the boundary of the LSI. In the example shown in FIG. 8, four input terminals 211 and four output terminals 212 are provided. However, the number of pins in an actual LSI is increasing, and a boundary scan register corresponding to several hundred pins is provided. is necessary.

As a conventional example of this type, as disclosed in Japanese Patent Application Laid-Open No. 9-200000, for example, a D-type flip-flop is provided with a D-type flip-flop in order to prevent a latch error due to skew. A method has been proposed that includes a clock delay circuit that generates and outputs a clock that matches a delay time at which data is output from a data output terminal Q of a flip-flop, and a clock output terminal for connecting the output of the delay circuit to the outside. Have been.
Another conventional example is disclosed in, for example, JP-A-8-2357.
As disclosed in Japanese Patent Publication No. 56-56, a data signal and a clock signal corresponding thereto are read from a card on which data is written by a card reader / writer, and the width of these signals and the skew between the signals are measured. A method of comparing a time interval between read data and a read clock with a predetermined value when determining pass / fail has been proposed.

[0015]

By the way, in the conventional shift register circuit shown in FIG. 5, the layout is manually performed to optimize the arrangement of the flip-flops and the clock wiring, thereby avoiding the data omission. .
However, according to this method, when the physical arrangement of the flip-flops and the clock wiring are performed, if the balance of the capacitances 5, 6, 7 and the resistors 11, 12 of the clock wiring is deteriorated,
As shown in FIG. 7, the shift data comes off the cylinder due to the shift of the clock skew 500 between the registers, so that the LS
There is a problem that I malfunctions.

The malfunction will be described with reference to FIG. In this example, the clock signal 108 input to the flip-flop 3 is shifted, so that it operates normally in the sections T0 and T1, but malfunctions occur in the subsequent section T2. That is, the flip-flop 3 is set in the section T
Although the logic “1” is normally stored at the rising edge “a” of the clock signal 108 between 0 and T 1, the capacitances 5 and 6 are connected between the original clock CLK and the clock signal 107 input to the flip-flop 2. And the resistor 11 are connected as loads, and the capacitors 8, 9, 10 and the resistors 13, 14 are connected as loads between the original clock signal CLK and the clock signal 108 input to the flip-flop circuit 3, so that the original clock CLK Due to the difference between the respective delay times from the clock signal 107 to the clock signal 107, the data 103 output from the output terminal O of the flip-flop circuit 2 arrives at the input terminal I of the flip-flop circuit 3 earlier.

Therefore, the flip-flop circuit 2 sets the rising edge b of the clock signal 107 between the sections T1 and T2.
Is propagated to the data 103, and the flip-flop circuit 3 erroneously stores the data at the rising edge b of the clock signal 108 between the sections T1 and T2. That is,
During normal operation, the four flip-flops 1 to 4 sequentially drive logic "0" in synchronization with the rise of the original clock signal CLK.
Is shifted to the final-stage flip-flop 4 in the section T5 to output the output data 105
Becomes logic "0", but in the case shown in FIG. 7, the LSI malfunctions due to a missing data cylinder.

[0018] The reason why the clock skew shift occurs is that when the arrangement of flip-flops and the clock wiring in a large-scale layout are automated, a clock control error, a hard macro, and a clock control error of a user logic are also caused. Affect. Recently, a clock skew adjustment tool such as a clock tree sequence (CTS) is also known, but even with this method, it is difficult to match the same timing.

Further, it is necessary to determine whether or not the LSI malfunction has occurred due to the missing cylinder of the shift data.
The SI is difficult and requires a huge amount of analysis time. Even if it is possible to judge that the cause is the missing cylinder of the shift data based on the analysis result, it is difficult to specify the location of the missing cylinder of the shift data. Further, in order to analyze the missing portion of the cylinder, a test pattern for outputting the state of the shift register inside the LSI to the output terminal is required, and it is necessary to operate circuits other than the shift register inside the LSI. A huge test pattern is required.

The boundary scan shown in FIG.
In the registers 201 to 208, it is difficult to adjust each clock skew of hundreds of boundary scan registers arranged around the chip in an actual LSI. It is difficult to identify a defective part from the boundary scan registers. Furthermore, if data loss occurs at a plurality of locations in hundreds of boundary scan registers, enormous analysis time is required, and if this countermeasure cannot be taken, user reliability will be lost. Become. Further, if a data cylinder missing detection circuit is configured by an OR circuit, an AND circuit, and the like for each shift register and added, the mounting area increases.

The present invention has been made in view of the above-mentioned problems of the prior art, and provides a shift register circuit capable of specifying a missing portion of shift data in a cylinder with a simple circuit, and thus speeding up the analysis and countermeasures of a defect. The purpose is to:

[0022]

In order to achieve the above object, the present invention provides a plurality of storage means for storing input data from a preceding stage in synchronization with an edge of a clock signal and outputting the data to a succeeding stage; front and rear stages of the respective output Kadeta storage means determines whether identical or not, shift and a data directly transmitting detection means for detecting a cylinder omission of shift data when the same
In the register circuit, the data cylinder missing detection means
Is a combination of the preceding and following storage means,
The output data of the storage means is applied to the gate, and the source is
First P-channel MOS transistor connected to power supply
And the output data of the storage means at the subsequent stage are applied to the gate.
And the source is the first P-channel MOS transistor.
Connected to the drain of the
"1" is applied to the drain and the drain output is
The second P channel serving as a data cylinder missing detection signal of logic "0"
MOS transistor and output data of the preceding storage means
The first N channel is applied to the gate and the source is grounded.
Output of channel-type MOS transistor and storage means in subsequent stage
Data is applied to the gate and the source is the first N channel.
Connected to the drain of
Logic "1" is applied to the drain to detect injuries
At the same time, the drain output signal is logic "1".
Signal and a second N-channel MOS transistor
Characterized in that it.

[0023]

Also, the present invention provides a method for detecting an edge of a clock signal.
Synchronously store input data from the previous stage and output to the subsequent stage
A plurality of storage means, and a preceding and succeeding stage of the plurality of storage means
Judge whether each output data is the same or not.
Data cylinder missing detection method to detect as missing cylinder data
In a shift register circuit having a stage, the data cylinder missing detection unit includes, for each combination of the pre-stage and post-stage storage units , output data of the pre-stage storage unit applied to the gate and a source connected to the power supply. P-channel type M
The output data of the OS transistor and the memory unit at the subsequent stage are applied to the gate, and the source is the first P-channel type MO.
A second P-channel MOS transistor connected to the drain of the S transistor, and a logic "0" applied to the gate when a data cylinder missing of logic "0" is detected, and a source connected to the drain of the second P-channel MOS transistor A third P-channel MOS transistor which is applied with a logic "1" to the drain when the cylinder cover is detected and whose drain output is a data cylinder missing detection signal of logic "0"; A first N-channel MOS transistor whose output data is applied to its gate and whose source is grounded, and an output data of a memory device provided at a subsequent stage which is applied to its gate and whose source is said first N-channel MOS transistor N-channel type M connected to the drain of
The logic "1" is applied to the gate when the data missing of the OS transistor and the logic "1" is detected, the source is connected to the drain of the second N-channel MOS transistor, and the logic "1" is detected when the missing data is detected. And a third N-channel MOS transistor whose drain output is a logic "1" data cylinder missing detection signal. Further, the data cylinder missing detection signals of the logics “0” and “1” are transmitted through a common signal line. Further, a terminal for outputting the data cylinder missing detection signal to the outside is provided.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing one embodiment of a shift register circuit according to the present invention, and FIG. 2 is a timing chart showing main signals of the shift register circuit of FIG. The circuit shown in FIG.
9 and a data cylinder missing circuit 50, and the shift register circuit 49 is the same as the conventional example shown in FIG. The data cylinder missing circuit 50 is roughly composed of a circuit for detecting a missing data cylinder of logic “1” and a circuit for detecting a missing data cylinder of logic “0”.

The circuit for detecting a missing data cylinder of logic "1" includes an inverter 15, a P-channel MOS transistor 16, a resistor 17, and N-channel MOS transistors 22, 23, 26, 27, 30, and 31. When,
It has an output terminal SOB of a data cylinder missing detection signal of logic “1”. The circuit for detecting the data cylinder missing of logic “0” includes an N-channel MOS transistor 19 and a resistor 1
8 and P-channel MOS transistors 20, 21, 2
4, 25, 28 and 29, and an output terminal SOA of a data cylinder missing signal of logic "0".

First, a circuit for detecting data cylinder missing of logic "1" will be described in detail. The test signal 110 (TEST) for permitting the detection of the missing data cylinder is output from the inverter 1
The power supply voltage VDD is applied to the gate of the P-channel MOS transistor 16 via the gate 5, and the source of the transistor 16 is applied to the source of the transistor 16. The drain of the transistor 16 is connected via the resistor 17 to the drains of the N-channel MOS transistors 22, 26 and 30 and the output terminal SOB of the data cylinder missing detection signal 112 of logic "1".

The sources of the transistors 22, 26 and 30 are N-channel MOS transistors 23 and 2 respectively.
7, 31 are connected to the drains of the transistors 23, 2
Sources 7 and 31 are grounded. Then, the output data 102 of the flip-flop 1 is applied to the gate of the transistor 23, and the output data 1 of the flip-flop 2
03 is applied to each gate of transistors 22 and 27,
The output data 104 of the flip-flop 3 is applied to the gates of the transistors 26 and 31 and the flip-flop 4
Is applied to the gate of the transistor 30.

Therefore, transistors 22 and 23
Are output data 103 and 10 of the flip-flops 2 and 1
When both 2 are logic "1", the drain of the transistor 22 constitutes an AND gate which becomes logic "0". The transistors 26 and 27 have a drain A of which the drain becomes a logic “0” when the output data 104 and 103 of the flip-flops 3 and 2 are both a logic “1”.
The transistors 30 and 31 constitute an AND gate in which the drain of the transistor 30 becomes logic "0" when the output data 105 and 104 of the flip-flops 4 and 3 are both logic "1".

Next, a circuit for detecting data cylinder missing of logic "0" will be described in detail. Test signal 110 (T
EST) is applied to the gate of the N-channel MOS transistor 19, and the source of the transistor 19 is grounded. The drain of the transistor 19 is connected to the resistor 18
, P-channel MOS transistors 21, 25,
29, and the output terminal SDA of the data cylinder missing detection signal 111 of logic “0”.

The sources of the transistors 21, 25 and 29 are respectively P-channel MOS transistors 20, 2
4, 28 connected to the drains of the transistors 20, 2
The power supply voltage VDD is applied to each of the sources 4 and 28.
Then, the output data 102 of the flip-flop 1 is applied to the gate of the transistor 20, and the flip-flop 2
Is applied to the gates of the transistors 21 and 24, and the output data 104 of the flip-flop 3
Is applied to the gates of the transistors 25 and 28, and the output data 105 of the flip-flop 4 is
Is applied to the gates.

Therefore, transistors 20 and 21
Are output data 103 and 10 of the flip-flops 2 and 1
2 constitutes a NAND gate in which the drain of the transistor 21 becomes logic "1" when both are logic "0". Similarly, when the output data 104 and 103 of the flip-flops 3 and 2 are both logic "0", the drains of the transistors 25 and 25 become logic "1".
An AND gate is formed, and transistors 28 and 29 are
When the output data 105 and 104 of the flip-flops 4 and 3 are both logic "0", the drain of the transistor 29 constitutes a NAND gate whose logic is "1".

Next, the operation of the above embodiment will be described with reference to FIG. In FIG. 2, the clock signal 108 input to the flip-flop 3 is shifted (clock skew 500 shown) as in the case shown in FIG. First, the case of detecting missing data cylinder of logic "1" will be described. In the data cylinder missing circuit 50, the test signal 110 is set to logic "1" in advance to turn on the transistor 16 (the data cylinder missing detection signal 112 of logic "1" is logic "1"). Is shifted. That is, first, in the first shift operation timing section T0, the flip-flop circuits 1 to
4 both store the logic "0" in advance, and in this state, input the logic "1" through the input terminal SIN.

In the first section T0, since no missing data cylinder of logic "1" has occurred, the output data 102 to 105 of the flip-flop circuits 1 to 4 are all logic "0".
It is. Therefore, since the N-channel MOS transistors 22, 23, 26, 27, 30, and 31 are all off, the data cylinder missing detection signal 112 of logic "1" becomes logic "1", thereby the data of logic "1". It is possible to detect that cylinder missing has not occurred.

In the subsequent second section T1, the input terminal SI
When logic “0” is input via N, the flip-flop circuit 1 converts the logic “1” input to the section T0 into the sections T0, T
1 is stored at the rising edge a of the clock signal 106,
The flip-flop circuit 2 stores the output “0” of the flip-flop circuit 1 at the rising a of the clock signal 107 between the sections T0 and T1, and the flip-flop circuit 3 stores the output “0” of the flip-flop circuit 2 in the section T0, The flip-flop circuit 4 stores the output “0” of the flip-flop circuit 3 at the rising edge “a” of the clock signal 109 between the sections T0 and T1.

In the second section T1, no data cylinder missing of logic "1" has occurred, so that the output data 102 of the flip-flop circuit 1 is logic "1" and the output data 103 of each of the flip-flop circuits 2-4. To 105 are logic "0". Therefore, since the N-channel MOS transistors 22, 23, 26, 27, 30 and 31 are all off, the data cylinder missing detection signal 11 of logic "1" is output.
2 becomes logic "1", which makes it possible to detect that data cylinder omission of logic "1" has not occurred.

In the following third section T2, the input terminal SI
When a logic “0” is input through N, the flip-flop circuit 1 converts the logic “0” input in the section T1 into the section T
1 and T2 are stored at the rising edge b of the clock signal 106, and the flip-flop circuit 2 outputs the output “1” of the flip-flop circuit 1 to the clock signal 1 between the sections T1 and T2.
It is stored at the rising b of 07.

At this time, during normal operation of the flip-flop circuit 3, the output "0" of the flip-flop circuit 3 is set to the rising edge b of the clock signal 108 during the sections T1 and T2.
The clock skew 50 is stored as described above.
Since the time at which the data 103 output from the output terminal O of the flip-flop circuit 2 reaches the input terminal I of the flip-flop circuit 3 becomes earlier due to 0, the flip-flop circuit 3 sets the clock signal between the sections T1 and T2. 107
The logic "1" stored at the rising edge b of the memory is stored and malfunctions.

In this case, in the section T2, a data cylinder missing of logic "1" occurs between the flip-flop circuits 2 and 3, so that the N-channel MOS transistors 22 and 2
3, 30 and 31 are all off, and the N-channel MOS transistors 26 and 27 are all on. The resistance 17
Is smaller than the transistors 26 and 27, the logic "1" data cylinder missing detection signal 112 becomes logic "0", which makes it possible to detect the occurrence of logic "1" data cylinder missing. . Further, it is possible to detect the occurrence of the data cylinder missing of the logic “1” between the flip-flop circuits 2 and 3 at the timing when the data cylinder missing detection signal 112 of the logic “1” becomes the logic “0”.

To detect a missing data cylinder of logic "0", the data cylinder missing circuit 50 sets the test signal 110 to logic "1" in advance and turns on the transistor 19 (detects a missing data cylinder of logic "0"). The signal 111 is set to logic "0", and then the data of logic "0" is shifted by the shift register circuit 49. Referring to FIG. 7, when both the output data 103 and 104 of the flip-flops 2 and 3 become logic "0" in the section T2, both the transistors 24 and 25 are turned on.
3, the output data 10 of the flip-flops 3 and 4
When both 4 and 105 become logic "0", transistor 2
8 and 29 are both turned on.

Therefore, at this time, the data cylinder missing detection signal 111 of logic "0" becomes logic "1", whereby it is possible to detect the occurrence of data cylinder missing of logic "0". Further, it is possible to detect the occurrence of a missing data cylinder of logic “0” between the flip-flop circuits 2 and 3 based on the timing at which the missing data cylinder detection signal 111 of logic “0” becomes logic “1”.

Next, a second embodiment will be described with reference to FIGS. By the way, in the first embodiment, the data cylinder missing detection signal 111 of logic “0” and the data cylinder missing detection signal 112 of logic “1” are output to the outside via the respective output terminals SOA and SOB. Increase. Therefore, in the second embodiment, a common data cylinder missing detection signal 11 of logic “0” and “1” is used.
5 is output through one output terminal SO.

First, a circuit for detecting a missing data cylinder of logic "1" will be described in detail with reference to FIG. A test signal TEST for permitting detection of missing data cylinder is applied to the gate of a P-channel MOS transistor 16 via an inverter 15, and the power supply voltage VDD is applied to the source of the transistor 16. The drain of the transistor 16 is connected to the source of the P-channel MOS transistor 33, and the gate of the transistor 33 has a logic "0" or "1" data cylinder missing detection switching signal H /.
L is applied.

The drain of the transistor 33 is connected to one end of the resistor 18 via the resistor 17 and each drain of the N-channel MOS transistors 36, 38 and 40 (and each drain of the P-channel MOS transistors 35, 37 and 39).
And data cylinder missing detection signal 1 of logic “1” and “0”
15 output terminals SO. Further, the switching signal H / L is supplied to the transistor 3 via the inverter 32.
6, 38, and 40 (and P-channel MOS transistors 35, 37, and 39) are applied to respective gates, and the sources of transistors 36, 38, and 40 are connected to the drains of N-channel MOS transistors 22, 26, and 30. Have been.

As in the first embodiment, the sources of the transistors 22, 26, and 30 are respectively connected to the drains of N-channel MOS transistors 23, 27, and 31, and the sources of the transistors 23, 27, and 31 are connected. Is grounded. The output data 102 of the flip-flop 1 is applied to the gate of the transistor 23, and the output data 103 of the flip-flop 2 is
The output data 104 of the flip-flop 3 is applied to the gates of the transistors 26 and 31, and the output data 105 of the flip-flop 4 is applied to the gate of the transistor 30.

Therefore, when the switching signal H / L is logic "0" and the output data 103 and 102 of the flip-flops 2 and 1 are both logic "1", the drains of the transistors 36, 22 and 23 are turned off. An AND gate having a logic "0" is configured. When the switching signal H / L is logic “0” and the output data 104 and 103 of the flip-flops 3 and 2 are both logic “1”, the drains of the transistors 38, 26 and 27 are logic “0”. And the transistors 40, 30 and 31 are turned on when the switching signal H / L is logic "0" and the output data 105 and 104 of the flip-flops 4 and 3 are both logic "1". 40 constitutes an AND gate whose logic becomes "0".

Next, a circuit for detecting data cylinder missing of logic "0" will be described in detail. The other end of the resistor 18 is connected to the drain of an N-channel MOS transistor 34, and the gate of the transistor 34 is supplied with a data cylinder missing detection switching signal H / L. The source of the transistor 34 is connected to the drain of the N-channel MOS transistor 19, and the test signal TEST is applied to the gate of the transistor 19. The source of the transistor 19 is grounded.

As described above, the drain of the transistor 33 is connected to the drains of the P-channel MOS transistors 35, 37 and 39 via the resistor 17 (detection of missing data cylinders of logic "1" and "0"). Signal 11
5). The switching signal H / L is supplied to the P-channel MOS transistors 35, 37, 39 via the inverter 32.
Is applied to each gate. Transistors 35, 37, 3
9 are connected to transistors 21, 25, 29, respectively.
Connected to each drain.

As in the first embodiment, the sources of the transistors 21, 25 and 29 are respectively connected to the drains of the P-channel MOS transistors 20, 24 and 28, and the sources of the transistors 20, 24 and 28 are connected. Is supplied with a power supply voltage VDD. The output data 102 of the flip-flop 1 is applied to the gate of the transistor 20, the output data 103 of the flip-flop 2 is applied to the gates of the transistors 21 and 24, and the output data 104 of the flip-flop 3 is
The output data 105 of the flip-flop 4 is applied to the gate of the transistor 29.

Therefore, when the switching signal H / L is logic "1" and the output data 103 and 102 of the flip-flops 2 and 1 are both logic "0", the transistors 35, 20 and 21 have their drains turned on. This constitutes a NAND gate having a logic “1”. Similarly,
Transistors 37, 24 and 25 provide switching signal H /
When L is logic “1” and the output data 104 and 103 of the flip-flops 3 and 2 are both logic “0”, the drain of the transistor 37 constitutes a NAND gate having the logic “1”. Reference numeral 29 denotes an N in which the drain of the transistor 39 becomes logic "1" when the switching signal H / L is logic "1" and the output data 105 and 104 of the flip-flops 4 and 3 are both logic "0".
It constitutes an AND gate.

FIG. 4 shows a process for detecting missing data cylinder of logic "0". In this case, the test signal TEST
And the switching signal H / L are both set to logic "1".
Therefore, when data of logic "0" is shifted in the shift register circuit 49 in this state, the clock signal 1 inputted to the flip-flop 3 is shifted as in the case shown in FIG.
08 is shifted (clock skew 500 shown), the transistors 37, 24, and 25 in the section T2.
Are turned on, and when the transistors 39, 28, and 29 are turned on in the section T3, the common data cylinder missing detection signal 115 becomes logic "1".

To detect a missing data cylinder of logic "1", the test signal TEST is set to logic "1" and the switching signal H / L is set to logic "0". Therefore, when the data of logic "1" is shifted in the shift register circuit 49 in this state, the clock signal 10 inputted to the flip-flop 3 is shifted as in the case shown in FIG.
8 (clock skew 500 shown), when the transistors 38, 26, 27 are both turned on in the section T2 and when the transistors 40, 30, 31 are both turned on in the section T3, the common data The cylinder missing detection signal 115 becomes logic “1”.

[0053]

As described above, according to the present invention, it is determined whether or not the output data of the preceding stage and the subsequent stage of the plurality of storage means are the same, and if the output data is the same, it is detected as the missing cylinder of the shift data. Since the detection means is provided, the location where the shift data is missing from the cylinder can be specified with a simple circuit, and the analysis of the failure and the countermeasures can be speeded up.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a shift register circuit according to the present invention.

FIG. 2 is a timing chart showing main signals of the shift register circuit of FIG.

FIG. 3 is a circuit diagram illustrating a shift register circuit according to a second embodiment.

FIG. 4 is a timing chart showing main signals of the shift register circuit of FIG. 3;

FIG. 5 is a circuit diagram showing a conventional shift register circuit.

6 is a timing chart showing main signals in a normal operation of the shift register circuit of FIG. 5;

7 is a timing chart showing main signals of the shift register circuit of FIG. 5 when a data cylinder is missing.

FIG. 8 is a circuit diagram showing another conventional shift register circuit.

[Explanation of symbols]

1-4 Flip-flop circuit 5-10 Capacity 11-14,17,18 Resistance 15,32 Inverter 16,20,21,24,25,28,29,33,3
5,37,39 P-channel MOS transistors 19,22,23,26,27,30,31,34,3
6, 38, 40 N-channel MOS transistor 49 Shift register circuit 50 Data cylinder missing detection circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G01R 31/28-31/3193 G06F 11/22-11/277

Claims (4)

(57) [Claims] 1. A plurality of storage means for storing input data from a preceding stage in synchronization with an edge of a clock signal and outputting the data to a succeeding stage, and determining whether output data of a preceding stage and a succeeding stage of the plurality of storing units are the same. And a data cylinder missing detecting means for detecting as the missing cylinder of the shift data when they are the same , wherein the data cylinder missing detecting means comprises:
For each combination of stages, the output data of the preceding storage means is applied to the gate,
A first P-channel MOS transistor connected to a power supply.
The output data of the register and the storage means at the subsequent stage are applied to the gate,
Is the drain of the first P-channel MOS transistor.
Logic "1" is connected to
A logic "0" is applied to the drain and the drain output is logic "0".
Second P-channel type MO which becomes a data cylinder missing detection signal
The output data of the S transistor and the preceding storage means are applied to the gate,
First N-channel MOS transistor whose ground is grounded
And the output data of the storage means at the subsequent stage is applied to the gate,
Is the drain of the first N-channel MOS transistor.
Logic "1" is connected to
A logic "1" is applied to the drain and the drain output is logic "1".
The second N-channel type MO which becomes a data cylinder missing detection signal
A shift register circuit comprising: an S transistor . Wherein in synchronization with the edge of the clock signal or the preceding stage
Memory means for storing the input data of the
And the output data of the preceding and succeeding stages of the plurality of storage means are the same.
Judge whether the shift data is missing or not.
Data cylinder missing detection means for detecting
In the register circuit, the data-cylinder-missing detecting means may include a memory device of the preceding stage and a succeeding-stage
For each combination of stages, the output data of the preceding storage means is applied to the gate,
A first P-channel MOS transistor connected to a power supply.
The output data of the register and the storage device at the later stage are applied to the gate,
Vinegar of the first P-channel type MOS transistor drain
P-channel MOS transistor connected to the gate
Data and, gate logic "0" at the time of data cylinder omission detection of logic "0"
And the source is the second P-channel type MOS transistor.
Connected to the drain of the transistor to detect cylinder cover
If a logic "1" is applied to the drain
The third output is a data cylinder missing detection signal of logic "0".
The output data of the P-channel MOS transistor and the output of the preceding storage means are applied to the gate,
First N-channel MOS transistor whose ground is grounded
And the output data of the storage device at the later stage is applied to the gate,
Is the drain of the first N-channel MOS transistor.
N-channel MOS transistor connected to
Data and, logic "1" logic "1" when the data cylinder omission detection of the gate
And the source is the second N-channel MOS transistor.
Connected to the drain of the transistor to detect cylinder dropout
If a logic "1" is applied to the drain
The third output is a data cylinder missing detection signal of logic "1".
And an N-channel MOS transistor.
Shift register circuit. 3. The shift register circuit according to claim 2 , wherein the data cylinder missing detection signals of the logic “0” and “1” are transmitted through a common signal line. 4. The apparatus according to claim 1, further comprising a terminal for outputting the data cylinder missing detection signal to the outside.
3. The shift register circuit according to any one of 3 .