JP2979637B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2979637B2 JP2979637B2 JP33653990A JP33653990A JP2979637B2 JP 2979637 B2 JP2979637 B2 JP 2979637B2 JP 33653990 A JP33653990 A JP 33653990A JP 33653990 A JP33653990 A JP 33653990A JP 2979637 B2 JP2979637 B2 JP 2979637B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- pellet
- wiring board
- resin
- metal wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に樹脂封止型の半導体
装置に関する。Description: TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly to a resin-sealed semiconductor device.
〔従来の技術〕 従来のこの種の半導体装置は、リードの一部にペレッ
トをマウントし、このペレットと他のリードとをボンデ
ィングワイヤを用いて電気接続し、その上でこれらを樹
脂で封止している。また、各リードの端部を樹脂の外部
に突出させ、これら端部を実装基板の配線にロー付け等
により接続することで平面実装を実現している。[Prior art] A conventional semiconductor device of this type mounts a pellet on a part of a lead, electrically connects the pellet with another lead using a bonding wire, and then seals the resin with a resin. doing. In addition, planar mounting is realized by projecting the ends of the leads to the outside of the resin and connecting these ends to the wiring of the mounting board by brazing or the like.
第５図はその一例を示しており、樹脂７の外部に突出
されている各リード１〜３の端部を、実装基板８に設け
た配線９にロー付けしている。また、この例ではペレッ
トを搭載したリード１の素子搭載部1aも配線９にロー付
けしている。FIG. 5 shows an example of this, in which the ends of the leads 1 to 3 protruding outside the resin 7 are soldered to the wiring 9 provided on the mounting board 8. In this example, the element mounting portion 1a of the lead 1 on which the pellet is mounted is also soldered to the wiring 9.
この従来の半導体装置では、半導体装置の動作時にペ
レットから発生する熱は、ペレットをマウントしている
リードを介して、あるいは樹脂を通して樹脂外部に放熱
させている。このため、リードが完全に樹脂内に封止さ
れる絶縁タイプの半導体装置の場合には、放熱効果が十
分ではなく、許容損失を大きくすることが難しいという
問題がある。In this conventional semiconductor device, heat generated from the pellet during operation of the semiconductor device is radiated to the outside of the resin through a lead on which the pellet is mounted or through a resin. For this reason, in the case of an insulation type semiconductor device in which the leads are completely sealed in the resin, there is a problem that the heat dissipation effect is not sufficient and it is difficult to increase the allowable loss.
また、非絶縁タイプの半導体装置の場合には、実装基
板８に実装する半導体装置の直下には露呈された配線９
を設けることができないため、配線を迂回させたり多層
配線構造にする等の必要があり、配線面積が大きくな
り、あるいは配線構造が複雑になるという問題がある。In the case of a non-insulated type semiconductor device, an exposed wiring 9 is provided immediately below the semiconductor device mounted on the mounting substrate 8.
Cannot be provided, it is necessary to detour the wiring, or to have a multilayer wiring structure, and there is a problem that the wiring area becomes large or the wiring structure becomes complicated.
さらに、ボンディングワイヤのワイヤループが異常に
高いものが発生した場合でも、樹脂内に封入した後では
これを判別することができず、したがって半導体装置の
電気的特性が良品であれば製品として使用されるため、
経時変化による信頼性の低下が生じることがあるという
問題がある。Furthermore, even if the wire loop of the bonding wire is abnormally high, it cannot be determined after encapsulation in the resin, so that if the electrical characteristics of the semiconductor device are good, it is used as a product. Because
There is a problem that the reliability may be deteriorated due to aging.
本発明の目的は、これらの問題を解消した半導体装置
を提供することにある。An object of the present invention is to provide a semiconductor device which solves these problems.
本発明の半導体装置は、リード上にマウントされたペ
レットの表面側にペレットと所要間隔おいて金属配線板
を設け、この金属配線板を樹脂内に一体的に封止し、か
つ前記リードの端部と前記金属配線板の両端部を、それ
ぞれ同一平面上に位置する状態に樹脂の各異なる辺から
突出させた構成とする。In the semiconductor device of the present invention, a metal wiring board is provided on a surface side of a pellet mounted on a lead at a required interval from the pellet, the metal wiring board is integrally sealed in a resin, and an end of the lead is provided. In this configuration, the portion and both ends of the metal wiring board protrude from different sides of the resin so as to be located on the same plane.
この場合、金属配線板とペレット表面との間隔を、ボ
ンディングワイヤのループ高さの管理限界値の上限に設
定する。In this case, the interval between the metal wiring board and the surface of the pellet is set to the upper limit of the control limit value of the loop height of the bonding wire.
本発明によれば、金属配線板を配線の一部に利用で
き、かつ放熱に利用し、さらにボンディングワイヤのル
ープ高さの異常を判断することに利用できる。ADVANTAGE OF THE INVENTION According to this invention, a metal wiring board can be used for a part of wiring, it can be used for heat dissipation, and can also be used for judging abnormality of the loop height of a bonding wire.
次に、本発明を図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図（ａ）ないし（ｃ）は本発明を絶縁タイプの平
面実装型半導体装置に適用した実施例の内部構造の平面
図、正面図、側面図である。これらの図において、１〜
３はリードであり、リード１に設けた素子搭載部1aにペ
レット４を搭載し、かつこのペレット４と他のリード2,
3とをボンディングワイヤ５で電気接続している。ま
た、前記ペレット４の表面側には、ペレット４に対して
所要間隔おいた位置に金属配線板６を延設している。そ
の上でこれらを樹脂７で封止している。このとき、各リ
ード１〜３の端部と、金属配線板６の両端部は夫々樹脂
７の側面から突出させ、かつ曲げ形成することでそれぞ
れが同一平面上に位置されるように構成している。1 (a) to 1 (c) are a plan view, a front view, and a side view of an internal structure of an embodiment in which the present invention is applied to an insulating type surface mount semiconductor device. In these figures,
Reference numeral 3 denotes a lead. A pellet 4 is mounted on an element mounting portion 1a provided on the lead 1, and the pellet 4 and other leads 2,
3 is electrically connected by a bonding wire 5. A metal wiring board 6 is provided on the surface of the pellet 4 at a position spaced from the pellet 4 by a predetermined distance. Then, these are sealed with a resin 7. At this time, the ends of the leads 1 to 3 and the both ends of the metal wiring board 6 project from the side surfaces of the resin 7 and are formed by bending so that they are located on the same plane. I have.
なお、このような構成の製造に際しては、第２図
（ａ）に示すように、リードフレーム10に形成されたリ
ード１の素子搭載部1aにペレット４をマウントし、他の
リード2,3にボンディングワイヤ５で電気接続を行った
後に、第２図（ｂ）に示すように金属配線板６を形成し
た金属フレーム11を所要の間隔で重ね、この状態で樹脂
封止する。その後、リードフレーム10および金属フレー
ム11に対して曲げ加工と切断を行うことで第１図の構造
が実現される。When manufacturing such a configuration, as shown in FIG. 2 (a), the pellet 4 is mounted on the element mounting portion 1a of the lead 1 formed on the lead frame 10, and the pellets 4 are mounted on the other leads 2 and 3. After the electrical connection is made by the bonding wires 5, the metal frames 11 on which the metal wiring boards 6 are formed are stacked at required intervals as shown in FIG. 2 (b), and the resin is sealed in this state. After that, the lead frame 10 and the metal frame 11 are bent and cut to realize the structure shown in FIG.
なお、金属配線板６とペレット４の表面との間隔は、
ボンディングワイヤ５のループ高さの管理限界値の上限
になるように配置しておくことが好ましい。The distance between the metal wiring board 6 and the surface of the pellet 4 is
It is preferable to arrange the bonding wire 5 so as to be the upper limit of the control limit value of the loop height.
また、第３図（ａ）ないし（ｃ）は非絶縁タイプの平
面実装型半導体装置に本発明を適用した実施例の内部構
造の平面図、正面図、側面図であり、第１図の実施例と
対応する部分には同一符号を付してある。この構成で
は、ペレット４をマウントしたリード１の裏面を樹脂７
の底面に露呈させている。3 (a) to 3 (c) are a plan view, a front view, and a side view of an internal structure of an embodiment in which the present invention is applied to a non-insulating type surface mount type semiconductor device, and FIG. Parts corresponding to the examples are denoted by the same reference numerals. In this configuration, the back surface of the lead 1 on which the pellet 4 is mounted is
It is exposed on the bottom surface.
このように構成された半導体装置によれば、例えば、
第３図に示した非絶縁タイプ平面実装型半導体装置を基
板に実装する場合には、第４図に示すように、リード１
〜３の端部を実装基板８の配線９にロー付け等により実
装を行うと同時に、金属配線板６の両端部を配線９にロ
ー付けしてもよい。また、ここではペレット４を搭載し
た素子搭載部1aの露呈面も配線９にロー付けしている。According to the semiconductor device configured as described above, for example,
When mounting the non-insulating type surface-mount type semiconductor device shown in FIG. 3 on a substrate, as shown in FIG.
At the same time, the both ends of the metal wiring board 6 may be soldered to the wiring 9 at the same time as the mounting of the ends of the metal wiring board 3 to the wiring 9 of the mounting board 8. Here, the exposed surface of the element mounting portion 1a on which the pellet 4 is mounted is also soldered to the wiring 9.
これにより、金属配線板６は半導体装置の両側の配線
９を相互に接続することが可能となり、この金属配線板
６が半導体装置の内部を通過させる配線の一部として構
成でき、実装基板８の配線９を多層化しなくとも交差配
線を実現することができ、実装基板の配線面積を縮小で
きる。Thus, the metal wiring board 6 can connect the wirings 9 on both sides of the semiconductor device to each other, and the metal wiring board 6 can be configured as a part of the wiring passing through the inside of the semiconductor device. The cross wiring can be realized without multi-layering the wiring 9, and the wiring area of the mounting substrate can be reduced.
また、金属配線板６を設けることにより、ペレット４
で発生した熱を金属配線板６を通して放熱することも可
能となり、許容損失を大きくすることができる。In addition, by providing the metal wiring board 6, the pellet 4
Can be dissipated through the metal wiring board 6, and the allowable loss can be increased.
さらに、ボンディングワイヤ５のループが異常に高い
場合には、ボンディングワイヤ５が金属配線板６に接触
して電気的に短絡した状態となるため、樹脂７での封止
後においても金属配線板６に対する導通試験によって半
導体装置の良否を判別することができる。Further, when the loop of the bonding wire 5 is abnormally high, the bonding wire 5 comes into contact with the metal wiring board 6 and is in an electrically short-circuited state. Of the semiconductor device can be determined by a continuity test on the semiconductor device.
以上説明したように本発明は、ペレットの表面側にペ
レットと所要間隔おいて金属配線板を設け、この金属配
線板を樹脂内に一体的に封止するとともに、前記リード
の端部と前記金属配線板の両端部を、それぞれ同一平面
上に位置する状態に樹脂の各異なる辺から突出させてい
るので、実装基板の配線面積を低減できるとともに、放
熱効果を高めて許容損失を大きくすることができる。ま
た、金属配線板とペレット表面との間隔を、ボンディン
グワイヤのループ高さの管理限界値の上限に設定するこ
とで、ボンディングワイヤのループ高さ異常を容易に判
別することができる効果がある。As described above, according to the present invention, a metal wiring board is provided on a surface side of a pellet at a predetermined interval from a pellet, and the metal wiring board is integrally sealed in a resin, and an end portion of the lead and the metal Since both ends of the wiring board are projected from different sides of the resin so as to be located on the same plane, the wiring area of the mounting board can be reduced, and the heat dissipation effect can be increased to increase the allowable loss. it can. Further, by setting the distance between the metal wiring board and the surface of the pellet to the upper limit of the control limit value of the loop height of the bonding wire, the loop height abnormality of the bonding wire can be easily determined.
さらに、前記のように金属配線板の両端部を、リード
の端部とは異なる辺から突出させることで、実装基板に
形成する配線、特に金属配線板によって半導体装置を貫
通させる配線をリードの端子に接続するための配線から
離すことができ、配線のパターン配置が容易なものにな
るという効果も得られる。Further, as described above, both ends of the metal wiring board are protruded from sides different from the ends of the leads, so that wiring formed on the mounting board, particularly wiring for penetrating the semiconductor device through the metal wiring board, is connected to the terminal of the lead. The wiring pattern can be separated from the wiring for connecting the wiring, and the effect that the wiring pattern can be easily arranged can be obtained.
第１図（ａ）ないし（ｃ）は本発明を絶縁タイプ半導体
装置に適用した実施例の平面図、正面図、側面図、第２
図（ａ）および（ｂ）は第１図の構造を製造する際に用
いられるフレームの平面図、第３図（ａ）ないし（ｃ）
は本発明を非絶縁タイプ半導体装置に適用した実施例の
平面図、正面図、側面図、第４図は第３図の半導体装置
を平面実装した状態を示す平面図、第５図は従来の半導
体装置を平面実装した状態を示す平面図である。 １〜３……リード、1a……素子搭載部、４……ペレッ
ト、５……ボンディングワイヤ、６……金属配線板、７
……樹脂、８……実装基板、９……配線、10……リード
フレーム、11……金属フレーム。FIGS. 1A to 1C are a plan view, a front view, a side view, and a second embodiment of an embodiment in which the present invention is applied to an insulation type semiconductor device.
FIGS. 3 (a) and 3 (b) are plan views of a frame used for manufacturing the structure of FIG. 1, and FIGS. 3 (a) to 3 (c).
FIG. 4 is a plan view, a front view, and a side view of an embodiment in which the present invention is applied to a non-insulated type semiconductor device. FIG. 4 is a plan view showing a state in which the semiconductor device of FIG. 3 is mounted on a plane. FIG. 4 is a plan view showing a state where the semiconductor device is mounted on a plane. 1-3 Leads 1a Element mounting part 4 Pellets 5 Bonding wire 6 Metal wiring board 7
... Resin, 8 mounting board, 9 wiring, 10 lead frame, 11 metal frame.
Claims (1)
レットと他のリードとをボンディングワイヤで電気接続
し、これらを樹脂で封止してなる半導体装置において、
前記ペレットの表面側にペレットと所要間隔おいて金属
配線板を設け、この金属配線板を前記樹脂内に一体的に
封止し、かつ前記リードの端部と前記金属配線板の両端
部を、それぞれ同一平面上に位置する状態でかつ前記樹
脂の各異なる辺から突出させたことを特徴とする半導体
装置。A semiconductor device in which a pellet is mounted on a lead, the pellet is electrically connected to another lead by a bonding wire, and these are sealed with a resin.
A metal wiring board is provided at a predetermined interval from the pellet on the surface side of the pellet, the metal wiring board is integrally sealed in the resin, and the ends of the leads and both ends of the metal wiring board are A semiconductor device, wherein each semiconductor device is located on the same plane and protrudes from each of different sides of the resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33653990A JP2979637B2 (en) | 1990-11-30 | 1990-11-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33653990A JP2979637B2 (en) | 1990-11-30 | 1990-11-30 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04206761A JPH04206761A (en) | 1992-07-28 |
| JP2979637B2 true JP2979637B2 (en) | 1999-11-15 |
Family
ID=18300182
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33653990A Expired - Lifetime JP2979637B2 (en) | 1990-11-30 | 1990-11-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2979637B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2907186B2 (en) * | 1997-05-19 | 1999-06-21 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
-
1990
- 1990-11-30 JP JP33653990A patent/JP2979637B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04206761A (en) | 1992-07-28 |
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