JP2970570B2 - Tone generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a musical tone generator, and more particularly to a musical tone generator that generates musical tones using a storage means such as a memory.

[0002]

2. Description of the Related Art Generally, a musical sound generating device includes a musical information input means such as a keyboard, a control means for generating control parameters such as a musical sound forming instruction in response to information input by the musical information input means. A sound source that forms a musical tone based on the control parameters. Usually, a sound source is composed of a plurality of circuits such as a circuit for generating a musical tone waveform and a circuit for providing an envelope. In the conventional tone generator, storage means for storing a plurality of types of parameters used by each circuit in the sound source is provided, and the plurality of types of parameters are read from the storage means and read out. There is a configuration in which a musical tone signal is generated by supplying the parameters to each circuit.

[0003]

By the way, in such a conventional tone generating apparatus, a plurality of kinds of parameters used for generating a certain tone signal are read out (or continuously) at a time from the storage means. . However,
Since a plurality of circuits in the sound source have different processing timings (in other words, timings requiring parameters), when the parameters are collectively read, each circuit actually needs the parameters. It is necessary to hold these parameters until the timing of performing. Therefore, the conventional musical sound generating apparatus stores a plurality of types of parameters collectively read from the storage means in a latch or the like, and outputs each parameter at the timing when each circuit performs processing.

As described above, the conventional tone generator requires an extra circuit such as a latch to adjust the output timing of each parameter. For this reason, in the case of a sound source having a large number of sounding channels, or when the number and types of parameters supplied to each circuit in the sound source are large, the scale of the circuit becomes large, and the tone generator becomes expensive. There was a problem. The present invention has been made in view of the above circumstances, and does not require an extra circuit such as a latch for adjusting the output timing of a parameter used for tone generation, and has a small circuit size and an inexpensive tone generator. The purpose is to provide.

[0005]

SUMMARY OF THE INVENTION The present invention provides an address
Data that can be read from and written to each storage location specified by
A憶means, storage means includes a storage area Nos. 1 through N corresponding to N sound channels, to memorize a plurality of types of musical tone parameters for each storage area, in response to the sounding instruction, the assign at least one sound channel of the sound channel, of the memory means, assigned to the corresponding storage area in the sound channel, writes the plurality of types of musical tone parameters corresponding to the musical tone to be formed, a generate instruction tone and line intends control unit, every predetermined sampling period, the plurality of types of musical para each sound channel from the storage hand stage
Reading means for sequentially reading out meters and one tone generation method
Multiple series connections for each of the multiple processes
Processing block for each sampling period.
And on the basis of a plurality of types of musical tone parameters of each sound channel read, N pieces row division channel operation when each processing block is N dividing the sampling period, respectively
In addition to performing pipeline operations as a whole ,
Music generating means for generating N musical tones, wherein the storage means comprises:
Is accessed for each of M time slots obtained by dividing M into
The reading means includes:
In the im slot, the plurality of types of tone parameters corresponding to different tone generation channels for each type are shown.
Address generation means for sequentially generating read addresses is provided.
Along with the plurality of processing blocks,
The data read from the storage means according to the read address.
Processing of each processing block among several types of tone parameters
Time slot from which the necessary tone parameters were read
Latch means for latching each sound channel.
The plurality of types of musical tone patterns stored in the storage area corresponding to
Parameters use the corresponding tone parameters
Timing corresponding to the processing timing of each processing block
And latched by the latch means of each processing block.
It is characterized that you are Ji.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. <Structure of Embodiment> (1) Overall Structure FIG. 1 is a block diagram showing the structure of a tone generator according to an embodiment of the present invention. In this figure, reference numeral 1 denotes a control section for controlling each section of the musical sound generating apparatus. Reference numeral 2 denotes a keyboard provided with a large number of keys. Reference numeral 3 denotes a panel switch group, and each switch is turned on / off by operating a corresponding operator provided on a panel surface of the tone generator. Reference numeral 4 denotes a panel display provided on a panel surface of the musical sound generating device, and displays a currently executed function or the like. Reference numeral 5 denotes a sound source section that forms a tone signal in accordance with a tone generation instruction given from the control section 1. The sound source unit 5 is a so-called time-division sound source, and can simultaneously form up to 12 types of tone signals.
The calculation of the waveform value of each tone signal is performed in each sounding channel CHi (i = 0 to 11) obtained by dividing the sampling period Ts, which is the generation interval of the waveform value, into 12 parts. Each time slot Tk (k = 0) obtained by dividing the sound channel into 16
A predetermined process required for calculating the waveform value is executed for each of (15) to (15). FIG. 2 shows a sampling cycle Ts and a sound channel CH.
i (i = 0 to 11) and time slot Tk (k = 0
15) to 15). A parameter ROM 6 stores various tone parameters necessary for the tone generator 5 to form a tone signal. The tone parameters will be described later. The parameter ROM 6 has an address bus ABRO
ROM bus R comprising M and data bus DBROM
It is connected to the sound source unit 5 via OMBUS.

Reference numeral 7 denotes a shared RAM, which is used as a storage means for control data when the CPU 11 (described later) in the control unit 1 controls the tone generator, and is necessary for the sound source unit 5 to form a tone. It is used as a storage means for various musical tone parameters. Here, the tone parameters stored in the shared RAM 7 include, in addition to data used independently by the CPU 11 and the tone generator 5, B. information provided by the CPU 11 to the sound source unit 5, such as sounding instructions, tone color designation information, and the like; It is information indicating the current tone formation state in the tone generator 5 and includes both information that the CPU 11 refers to when controlling the operation of the tone generator. Therefore, the shared RAM 7 not only functions as storage means but also has a CPU
It can be said that it also plays a role as a mutual information transmission means between the sound source unit 11 and the sound source unit 5. The details of the data stored in the shared RAM 7 will be described later. Bus RBUS for RAM is made from the data bus DB _R, address bus AB _R and the read write line _R / W R. These data buses DB _R, the address bus AB _R and the read write line R
/ W _R is connected to the data terminals of the shared RAM 7, the address terminals and read-write terminal. Reference numeral 8 denotes a RAM connection control unit, which includes the CPU 11 in the control unit 1 and the sound source unit 5
And the connection state between the shared RAM 7 and the shared RAM 7 is controlled.
Reference numeral 9 denotes a write detection unit which constantly monitors the data writing operation to the shared RAM 7 via the RAM connection control unit 8 and sets the first parameter (in this embodiment, the voice When the lower-order bit data VnL of the number is written, a signal "1" is output as the load signal LOAD, and the tone generator 5 is instructed to take in parameters relating to musical tones to be formed in the shared RAM. Reference numerals 10L and 10R denote left channel and right channel sound systems, respectively. The left channel tone signal LOUT and right channel tone signal R
OUT is pronounced as a musical tone. A timing signal generator 100 outputs a timing signal for determining the timing of various operations performed in the controller 1, the RAM connection controller 8, and the tone generator 5.

(2) Configuration of the control unit 1 The control unit 1 includes a CPU (central processing unit) 11, a timer 12, a ROM (read only memory) 13, a parallel I
/ O (input / output) interface 14, driver 15, and CPU bus C for interconnecting these components.
It consists of PUB. In the control section 1, the CPU 11 controls each section of the tone generating apparatus based on a control program stored in the ROM 13. The timer 12
The CPU 11 sets timekeeping data via the CPU bus CPUB by the CPU 11 and outputs an interrupt signal to the CPU 11 when a time corresponding to the timekeeping data has elapsed. Keyboard 2
The state of each key and the state of the panel switch group 3 in the parallel I / O interface 14 and the CPU bus C
The data is taken into the CPU 11 via the PUB. The CPU 11 outputs to the CPU bus CPUB information necessary for forming a musical tone, such as tone generation instruction information and tone color designation information, based on the information taken in through the parallel I / O interface 14. Further, the CPU 11 sends display data representing the function or the like currently being executed to the driver 15 and causes the panel display 4 to display the data.

(3) Contents Stored in Parameter ROM 6 FIG. 3 is a memory map showing the contents stored in the parameter ROM 6. The parameter ROM 6 has a storage area having a storage capacity of 16 bits each. Of these storage areas, a series of storage areas starting from the absolute address "0" constitute a timbre data area corresponding to 100 kinds of timbres. In these tone color data areas, tone color data corresponding to voice numbers Vn = “0” to “99” are stored. Then, a series of storage areas after the tone color data area are waveform sample data areas,
In this area, musical sound waveform sample data corresponding to each tone color is stored.

Each tone color data area comprises six storage areas, and relative addresses "0" to "5" are assigned to each of these six storage areas. Here, each tone color data stored in the six storage areas of the tone color data area will be listed. First, the relative address is "0"
The level shift data LS is stored in the upper 8-bit area of the storage area. The lower 8-bit area of the storage area whose relative address is "0" stores the upper 8-bit data SAH of the start address. Next, the middle 8-bit data SAM of the start address is stored in the upper 8-bit area of the storage area whose relative address is "1", and the lower 8-bit data S of the start address is stored in the lower 8-bit area.
AL is stored. These data SAH, SAM
24-bit start address S consisting of SAL and SAL
A designates a storage area in which the leading data of the waveform sample data corresponding to the tone color is stored, and is represented by an absolute address in the parameter ROM 6. Next, data LSH of the upper 8 bits of the loop start address LS is stored in the upper 8 bits area of the storage area whose relative address is “2”, and lower 8 bits of the loop start address LS are stored in the lower 8 bits area. Bit data LSL is stored. The 16-bit loop start address LS composed of these data LSH and LSL is an address for designating the start point of a section in which loop reproduction is performed in the sample data of the waveform corresponding to the tone color, and is relative to the start address SA = SAH + SAM + SAL. Expressed as an address. Next, data LEH of the upper 8 bits of the loop end address is stored in the upper 8 bits area of the storage area whose relative address is “3”, and the lower 8 bits of the loop end address are stored in the lower 8 bits area. Data LEL is stored. The 16-bit loop end address LE composed of these data LEH and LEL is an address for specifying the end point of the section in which loop reproduction is to be performed among the sample data of the waveform corresponding to the tone color, and the loop end address LE
The start address S is the same as the loop start address.
A = SAH + SAM + SAL. FIG. 4 shows the relationship among the start address SA, the loop start address LS, and the loop end address LE. When an instruction to form a musical tone is given, first, sample data is read out from a storage area in the parameter ROM 6 in which an absolute address is specified by a start address SA. Then, after the sample data is read from the storage area whose relative address to the start address SA is LE, the relative address becomes L from the storage area whose relative address is LS.
The sample data of the section up to the storage area E is repeatedly read.

Various modulation control data MS, AMD, and PMD are stored in an upper 8-bit area of a storage area whose relative address is "4" in the timbre data area. Next, the lower 8-bit area of the storage area whose relative address is "4" and the upper 12-bit area of the storage area whose relative address is "5" are used to control the envelope of the musical tone waveform corresponding to the tone color. Data is stored. First, in an area of lower 8 bits of a storage area whose relative address is "4", an attack rate AR for determining a temporal change of an envelope in an attack portion A of a musical sound waveform to be formed, and an attack rate AR in a first decay portion D1. A first decay rate D1R for determining a temporal change of the envelope is stored. Next, in the upper 12-bit area of the storage area whose relative address is "5", the second decay portion D of the tone waveform to be formed is provided.
2, a second decay rate D2R for determining the temporal change of the envelope in the release section R, a release rate RR for determining the temporal change in the envelope in the release section R, and the level of the envelope switching from the first decay section to the second decay section. The reference level DL is stored (see FIG. 5). Next, the key scaling coefficient KS is stored in the lower 4-bit area of the storage area whose relative address is "5".

(4) Information Stored in Shared RAM 7 FIG. 6 is a memory map showing storage areas for various tone parameters set in shared RAM 7. Shared RAM 7
Consists of storage areas each having a storage capacity of 8 bits. Of these storage areas, a series of storage areas starting from the absolute address "0" constitute a sounding data area for storing tone parameters corresponding to each of the 0th to 11th sounding channels. . The series of storage areas after the sound channel data area is the CPU
11 is a work area in which control data used by the memory 11 is stored. Each sound data area is composed of 12 storage areas, and each of these storage areas has relative addresses "0" to "11". Hereinafter, these 12 storage areas will be described.

First, the storage area whose relative address is "0" stores the lower 8 bits of data V of the voice number Vn which specifies the timbre of the musical tone to be generated in the relevant channel.
It is an nL storage area. Next, in the storage area where the relative address is “1”, the upper 6-bit area is the storage area for the lower 6-bit data FnL of the F number Fn that specifies the pitch of the musical tone to be generated in the sounding channel. , The lower 2 bits area is the voice number V
It is a storage area for n upper 2 bits of data VnH. Next, in the storage area whose relative address is "2", the upper 4 bits area is the storage area of the octave data Oct specifying the octave value of the musical tone to be generated, and the lower 4 bits area is the F number Fn. It is a storage area for upper 4 bits of data. Next, in the storage area where the relative address is "3", the upper 2 bits area is the storage area of the note-on flag NON for sound generation instruction, and the subsequent 2 bits area is the amount of depression of the sustain pedal (not shown). Is stored in the storage area of the sustain data SUS, and the remaining lower 4-bit area is the storage area of the sound image position data PAN.

Data VnL, FnL, VnH, Oct, FnH, NO stored in each storage area described above
N, SUS and PAN are output by the CPU 11 and written in the corresponding areas. That is, when any key on the keyboard 1 is pressed, the CPU 11 outputs the data VnL, FnL, VnL, FnL based on the key press event and the operation state of an operator such as a tone operator (not shown).
VnH, Oct, FnH, SUS, and PAN are determined, a sounding channel for sounding in response to a key press event is determined, and the data is written to a sounding data area corresponding to the sounding channel. At this time, "1" is written as the note-on flag NON.
When the key being released is released, the CPU 11 determines the sounding channel that is sounding according to the key, and writes "0" as the note-on flag NON in the sounding channel data area corresponding to the sounding channel. It is.
Next, the storage area whose relative address is "4" is a storage area of the total level data TL. Next, in the storage area whose relative address is “5”, the upper 4 bits are the storage area of the attack rate AR, and the lower 4 bits are the storage area of the first decay rate D1R. Next, in the storage area whose relative address is “6”, the area of the upper 4 bits is the second decay rate D
The 2R storage area and the lower 4 bits are the release rate RR storage areas. Next, in the storage area whose relative address is “7”, the upper 4 bits area is the storage area of the reference level DL, and the lower 4 bits area is the storage area of the key scaling coefficient KS.
Next, the storage area whose relative address is "8" is a storage area for modulation control data MS, AMD, and PMD. Next, in the storage area whose relative address is “9”, the area of the upper 4 bits is an unused area, and the area of the lower 4 bits is the storage area of the shift data LS.

The data TL, AR, D1R, D2R, RR, DL, KS,
MS, AMD, PMD, and LS are output by the sound source unit 5 and written in the corresponding areas. That is, when the voice number Vn is written into one of the sounding data areas by the CPU 11 in response to the occurrence of the key press event as described above, the tone generator 5 causes the parameter ROM 6
From the timbre data TL, AR,
D1R, D2R, RR, DL, KS, MS, AMD, P
The MD and the LS are read out and written in the corresponding areas in the sounding data area. When “0” is written as the note-on flag NON in the sounding channel data area in response to the occurrence of the key release event, the sound source unit 5 writes a large release rate RR in the sounding data area. Next, if the relative address is "1
The storage area “0” is the current envelope data EGD
Of the upper eight bits of the data EGH. Next, the storage area whose relative address is “11” is a storage area for the lower 2 bits of data EGL of the current envelope data EGD, a subsequent 2 bits area is a storage area for the current state data EGS, and a remaining lower 4 bits area. Is an unused area. Here, the current envelope data EGD is data indicating the value of the currently generated envelope in the sound source unit 5, and the current state data EGS is data indicating the state of the currently generated envelope. These data are shared by the tone generator 5
AM7 is written.

(5) Configuration of the tone generator 5 As shown in FIG. 1, the tone generator 5 includes a tone generator 51, a note-on pulse generator 52, a tone generator address generator 53, and a tone generator 51 for forming tone signals of left and right channels. The sound source data bus GEB interconnects these elements. The tone generation unit 51 executes the processing described below for each tone generation channel to form tone signals LOUT and ROUT for the left and right channels corresponding to each tone generation channel. When the load signal LOAD is set to "1" by the write detection unit 9, the sounding channel at that time in the shared RAM 7 (that is, the sounding channel for which the sounding instruction is issued).
The voice number Vn is read from the sounding data area corresponding to. The timbre data is read from the timbre data area corresponding to the voice number Vn read in the processing in the parameter ROM 6 and written into the sound data area corresponding to the sound channel for which the sound is instructed in the shared RAM 7. Also, when reading and writing the tone color data, a load number LN is output. This load number LN
Are sequentially switched from "0" to "5" in six sampling cycles from the point in time when the load signal LOAD becomes "1", are used as relative addresses for reading timbre data from the parameter ROM 6, and are used as parameters. It is used for calculating a relative address when writing the tone color data read from the ROM 6 into the tone generation data area. The load number LN is generated by an address generator 502 (described later) in the musical sound generator 51. The sounding data area of the shared RAM 7 is used as storage means for the value of the envelope, and the envelope value of the musical sound to be sounded is sequentially calculated. In parallel with the above processing, the waveform sample data corresponding to the voice number Vn is sequentially read from the parameter ROM 6, and the waveform sample data is processed in accordance with the tone color data corresponding to the voice number Vn to form musical tone signals LOUT and ROUT. In the following, an operation mode in which the above-described processing is performed is referred to as a load mode, and a mode in which the above-described processing is performed is referred to as a sound generation mode.

The note-on pulse generator 52 is a shared RAM
7, the note-on flag NON of each sounding channel is monitored, and when the value of the note-on flag NON of a certain sounding channel becomes "1", a note-on signal is sent to the musical sound generation unit 51 at a timing corresponding to the sounding channel. NON
S is sent to the tone generator 51.

The sending source address generator 53 in each time slot of each sound channel address ADR _G below into RAM connection control unit 8. However, in the following, i is the number of the sounding channel at the present time. Addresses generated in time slots T ₃ , T ₈ , T ₁₁ and T ₁₄ are write addresses, and addresses generated in other time slots are read addresses. Ax and Ay are relative addresses determined according to the above-mentioned load number LN. When LN = 0, Ax = 9, when LN = 4, Ax = 8, Ay = 5, L
When N = 5, Ax = 6 and Ay = 7. {Each timeslot source address ADR _G in} timeslot _{T 0: 6 (i-1} ) +1 time slot _{T 1: 6 (i-1} ) +2 time slot _{T 2: 6 (i-4} ) +3 timeslot T _{3: 6 (i-3)} + Ax timeslot _{T 4: 6 (i-3} ) +4 time slot _{T 5: 6 (i-3} ) +5 time slot _{T 6: 6 (i-3} ) +6 time slot T _7: 6 (i-3) +7 timeslot _{T 8: 6 (i-3} ) + Ay time slot T _9: 6i + 8 time slots _{T 10: 6 (i-3} ) +9 time slot _{T 11: 6 (i-4} ) +10 time slot _{T 12: 6 (i-3} ) +10 timeslot _{T 13: 6 (i-3} ) +11 timeslot _{T 14: 6 (i-4} ) +11 timeslot T _15: 6i However, expression indicating each address of the Oite, paragraph 1 6
When (ik) is a negative number, 6 (ik + 12) is used instead of 6 (ik) as the arithmetic expression of the first term. The first term in the above equation indicates the head address of the sound data area to which the target data belongs, and the second term indicates the relative address of the target data with respect to the head address. The tone generator address generator 53 generates first and second write control signals GW and GWa necessary for accessing the shared RAM 7,
This is supplied to the AM connection control unit 8. Note that these write control signals will be described later. The sound source data bus GEB is the 0th
To 7th bit lines.

Next, the configuration of the tone generator 51 will be described with reference to FIG.
Latches 701 to 717 each latch data output to a predetermined bit line on sound source data bus GEB in a predetermined time slot. In FIG.
Any symbol of Ti (i = 0 to 15) is written in a frame indicating 01 to 717, and these symbols indicate a time slot in which each latch takes in data from the sound source data bus GEB. . The address register section 501 has a 24-bit storage area for storing a start address SA, a 16-bit storage area for storing a loop start address LS, and a loop end address L.
It has a 16-bit storage area for storing E.

Each of the latches 704 to 706 has a capacity of 8 bits. The latch 704 reads out from the shared RAM ₇ in the time slot T0 and outputs the sound source data bus GEB.
Is latched at the lower bit data VnL of the voice number output to. The lower bit data FnL latch 705 upper bit data VnH (zeroth and second bits) of the voice number that is output in time slot T ₁ in the sound source data bus GEB and F number (second to seventh bits) Latch. The latch 706 latches the upper bit data of the F number to be output in time slot T ₂ to the sound source data bus GEB (0th 3 bits) and octave data Oct (fourth to seventh bits). The operation in which these data are read from the shared RAM 7 and output to the sound source data bus GEB will be described later.

The address generator 502 is a parameter ROM
6 is generated. Here, the manner of address generation performed by the address generation section 502 differs between the load mode and the tone generation mode as described below.
In the load mode (LOAD = "1"), the address generator 502 generates a load number LN and generates an address determined by the load number LN. Here, the address generator 502 has a counter for counting the load number LN for each sounding channel. Load signal LOA in a certain sound channel CHi
When D becomes "1", "0" is set as the initial value of the load number LN in the counter corresponding to the tone generation channel CHi. Thereafter, the sampling cycle switches,
The load number LN is incremented each time the sound channel CHi is used again. The load number LN is sent to the above-mentioned sound source address generator 53 (FIG. 1) and also sent to the address register 501. Address register section 501
The load number LN is used as a control signal for controlling the writing of the start address, loop start address, and loop end address read from the parameter ROM 6. That is, the load number L
When N is “0”, the level shift data LS is read from the parameter ROM 6 as the upper 8 bits, and the upper 8 bits of the start address are read as the lower 8 bits. Therefore, in this case, the ROM data bus D is stored in the storage area corresponding to the upper 8 bits of the start address among the storage areas in the address register 501.
Data on the lower 8 bit lines of the BROM is written. Thereafter, in each case of LN = “1” to “3”, the same control is performed, and the start address, the loop start address, and the loop end address are stored in predetermined storage areas corresponding to each of the address register units 501. Written. In the load mode, the address generator 502 performs an operation of 6Vn + LN using the voice number Vn latched by the latches 704 and 705 and the load number LN at that time, and stores the resulting address in the ROM address bus ABROM. Via the parameter ROM 6. When the load number LN becomes “5”, the address generator 502 sends a load end signal END indicating that the load mode has ended to the write detector 9. The write detection unit 9 returns the load signal LOAD to “0” when the load end signal END is input.

On the other hand, in the tone generation mode (LOAD = "0"), the address generator 502 generates phase information representing the phase of the waveform value of the tone signal to be formed, and determines the phase information based on the integer part of the phase information. The waveform address IA to be sent to the parameter ROM 6 and the decimal part FRAC of the phase information.
To the interpolation unit 505 described later. Here, the phase information is
The F number Fn and the octave data Oct stored in the latches 705 and 706, and a modulation signal generator 50 described later.
4 is obtained by accumulating the pitch information determined based on the frequency modulation data PM output from the sampling cycle 4 every time the sampling period is switched. If the integral part of the phase information exceeds the loop end address LE stored in the address register 501 by accumulation, the result of adding the extra part to the loop start address LS is set as the integral part of the phase information. The control for the loop reproduction described above is performed.

The transfer register 503 includes a parameter ROM
Read data from 6 a register sequentially transferred to the sound source data bus GEB, and transfers the low-order 8 bits of the data of the read data in time slot T _4, and transfers the upper 8 bits of data in time slot T _15. Latch 701 is the sixth and seventh sound source data bus GEB is read from the shared RAM7 at time slot T ₁₀
The data MS output to the bit line is latched. Latch 702 sound source data bus G in the time slot T ₁₀
The data AMD output to the third to fifth bit lines of the EB is latched. Latch 703 latches the data PMD to be output to the third to fifth bit line of the sound source data bus GEB in time slot T _10. Modulation signal generator 504
Is the data M held in these latches 701-703.
Predetermined arithmetic processing is performed on S, AMD, and PMD, and the result is output as an amplitude modulation signal AM and a frequency modulation signal PM. The frequency modulation signal PM is used for generating phase information in the address generator 502 as described above.

An interpolation section 505 performs an interpolation operation on a predetermined number of waveform sample data sequentially output from the parameter ROM 6 to the ROM data bus DBROM in the tone generation mode using an interpolation coefficient determined by a decimal part FRAC of phase information. And outputs the waveform value of the musical tone waveform to be reproduced. Latches 707 to 715 each latch data output to a predetermined bit line on sound source data bus GEB in the illustrated time slot. The envelope generator 600 includes the current envelope data EGD and the current state data EG latched by the latches 707 to 715.
S, total level data TL, attack rate AR,
1st decay rate D1R, 2nd decay rate D2
Based on R, release rate RR, reference level data DL, and key scaling coefficient KS, the state and value of the envelope in the next sampling cycle are calculated, and the calculation results are output as next state data NXTS and next envelope data NXTD. Gate 72
1 outputs the sound source data bus GEB in time slot T ₁₂ the next state data NXTS the envelope generating section 600 outputs. The gate 722 is connected to the next envelope data NX output by the envelope generator 600.
Sound source data bus GE a TD in the time slot T ₉
Output to B. The detailed configuration of the envelope generator 600 will be described later.

The multiplication unit 506 multiplies the waveform value output by the interpolation unit 505 by an envelope waveform value (described later) output by the envelope generation unit 600 and the amplitude modulation data AMD described above. Latch 716 has time slot T ₁₁
Latches the shift data LS read from the shared RAM 7 and output to the 0th to 3rd bit lines of the sound source data bus GEB. Latch 717 has time slot T ₃
Latches the sound image position data PAN output to the 0th to 3rd bit lines of the sound source data bus GEB. The shift unit 507 shifts the level of the signal output from the multiplier 506 according to the shift data LS latched by the latch 716. The PAN control unit 508 outputs the output signal of the shift unit 507 to the sound image position data PA held in the latch 717.
The output is distributed at the ratio determined by N. The accumulating section 509 accumulates the output signal from the PAN control section 508 for all tone generation channels, and outputs the accumulation result as a tone signal corresponding to the left and right channels. A D / A (digital / analog) converter 510 converts the tone signal output from the accumulator 509 into an analog signal, and outputs the tone signals LOUT and ROUT corresponding to the left and right channels to the sound channels 10L and 10R (FIG. 1). Supply.

FIG. 8 is a block diagram showing the configuration of the envelope generator 600. As shown in FIG. The selectors 601 and 602 are both supplied with the current state data EGS as the select signal S, and select and output the input signal of the input terminal specified by the current state data EGS. That is, the selector 60
1 selects and outputs a predetermined value max when the current state data EGS corresponding to the attack unit A is input,
Current state data EGS corresponding to first decay unit D1
Is input, the reference level data DL is selected and output. When the current state data EGS corresponding to the second decay section D2 or the release section R is input, a predetermined value min is selected and output. I do. Here, the values max and min are constants that specify the maximum value and the minimum value of the waveform value of the envelope waveform, respectively. Also, the selector 60
When the current state data EGS corresponding to the attack section A is input, the attack rate AR is selected and output, and the current state data E corresponding to the first decay section D1 is output.
When GS is input, the first decay rate D1R is selected and output. When the current state data EGS corresponding to the second decay section D2 is input, the second decay rate D2R is selected and output. When the current state data EGS corresponding to the release unit R is input, the release rate RR is selected and output.

The comparator 603 compares the output signal of the selector 601 with the current envelope data EGD, and outputs the comparison result as a detection signal OV. Here, the comparator 60
The control of the output of the detection signal OV in 3 is performed based on the current state data EGS. That is, the comparator 603
Is a detection signal O when the current envelope data EGD is equal to or greater than the value of the output signal of the selector 601 when the state indicated by the current state data EGS is the attack section A.
V. If the state indicated by the current state data EGS is the first decay section D1, the second decay section D2 or the release section R, the current envelope data EGD becomes equal to or less than the value of the output signal of the selector 601. The detection signal OV is output. The new state generator 604 outputs the next state data NXTS indicating the state in the next sampling cycle based on the note-on signal NNS, the sustain data SUS, and the detection signal OV. That is, the new state generator 604 outputs the note-on signal NO
When NS rises to “1”, the next state data NXTS corresponding to the attack unit A is output, and thereafter, each time the detection signal OV is output from the comparator 603, the first decay unit D1 and the second decay unit D2 Are sequentially output. In addition, when the note-on signal NNS falls to “0”, the new state generation unit 604 outputs the next state data NXTS corresponding to the release unit R. However, when the sustain data SUS indicating that the sustain pedal is depressed is provided, the release unit R by the new state generation unit 604 is provided.
The output of the next state data NXTS corresponding to the above is prohibited, and the second decay unit is set as the final state of the envelope. Envelope change amount generation section 605 includes selector 60
A key scaling coefficient KS is added to the output signal of No. 2 and the addition result is converted into change amount data designating the change amount of the envelope according to a predetermined conversion formula. Adder 6
06 adds the change amount data to the current envelope data EGD, and outputs the addition result as the next envelope data NXTD. The adder 607 calculates the current envelope data E
The total level data TL is added to the GD, and the result of the addition is supplied to the multiplier 506 as the above-mentioned envelope waveform value.

(6) Configuration of RAM Connection Unit 8 FIG. 9 shows a detailed configuration of the RAM connection control unit 8. In FIG. 9, an address decoder 801 has a CPU bus CPUB.
A circuit for decoding the address output of the address bus AB _P, the contents of the address PADR shared RAM
7 is the address corresponding to the read selection signal RSE.
L is output. The selectors 802 to 804 are supplied with a common select signal SELCPU. Here, the select signal SELCPU is a signal output from the timing signal generator 100. As shown in FIG. 10, the first half period of each time slot is "0" and the second half period is "1". Each of the selectors 802 to 804 selects the input signal of the input terminal A when the select signal SELCPU is “0”, and selects and outputs the input signal of the input terminal B when the select signal SELCPU is “1”.

The input terminal A of the selector 802 has a sound source 5
Of the first write control signal GW output from the sound source address generation unit 53 of FIG. Here, the first write control signal GW becomes “1” in each of the third, eighth, eleventh, and fourteenth time slots as shown in FIG. Also, the selector 802
Is connected to a read / write line R /
It is connected to the W _P. The output signal of the selector 802 is
Is input to the inverter 806 is outputted to the read write line R / W _R of RAM bus RBUS. Selector 8
03 source address ADR _G a sound source address generator 53 is output to the input terminal A is input. Further, to the input terminal B of the selector 803 CPU via the address bus AB _P
11 is input. The output signal of the selector 803 is the address bus AB on the RAM bus RBUS.
Output to _R. The output signal of the 8-bit latch 807 is input to the input terminal A of the selector 804. The latch 807 has a data input terminal connected to the sound source data bus GEB. The second write control signal GWa output from the tone generator address generator 53 is connected to the load terminal of the latch 807.
Is input, and a timing signal generator 1 is connected to a clock terminal.
00 is output. As shown in FIG. 10, the clock φ falls in synchronization with the switching of the time slot, and the second write control signal GWa
It becomes "1" in each of the ninth, twelfth and fifteenth time slots, and becomes "0" in other time slots.
The data output to the data bus DB _G in the tone generator 5 is taken into the latch 807 at the rise of the clock φ in each of the fourth, ninth, twelfth, and fifteenth time slots. On the other hand, the input terminal B of the selector 804 is CP
It is connected to the data bus DB _P in the U bus CPUB. The output signal of the selector 804 is input to the data input terminal of the gate 808. A signal obtained by inverting an output signal of the selector 802 by an inverter 806 is input to an enable terminal of the gate 808. When the output signal of the inverter 806 is “1”, the output signal of the selector 804 is output by the gate 808 to the data bus DB _R of the RAM bus RBUS. In contrast, the inverter 806
Is "0", the gate 808 is in an output disable state (a state in which the output impedance is extremely high).

The buffer 809 supplies a signal output to the data bus DB _R of the RAM bus RBUS to the data input terminal of the gate 810 and the data input terminal of the latch 811. Here, the enable terminal of the gate 810 is AND
The output signal of the gate 812 is input. This AND gate 812 has a read / write line R /
A read selection signal RSEL the read write signal and an address decoder 801 is output provided W _P is input. The output terminal of the gate 810 is connected to the input terminal B of the selector 804 together with the data bus DB _{P of the} CPU bus CPUB.
Connected to. On the other hand, the latch 811 has a clock φ input to a clock terminal and a NOR gate 81 connected to a load terminal.
No. 3 output signal L813 is input. NOR gate 81
3 receives the first write control signal GW and the clock φa. Here, the clock φa is the timing signal generator 1
00 is a timing signal to be output. As shown in FIG. 10, a period of a predetermined time before and after the switching timing of each time slot is “1”, and a period of a predetermined time before and after the rising timing of the clock φ is “0”. ". By receiving such an input signal, NO
As shown in FIG. 10, the output signal L813 of the R gate 813 is the 0th to the 2nd, the 4th to the 7th, the 9th, the 10th, the 12th,
"1" in each of the thirteenth and fifteenth time slots
In each of these time slots, the buffer 8
09 is taken into the latch 811. The output signal of the latch 811 is input to the data input terminal of the gate 814. A signal obtained by inverting the second write control signal GWa by the inverter 815 is input to the enable terminal of the gate 814. The output terminal of the gate 814 is connected to the data input terminal of the latch 807 and the sound source data bus GE.
B.

<Operation of the Embodiment> When the power of the tone generator is turned on, the CPU 11 starts a main routine whose flow is shown in FIG. First, the process proceeds to step S1, where an initial setting process is performed, and an initial value is written to each storage area in the shared RAM 7. Next, the process proceeds to step S2, where key processing corresponding to a key pressing operation or a key releasing operation performed on the keyboard 2 is performed. That is, when any key on the keyboard 1 is pressed, the key-on event is sent to the CPU 11.
Is detected by As a result, the CPU 11 executes a key-on event processing routine whose flow is shown in FIG. 12 as key processing. When any key on the keyboard 2 is released, the key-off event is detected by the CPU 11. As a result, the CPU 11 executes a key-off event processing routine (illustration of a flow is omitted) as key processing. Next, the process proceeds to step S3, in which panel switch processing corresponding to an operation performed on the panel switch group 3 is performed. When step S3 ends, the process returns to step S2. Thereafter, the CPU 11 proceeds to steps S2 and S
Step 3 is repeated.

On the other hand, every time a predetermined time elapses, the timer 12
Outputs a timer interrupt signal to the CPU 11. CP
U11 is interrupted by the supply of the timer interrupt signal, and executes the timer interrupt routine shown in FIG. First, step S2
In step 01, a process for setting the control variable i to “0” is performed. That is, the CPU 11 outputs an address corresponding to the control variable i to the address bus AB _P and outputs data “0” to the data bus DB _P , and further outputs “0” as a read / write signal to the read / write line R / W _P. Is output. As a result, “0” is written in the storage area corresponding to the control variable i of the work area in the shared RAM 7 in the second half reversal period of the time slot at that time. Next, the process proceeds to step S202, and it is determined whether or not the content of the sound channel-specific echo flag TON (i) specified by the control variable i is "0". More specifically,
The CPU 11 sets the echo flag TON (i) for each sounding channel.
Is output to the address bus AB _P and “1” is output to the read / write line R / W _P as a read / write signal. As a result, the content of the sound channel-specific echo flag TON (i) is read from the work area in the shared RAM 7 in the latter half of the time slot at the time. Here, the sounding channel-specific echo flag TON (i) is a flag indicating whether or not to emit an echo sound in the sounding channel i. Is written with "0". This writing process will be described later. Then, the CPU 11 determines whether or not the content of the sound channel-specific echo flag read from the shared RAM 7 in this way is “0”. Step S2
If the determination result of step 02 is "NO", step S20 is performed.
The process proceeds to the second and subsequent processes. If the determination result of step S202 is “YES”, the process proceeds to step S210, where the control variable i stored in the shared RAM 7 is read, and
It is determined whether the read value of the control variable i is smaller than the number "11" of the tone generation channels of the tone generator. If the result of this determination is “YES”, the flow proceeds to step S211 and the control variable i read in step S210
Is added to the storage area of the shared RAM 7 corresponding to the control variable i, and the result of step S202 is added.
Return to Thereafter, the determination in step S202 is performed for the control variable i of “1” to “11”. If the result of the determination is "NO" when proceeding to step S210, that is, if the above-described processing has been completed for all sounding channels CHi (i = 0 to 11), the timer interrupt routine is terminated and interrupted. Restart the process that was being performed.

(1) Key processing. When the player operates a control provided on the panel and inputs a voice number corresponding to the upper key of the keyboard 2, in step S3 of the main routine, a storage area corresponding to the upper key voice number V1 in the shared RAM 7 is obtained. Is input voice number. If a voice number corresponding to the lower key is input, the shared RA
The input voice number is written to the storage area corresponding to the lower key voice number V2 of M7. When the echo switch provided on the panel is operated and the echo switch is turned on, the echo flag EC is stored in the shared RAM 7.
"1" is written as HO, and "0" is written as the echo flag ECHO when the echo switch is turned off.

When the player presses any key on the keyboard 2, a key-on event processing routine is executed as key processing in step S2 of the main routine.
First, in step S101, based on the detected key-on event, the key code of the pressed key and the speed at which the key was pressed are written to the shared RAM 7 as key code data KCD and touch data TD. Next, proceeding to step S102, the current envelope data EGD (= EGH + EGL) corresponding to each sound channel CHi (i = 0 to 11) is sequentially read from each sound data area of the shared RAM 7, and the value of the current envelope data EGD is the lowest. The number i of a certain sound channel is written to the shared RAM 7 as sound assignment channel data AS. Next, the process proceeds to step S103, and in step S101, the shared RAM
7 is the key split point data KSP corresponding to the boundary between the upper key and the lower key.
It is determined whether it is greater than. The result of this determination is “YE
If the answer is "S", the upper key voice number V1 stored in the shared RAM 7 is read out as the voice number Vn of the musical tone to be pronounced (step S104). The voice number V2 is read out as the voice number Vn of the musical tone to be produced (step S
105).

Next, in step S106, octave data Oct and F number Fn are calculated based on the key code data KCD, sound image position data PAN is calculated based on the key code data KCD, and further, based on the touch data TD. Compute total level data TL. Here, if the key code data KCD is a key code of a bass key, sound image position data PAN for localizing the sound image to the left is obtained by calculation, and if the key code data KCD is a key code of a treble key, the sound image is Is obtained on the right side. Also,
The larger the touch data TD, the larger the value of the total level data TL obtained by the calculation. The octave data Oct and F number F are stored in the sound data area corresponding to the sound channel AS in the shared RAM 7.
n (= FnH + FnL), voice number Vn (= VnH +
VnL), total level data TL and sound image position data PAN are written. Further, "1" is written as the note-on flag NON in the sound data area corresponding to the sound channel AS. As a result, the tone generator 5 starts the tone generation process corresponding to the sound channel AS. The tone forming process will be described later.

When the process in step S106 is completed, the process proceeds to step S107, where the echo flag ECHO is read from the work area of the shared RAM 7, and the echo flag EC is read.
It is determined whether or not HO is “1”. If the result of this determination is "YES", the operation proceeds to step S108, in which the sound generation assignment channel data AS is read from the shared RAM 7, and the sound generation channel AS is stored in the work area in the shared RAM 7.
Time count data CNT for each sound channel corresponding to
A predetermined value WT is written as (AS). Also, the shared RA
In the work area in M7, "1" is set as the sound channel-specific echo flag TON (AS) corresponding to the sound channel AS.
Write. Then, the process returns to the main routine. On the other hand, if the decision result in the step S107 is "NO", the process advances to a step S109 to write "0" as a sounding channel-specific echo flag TON (AS) in the work area in the shared RAM 7, and returns to the main routine.

When the player releases the pressed key, the CPU 11 detects the key-off event. As a result, the CPU 11 executes a key-off event processing routine (not shown) as a key processing in step S2 of the main routine. That is, a sounding channel that is performing sounding processing corresponding to the key code in the key-off event is obtained, and “0” is written as a note-on flag NON in a sounding data area in the shared RAM 7 corresponding to the sounding channel. As a result, the sound source unit 5 performs a silencing process (described later) corresponding to the sound channel.

(2) Musical tone formation processing and silence processing Next, the musical tone formation processing performed in the tone generator 5 will be described. When the lower bit data VnL of the voice number Vn is written in the sound channel data area of the shared RAM 7 corresponding to the sound channel AS by the CPU 11 executing step S106 of the key-on event routine, the write operation is performed by the write detector 9. Is detected by Then, the write detector 9 outputs “1” as the load signal LOAD in the sounding channel AS, and the operation mode of the sound source unit 5 in the sounding channel AS is the load mode.

Load Mode In the load mode, parameters are set in the shared RAM 7 for forming a tone using the tone generation channel AS. That is, in the load mode, the tone color data corresponding to the voice number Vn of the musical tone to be emitted is sequentially read from the parameter ROM 6 and sequentially written to the tone generation data area of the shared RAM 7 corresponding to the tone generation channel AS. Shared RA corresponding to this sound channel AS
The write operation to M7 is not performed continuously at a time, but is performed at a timing dispersed on the time axis by using predetermined time slots of a plurality of sampling periods after the key-on time. A time slot in which a write operation corresponding to the sound channel AS is not performed is set to a shared RA corresponding to another sound channel.
Access of M7 is performed. As described above, since the access to the shared RAM 7 corresponding to the sound channel AS is executed at a dispersed timing on the time axis, the shared RAM 7 for the other sound channels is used in parallel with the control related to the sound channel AS. Control can be performed. In the tone generation mode described later, tone color data is sequentially read from the tone generation data area corresponding to the tone generation channel AS of the shared RAM 7, and the tone generation unit 51 performs a tone generation process based on the read data. Also,
Data (current envelope data and state data in the case of the present embodiment) corresponding to the progress of musical tone formation in the shared RAM 7 is sequentially updated. In the load mode, the shared R is applied to the latches 701 to 717 of the tone generator.
Data read from the AM 7 is latched, but these data are not used for tone generation. Hereinafter, the operation in the load mode will be described in detail. FIG. 14 shows the data output to the tone generator data bus GEB by the tone generator 51 and the shared RAM ₇ via the RAM address bus ABR.
Is a time chart showing, for each time slot, an address given to the common RAM 7 and data read from the shared RAM 7 and output to the tone generator data bus GEB. FIG.
4, the lower part of the description column of the data given to the sound source data bus GEB in each time slot has 2D to 4D.
Any symbol of D is attached. These symbols indicate how many channels before the current sounding channel the data is used in the sounding channel. For example, in time slot T _4, it is described as 3D below the data Dy. This indicates that the data Dy is data to be used in the sound channel three channels before the current sound channel. Similarly, the address ADR _R given to the shared _{RAM 7} and the data output from the shared RAM 7 to the tone generator data bus GEB are also used in the tone generation channel which is several channels before the current tone generation channel. Is shown. The address ADR _R given to the shared RAM7, describe the relative address in the pronunciation data area of the data of interest. FIG. 15 is a time chart showing the operation of the sound source unit 5 in the load mode. Hereinafter, the operation in the load mode will be described with reference to these drawings.

When the load signal LOAD is set to "1" and the load mode is started, the load number LN corresponding to the sound channel AS is set to "0" by the address generator 502. When the sound channel AS load number LN is "0", the sound source address generator 53, the address for the sound source at time slot T ₉ ADR _G
Is output as 6AS + 8. This sound source address A
DR _G = 6AS + 8 is, RA in the first half of the time slot T ₉
It is supplied to the shared RAM7 via RAM address bus AB _R by the selector 803 of the M connection control unit 8. As a result, the modulation control data MS, AMD and PM are stored in the storage area corresponding to the relative address "8" in the sounding data area corresponding to the sounding channel AS of the shared RAM 7.
D is read out, and the buffer 809 of the RAM connection control unit 8 is read out.
Is supplied to the data input terminal of the latch 811 via the. These modulation control data MS, AMD and PMD is the clock φ in the time slot T ₉ are latched in the latch 811 by the rising. Here, in the time slot T _9, a gate 814 for "1" as the second write control signal GWa is applied is in the output disable state. Then, at the time slot T _10, the gate 814 becomes the output enable state, the modulation control data MS latched by the latch 811,
AMD and PMD pass through the gate 814 and are output to the sound source data bus GEB. These modulation control data MS, AMD and PMD are latched by the latch 701 to 703 of the tone generator 51 in the time slot T _10. However, in the load mode, these data are not used for tone generation.

[0041] Then comes the time slot T _15, by the sound source address generator 53, 6AS is outputted as a sound source for the address ADR _G. This sound source address ADR _G =
6AS is supplied to the shared RAM7 via the selector 803 of the RAM connection control unit 8 in the first half of the time slot T _15. As a result, the lower bit data VnL of the voice number Vn is read from the storage area corresponding to the relative address “0” in the sounding data area corresponding to the sounding channel AS of the shared RAM 7, and is read out via the buffer 809 of the RAM connection control unit 8. And supplied to the data input terminal of the latch 811. The data VnL is latched by the rising edge of the clock φ in the time slot T ₁₅ to the latch 811. Then, in the time slot T ₀ of the next sound channel AS + 1, sound source data bus GEB latched data VnL the latch 811 passes through the gate 814
At the same time slot T ₀ , and is latched by the latch 704 of the tone generator 51. This data VnL is stored in a parameter ROM together with data VnH described later.
6 is used to generate an address when accessing the address 6.

From the sound channel AS to the sound channel AS +
Switches to 1, at the time slot T ₀ of the sound channel AS + 1, by adding "1" to the load number LN in the current sampling cycle, load number LN to be set when switched to the next sampling period
Is calculated. Also, the sound source address generation unit 53
Based on its number i = AS + 1 pronunciation channel at time 6 (i-1) + 1 = 6AS + 1 becomes source address ADR _G is output. This sound source address ADR _G =
6AS + 1 is shared RA in the first half of the time slot T ₀
M7. As a result, the lower bit data FnL of the F number Fn and the upper bit data VnH of the voice number Vn are read from the storage area corresponding to the relative address "1" in the sound data area corresponding to the sound channel AS of the shared RAM 7, and The clock φ in the slot T ₀ is latched by the latch 811 at the rise. Then, at the next time slot T ₁ , the data FnL and VnH latched by the latch 811 pass through the gate 814 and are output to the tone generator data bus GEB, and are latched by the latch 705 of the musical tone generator 51. Here, the data VnH is used for generating an address when accessing the parameter ROM 6 together with the data VnL described above. In the time slot T _1, the sound source address generator 53, based on the number i = AS + 1 pronunciation channel at that time 6 (i-
1) + 2 = 6AS + 2 becomes source address ADR _G is output. This sound source address ADR _G = 6AS + 2
Are supplied to the shared RAM _{7 in} the first half of the same time slot T ₁ , and the octave data Oct and the F number Fn are obtained from the storage area corresponding to the relative address “2” in the sound data area corresponding to the sound channel AS of the shared RAM 7.
Upper bit data FnH is read in, the latch clock φ in the time slot T ₁ is the rising 8
11 is latched. The data Oct and FnH latched by the latch 811 are stored in the time slot T ₂
, Passes through the gate 814 and is output to the sound source data bus GEB, and is latched by the latch 706 of the musical sound generation unit 51. As described above, in the tone generation channel AS, the modulation control data MS, AMD, and PMD of the tone to be formed in the tone generation channel are read out from the common RAM 7 and latched by the latches 701 to 702 of the tone generation unit 51. Then, in the next tone generation channel AS + 1, the voice number Vn, F number Fn, and octave data Oct of the tone to be formed in the tone generation channel AS are read from the common RAM 7 and latched by the latches 704 to 706 of the tone generation unit 51. .

Next, when the tone generation channel AS + 2 is reached, the address generator 502 generates 16Vn + LN based on the voice number Vn of the musical tone to be formed held in the latches 704 and 705 and the load number LN at that time.
Is output, and the ROM address bus ABR
It is supplied to the parameter ROM 6 via the OM. As a result, when the current load number LN is “0”, the upper 8 bits of the level shift data LS and the start address SA from the storage area whose relative address in the tone data area corresponding to the voice number Vn is “0”. The data SAH is read, and the ROM data bus DBROM is read.
Is output to Data Dx constituting the upper 8 bits of the data consisting of 16 bits in total, ie,
The level shift data LS If is outputted to the sound source data bus GEB by transfer registers 503 in the time slot T _15. Then, by the sound source address generator 53 in the time slot T ₁₅ is "1" as the second write control signals GWa output. Therefore, data LS output to the sound source data bus GEB is latched by the rising edge of the clock φ in the time slot T ₁₅ to the latch 807 of the RAM connection control unit 8. On the other hand, RO
Since the lower 8 bits of the total 16 bits output to the M data bus DBROM, that is, the upper 8 bits data SAH of the start address SA in this case, the load number LN at that time is “0”, The data is written to the corresponding storage area in the address register section 501.

In the time slots T _{0 to} T ₂ of the next tone generation channel AS + 3, since “0” is output as the second write control signal GWa, the latch 807 stores the data LS
Keep holding. Then, at the time slot T _3, by the sound source address generator 53, the relative address corresponding to the load number LN = "0" at that time Ax =
Based on “9” and the sound channel number i = AS + 3, the sound source address ADR _G = 6 (i−3) + Ax = 6AS +
9 is calculated and output. Address ADR _G for this sound source
= 6AS + 9 shared RAM in the first half of the time slot T ₃
7 is supplied. In time slot T ₃ ,
The first write control signal GW becomes "1". As a result, in the first half of the time slot T _3, the inverted signal of the first write control signal GW by the inverter 805 "0"
Is supplied to the shared _{RAM 7} via the selector 802 and the read / write line R / WR, and the output signal “0” of the selector 802 is inverted and supplied to the gate 808,
The gate 808 enters the output enable state. Then, the shift data LS held in the latch 807 is selected by the selector 804, passes through the gate 808, and is written in the storage area corresponding to the relative address “9” in the sound data area of the shared RAM 7 corresponding to the sound channel AS. It is.

[0045] Turning now become the time slot T ₄ of the sound channel AS + 3, the sound source address generator 53, based on the number i = AS + 3 of the sound channel at that time 6 (i-3) + 4 = 6AS + 4 becomes source address A
DR _G is output. This sound source address ADR _G = 6A
S + 4 has a shared RAM _{7 in} the first half of the same time slot T4.
Is read from the storage area of the total level data TL corresponding to the relative address “4” in the sound data area of the shared RAM 7 corresponding to the sound channel AS. The data read from the shared RAM7 is latched in the latch 709 of the tone generator 51 in the time slot T _5. However, the total level data TL latched by the latch 709 is not used for tone generation.

Next, in time slots T ₅ , T ₆ and T ₇ of the sound channel AS + 3, the relative addresses “5”, “6” and “7” of the sound data area corresponding to the sound channel AS of the shared RAM 7 are corresponded. performed data read from the storage area that is in time slot T _6, T ₇ and T _8, read data is latched by the latch 710 to 715. However, these latches 710-715
Are not used for controlling the generation of the envelope, like the data held in the latch 709.
Next, time slots T ₁₀ and T _{12 of the} sound channel AS + 3
In and T _13, pronounce shared RAM7 channel AS
Relative address "9" of the pronunciation data area corresponding to
Data reading from the storage areas corresponding to “10” and “11” is performed, and time slots T ₁₁ , T ₁₃ and T
_{At 14} , the read data is latched 716, 717, 70
7 and 708. However, the data held in these latches 716, 717, 707, and 708 are not used for controlling the generation of musical tones.

Next, when the tone generation channel AS + 4 is reached, the relative address "3" of the tone generation data area corresponding to the tone generation channel AS of the shared RAM ₇ in the time slot T2.
Is read from the storage area corresponding to. However, this read data is also not used for controlling tone generation. The next sounding channel AS + 5 does not access the shared RAM 7 and the parameter ROM 6 corresponding to the sounding channel AS.

Then, the sampling period is switched,
When the sound channel AS comes again, the load number LN becomes “1”. When the load number LN becomes “1”, the latches 704 and 705 are generated by the address generator 502 in the sounding channel AS + 2 of the sampling cycle.
16Vn + L on the basis of the voice number Vn of the musical tone to be formed and the load number LN at that time.
N is output and the ROM address bus AB
It is supplied to the parameter ROM 6 via the ROM. As in this case, when the current load number LN is “1”, the middle 8-bit data of the start address SA is transferred from the storage area whose relative address in the tone color data area corresponding to the voice number Vn is “1”. The SAM and the lower 8-bit data SAL are read and output to the ROM data bus DBROM. These 16-bit data are written to the corresponding storage area in the address register 501 because the load number LN at that time is “1”. When the load number LN is “1”, data is read from the shared RAM 7 in a predetermined time slot of each sounding channel, as in the case where the load number is “0”. However, these read data are not used for controlling tone formation.

Thereafter, when the sampling cycle is switched and the load number LN becomes "2", the latch 7
The upper 8-bit data LSH and the lower 8-bit data LSL of the loop start address LS are read from the tone color data area of the parameter ROM 6 corresponding to the voice number Vn of the musical tone to be formed, which is stored in the address register section 501 and the address register section 501. Are written to the corresponding storage areas. Further, when the sampling cycle is switched and the load number LN becomes "3", the loop end address from the tone color data area of the parameter ROM 6 corresponding to the voice number Vn held in the latches 704 and 705 in the sounding channel AS + 2 in the sampling cycle. The upper 8-bit data LEH and the lower 8-bit data LEL of LE are read and written into the corresponding storage areas of the address register section 501. Thus, the preparation for reading out the waveform sample data in the tone generation process corresponding to the tone generation channel AS is completed. When the load numbers LN are “2” and “3”, data is read from the shared RAM 7 in a predetermined time slot of each sounding channel, as in the case where the load number is “0”. However, these read data are not used for controlling tone formation.

Next, when the sampling cycle is switched and the load number LN becomes "4", the address generator 50 in the sounding channel AS + 2 within the sampling cycle.
2, the voice number Vn held in the latches 704 and 705 and the load number LN =
Based on “4”, an address of 16Vn + LN = 16Vn + 4 is supplied to the parameter ROM 6. As a result,
The modulation control data MS, AMD, and PMD are read as upper 8 bits of data from the storage area corresponding to the relative address “4” of the tone color data area corresponding to the voice number Vn, and the attack rate AR is read as lower 8 bits of data. One decay rate D1R is read. Modulation control data MS, AMD and PMD constituting the upper 8 bits of the data consisting of 16 bits in total.
Is output to the sound source data bus GEB by transfer registers 503 in the time slot T _15, in the time slot T ₁₅ second write control signal GWa is "1"
At the rising edge of the clock φ,
The data is latched by the latch 807 of the M connection control unit 8.

When the time slot T ₃ of the sound channel AS + 3 is reached, the tone generator address generator 53
The relative address Ax = “8” corresponding to the load number LN = “4” at that time and the sounding channel number i = AS
Based on +3, sound source address ADR _G = 6 (i−3)
+ Ax = 6AS + 8 is calculated and output. The source address ADR _G = 6AS + 8 is supplied to the shared RAM7 the first half of the time slot T _3. Further, in the time slot T _3, the first write control signal GW becomes "1". As a result, the modulation control data MS, AMD, and PMD held in the latch 807 are selected by the selector 804, pass through the gate 808, and have the relative address "8" in the sound data area corresponding to the sound channel AS in the shared RAM 7. Is written to the storage area corresponding to.

On the other hand, the attack rate AR and the first decay rate D1R constituting the lower 8 bits of the data consisting of a total of 16 bits read out from the parameter ROM 6 in the sounding channel AS + 2 are generated in the time slot T4 of the sounding channel AS + 3. is output to the data bus GEB, is latched by the latch 807 of the RAM connection control unit 8 at the rising edge of the clock φ in the time slot T _4.

[0053] Then, at the time slot T ₈ of the sound channel AS + 3, the sound source address generator 53,
The relative address Ay = “5” corresponding to the load number LN = “4” at that time and the sounding channel number i = AS
Based on +3, sound source address ADR _G = 6 (i−3)
+ Ay = 6AS + 5 is calculated and output. The sound source address ADR _G = 6AS + 5 is supplied to the shared RAM _{7 in} the first half of the time slot T8. Further, in the time slot T _8, the first write control signal GW becomes "1". As a result, the attack rate AR and the first decay rate D1R held by the latch 807 are changed by the selector 8
04, passed through gate 808, and shared R
The data is written to the storage area corresponding to the relative address "5" of the sound data area corresponding to the sound channel AS of AM7.

Next, when the sampling cycle is switched and the load number LN becomes "5", the address generator 50 in the sounding channel AS + 2 within the sampling cycle.
2, the voice number Vn held in the latches 704 and 705 and the load number LN =
Based on “5”, an address of 16Vn + LN = 16Vn + 5 is supplied to the parameter ROM 6. As a result,
The second decay rate D2R and the release rate RR are read from the storage area corresponding to the relative address “5” of the tone color data area corresponding to the voice number Vn as the upper 8 bits, and the reference level data DL and the lower 8 bits are read as the lower 8 bits. The key scaling coefficient KS is read. Here, the second decay rate D2R and release rate RR is output in time slot T ₁₅ to the sound source data bus GEB, latched in the latch 807 of the RAM connection control unit 8 at the rising edge of the clock φ in the same time slot T ₁₅ You. Then, at the time slot T ₃ of the sound channel AS + 3, the sound source address generator 53, load number LN at that time
= Sound source address A based on relative address Ax = "6" corresponding to "5" and sounding channel number i = AS + 3
DR _G = 6 (i−3) + Ax = 6AS + 6 is calculated and output. The second decay rate D2R and release rate RR is the relative address in the pronunciation data area corresponding to the sound channel AS shared RAM7 in the time slot T _3, which is held in the latch 807 "6"
Is written to the storage area corresponding to.

On the other hand, the reference level data DL read from the parameter ROM 6 in the tone generation channel AS + 2
And the key scaling coefficient KS are the sounding channels AS
+3 sound source data bus GE in the time slot T ₄ of
Is output to the B, the latch 8 of the RAM connection control unit 8 at the rising edge of the clock φ in this time slot T ₄
07. Then, when the time slot T ₈ of the sound channel AS + 3, the sound source address generator 53
Therefore, based on the relative address Ay = “7” corresponding to the load number LN = “5” at that time and the sound channel number i = AS + 3, the sound source address ADR _G = 6
(I-3) + Ay = 6AS + 7 is calculated and output.
Then, the reference level data D held in the latch 807
The L and the key scaling coefficient KS are written in the storage area of the shared RAM 7 corresponding to the relative address “7” of the sound data area corresponding to the sound channel AS. As described above, all the parameters necessary for the tone generation process in the tone generation channel AS have been written into the shared RAM 7 and the registers in the tone generator 51. When the load number LN becomes “5”, the load end signal E
ND is supplied from the address generator 502 to the write detector 9. As a result, the sound detection channel A
The load signal LOAD generated in S is set to “0”, and the load mode ends.

Sound Generation Mode When the load mode ends, the sound generation mode starts.
FIG. 16 is a time chart showing the operation of the sound source unit 5 in the sound generation mode. Hereinafter, the operation in the sound generation mode will be described with reference to FIGS. In the tone generation mode, data is not read from the tone color data area of the parameter ROM 6, and only waveform sample data is read from the parameter ROM 6. When the load mode ends, data necessary for controlling the tone generation is written in all the storage areas of the sound data area of the shared RAM 7 corresponding to the sound channel AS. In the sounding mode, data in these sounding data areas is referred to, and is sequentially updated depending on the type of data, and processing for forming a musical tone is performed.

[0057] First, in the time slot T ₉ of the sound channel AS, shared RAM7 of the sound channel AS to the corresponding modulation control data MS from the storage area corresponding to the relative address "8" pronunciation data area, AMD and P
MD is read out and latched in the latch 701 to 703 of the tone generator 51 in the time slot T _10. Then, the modulation signal generation unit 504 calculates the amplitude modulation data AM and the frequency modulation data PMD of the sounding channel AS in the sampling period. Next, in the time slot T ₁₅ of the sound channel AS, sharing R
From a storage area corresponding to the relative address "0" of the sound data area corresponding to the sound channel AS of AM7 lower bit data VnL voice number Vn is read out in time slot T ₀ of the sound channel AS + 1 tone generator 51 Latched by latch 704. Next, in time slots T ₁ and T ₂ of the sound channel AS + 1,
Each storage area corresponding to the relative address "1" and "2" of the sounding data area corresponding to the sounding channel AS of the shared RAM 7 or the lower bit data FnL of the F number Fn, the upper bit data VnH of the voice number Vn, and the octave data Oct. And upper bit data F of F number Fn
and nH are sequentially read, the time slots T1 and T ₂
Is latched by the latches 705 and 706 of the musical sound generation unit 51 As a result, based on the voice number Vn held in the latches 704 and 705, the parameter ROM
6, the start address SA and the loop start address L from the tone color data area corresponding to the voice number Vn.
S and the loop end address LE are read and written to the address register unit 501. Then, the address generator 502 calculates the increment of the phase information based on the F number Fn and the octave data Oct latched by the latches 705 and 706 and the frequency modulation data PMD, and calculates the sounding channel A at that time.
It is accumulated to the phase information corresponding to S. Then, the phase information and the start address S
A, the address IA of the waveform sample data to be read from the parameter ROM 6 is calculated based on A, the loop start address LS, and the loop end address LE.

The sound channels AS + 1 and AS
At +2, a predetermined number of waveform sample data including the waveform sample data corresponding to the address IA is read from the parameter ROM 6, and the interpolation unit 505 outputs the decimal number of the phase information output from the address generation unit 502 to these waveform sample data. An interpolation operation using an interpolation coefficient corresponding to the section FRAC is performed, and a waveform value of a musical tone corresponding to the sound channel AS in the sampling period is obtained.

Next, when the tone generation channel AS + 3 is reached, in the time slots T _{4 to} T ₇ , the total from the respective storage areas corresponding to the relative addresses “4” to “7” of the tone generation data area corresponding to the tone generation channel AS of the shared RAM 7 is obtained. level data TL, the attack rate AR, first decay rate D1R, second decay rate D2R, release rate RR, reference level data DL and key scaling factor KS is read, the tone generator 51 in time slot T ₅ through T ₈ Latches 709 to 715. Next, in time slots T ₁₀ , T ₁₂ and T ₁₃ , the shift data LS and the current envelope data from the respective storage areas corresponding to the relative addresses “9” to “11” of the sounding data area corresponding to the sounding channel AS of the shared RAM 7 are read. Upper bit data EGH and lower bit data EG
L and the current state data EGS are read out, and in the time slots T ₁₁ , T ₁₃ and T ₁₄ , the tone generator 51
Latches 716, 707, and 708 of FIG.
In the envelope generator 600, the latch 707
The total level data TL, the attack rate AR, the first decay rate D1R, the second decay rate D2R, the release rate RR, the reference level data DL, the key scaling coefficient KS, the current envelope data EG (= EGH + EGL) and the current The calculation of the next state data NXTS and the next envelope data NXTD is started based on the state data EGS. Also,
The current envelope data EGD and the total level data TL are added by the adder 607 of the envelope generator 600, and the amplitude output by the modulator 504 to the waveform value interpolated by the interpolator 505 by the multiplier 506. The modulated data AM is multiplied by the output signal of the adder 607 in the envelope generator 600.

Next, when the tone generation channel AS + 4 is reached, the relative address “3” of the tone generation data area corresponding to the tone generation channel AS of the shared RAM ₇ in the time slot T ₂ .
Is read out from the storage area corresponding to .sqn., The note-on flag NON, the sustain data SUS, and the sound image position data PAN. Then, the sound image position data PAN in timeslot T ₃ is latched by the latch 717 of the tone generator 51. The note-on flag NON is sent to the note-on pulse generator 52, and the note-on flag NON
Is "1", "1" is output as the note-on signal NONS corresponding to the tone generation channel AS.
Sustain data SUS and note-on signal NNS
Is supplied to the envelope generating section 600 and used together with other parameters for calculating the next state data NXTS and the next envelope data NXTD. Now it becomes the time slot T ₉ of the sound channel AS + 4, the gate 72
2 is in an output enable state. At this point, the next state data NX in the envelope generator 600
The calculation of the TS and the next envelope data NXTD has been completed. Then, at time slot T _9, the upper bit data of the next envelope data NXTD passes through the gate 722 is supplied to the data input of latch 807 of RAM connection control unit 8. And time slot T
_{In 9} , the second write signal GWa is set to “1”, so that the upper bit data of the next envelope data NXTD is latched by the latch 807 at the rise of the clock φ. Then, at the time slot T _11, by the sound source address generator 53, a sound source address AD based on the number i = AS + 4 pronunciation channel at that time
R _G = 6 (i−4) + 10 = 6AS + 10 is calculated,
It is provided to the common RAM 7. Further, the first write control signal GW is set to “1” by the sound source address generator 53. Accordingly, the upper bit data of the next envelope data NXTD held in the latch 807, in the time slot T _9, is written to the storage area corresponding to the relative address "10" of the sound data area corresponding to the sound channel AS shared RAM7 .

[0061] Turning now become the time slot T ₁₂ of the sound channel AS + 4, the gate 721 is the output enable state. As a result, the lower bit data of the next envelope data NXTD and the next state data NXTS output from the envelope generator 600 are supplied to the data input terminal of the latch 807 of the RAM connection controller 8. Then, in time slot T _12, since the second write signal GWa is set to "1", the lower bit data and next state data NXTS follows envelope data NXTD is latched in the latch 807 by the rising edge of the clock phi. Then, at the time slot T _14, by the sound source address generator 53, the address for the sound source based on the number i = AS + 4 pronunciation channel at that time ADR _G =
6 (i-4) + 11 = 6AS + 11 is calculated, and the shared R
AM7. Further, the first write control signal GW is set to “1” by the sound source address generator 53. Therefore, the next envelope data N held in the latch 807
Lower bit data of XTD and next state data NX
TS, in the time slot T _14, written to the storage area corresponding to the relative address "11" of the sound data area corresponding to the sound channel AS shared RAM 7.
Then, in the sounding channel AS + 4, the shift unit 50
7, the shift data LS held by the latch 716
, A shift process is performed on the output signal of the multiplier 506. Next, the PAN control unit 508 distributes the output signal of the shift unit 507 to signals corresponding to the left and right channels based on the sound image position control data PAN held by the latch 716. The output signal of the PAN control unit 508 is accumulated by the accumulating unit 509 for all sounding channels in the sampling period, and is output as digital musical tone signals LOUT and ROUT corresponding to the left and right channels in the sampling period.

In each of the subsequent sampling periods, the same processing as described above is performed. That is, the generation of the envelope will be described. In the sounding channel AS + 3 of each sampling period, the current envelope data EGD and the current state data EGS corresponding to the sounding channel AS are read from the shared RAM 7 and supplied to the tone generator 5. Then, the next envelope data NXTD and the next state data NXTS are output by the envelope generating section 600 of the sound source section 5 based on the current envelope data EGD and the current state data EGS. These next envelope data NXTD and next state data NXTS are stored in the shared RAM 7 in the sounding channel AS + 4.
, And these data are read out as the current envelope data EGD and the current state data EGS in the next sampling period. Thus shared RA
M7 is used as a storage unit for musical tone parameters, and musical tones are sequentially formed.

Next, the silencing process performed in the sound source unit 5 will be described. It is assumed that the key release event of the keyboard 2 is detected, the CPU 11 executes step S2 of the main routine, and sets the note-on flag NON in the sound data area of a certain sound channel to “0” in response to the key release event. The change of the note-on flag NON is used as the note-on pulse generation unit 5
2 and the note-on signal NNS corresponding to the sounding channel is set to "0". As a result, the new state generation unit 604 in the envelope generation unit 600 causes the next state data NX corresponding to the sounding channel to be generated.
Data corresponding to the release section R is output as TS,
Thereafter, in the envelope generating section 600, an envelope release section R corresponding to the sounding channel is formed.

(3) Generation of echo sound When the echo switch provided on the operation panel is turned on, "1" is set to the echo flag ECHO in step S3 of the main routine. In this case, the key on the keyboard 2 is pressed by the player,
When the key-on event processing routine is executed by U11, the result of the determination in step S107 is "Yes".
And step S108 is executed. In this step S108, the CPU 11 stores, in the shared RAM 7, the channel-specific count data CNT (A) corresponding to the sounding channel AS (sounding channel for performing sounding processing corresponding to the key press event determined in step S102).
A predetermined value WT is written as S) and the sounding channel A
“1” is written as the per-channel echo flag TON (AS) corresponding to S.

When a timer interrupt signal is given from the timer 12, the CPU 11 starts a timer interrupt routine. First, the process proceeds to step S201, and the control variable i is set to “0” as described above. Next, step S2
In step 02, the CPU reads the sound channel-specific echo flag TON (i) specified by the control variable i from the shared RAM 7, and determines whether or not the content is "0". If a key press operation is performed while the echo flag ECHO is "1", a sound generation process corresponding to a key press event is being performed in any of the sound generation channels AS. In addition, the sound channel-specific echo flag TON (m) corresponding to the sound channel that is sounding, for example, the sound channel m, is “1”. Then, during the execution of the timer interrupt routine, if the value of the control variable i coincides with the number AS of the sounding channel performing sounding processing, step S20
The determination result of Step 2 is “NO”, and the process proceeds to Step S203. Next, proceeding to step S203, the sound channel i
(= M) Count data CN for each sounding channel corresponding to
T (i) is read from the common RAM 7 and decremented, and the result is counted data CNT for each sounding channel
Write to the shared RAM 7 as (i). Next, step S
In step 204, it is determined whether or not the count data CNT (i) for each sounding channel has become “0” by executing step S203. If the result of this determination is "No", the operation proceeds to step S210. If i <11, i is incremented (step S211), and the process returns to step S202.

Thereafter, each time the timer interrupt routine is executed, the tone generation channel m for which tone generation processing is being performed is performed.
Count data CNT (m) for each sound channel corresponding to
Is decremented. And CNT (m) = “1”
After that, when the CPU 11 executes the timer interrupt routine, when i = AS, step S20
The result of the determination at step 4 is “Yes” and the operation proceeds to step S205. The corresponding sound channel-specific echo flag T
The numbers of sounding channels whose ON (i) are "0", that is, sounding channels not used for sounding of the echo sound are all obtained, and the current envelope data EG is determined from among them.
The number of the sounding channel with the lowest D is selected and written into the shared RAM 7 as the sounding assigned channel number AS.
Next, in step S207, the total level data TL is read from the sound data area corresponding to the i-th channel of the shared RAM 7, and a predetermined attenuation coefficient D is added to the read data.
And writes the multiplication result as the total level data TL in the sounding data area of the shared RAM 7 corresponding to the AS channel. Next, proceeding to step S207, the shared R
Octave data Oct, F number Fn, voice number Vn from the sounding data area corresponding to the i-th channel of AM7
Then, the sound image position control data PAN is read out, and the read out data is written to the corresponding storage area in the sounding data area corresponding to the AS channel of the shared RAM 7. Next, in step S208, "1" is written as the note-on flag NON in the sound data area corresponding to the sound channel AS in the shared RAM 7. As a result, a musical sound waveform generated in the sound channel m is attenuated based on the attenuation coefficient D, thereby forming a musical sound waveform in the sound channel AS. Next, in step S209, predetermined values WT and "1" are written in the shared RAM 7 as the count data CNT (AS) for each sound channel and the echo flag TON (AS) for each sound channel corresponding to the sound channel AS, and sound is generated. "0" is written as the sound flag TON (i) for each sounding channel corresponding to the channel i. Next, proceeding to step S210, i
It is determined whether or not <11. If the determination result is “Yes”, i is incremented (step S211),
It returns to step S202.

As a result of performing the above processing, FIG.
As shown in (2), echo sounds are generated at time intervals corresponding to the predetermined value WT, and the maximum value of the envelope of each echo sound attenuates as time elapses as shown by a broken line. The rate of the temporal change of the maximum value of the envelope of each echo sound is determined by the attenuation coefficient D used in step S205 of the timer interrupt routine.

[0068]

As described above, according to the present invention, each time-division channel of the sampling period is further divided by M minutes.
Each of the M divided time slots has a different
Multiple tone parameters corresponding to different sounding channels
Are sequentially generated and pipeline operation is performed.
A plurality of processing blocks that generate musical tones in
Multiple types of music that are read from the storage means according to the dress
Of the sound parameters, the ease required for the processing of each processing block
At the time slot from which the sound parameter was read,
The parameter is latched by the latch means. This
Therefore, the output timing of the tone parameters read from the storage means can be set to a different time-division channel period for each tone parameter type. Can be read from the storage means. Therefore, it is possible to omit a latch or the like for adjusting the output timing of each musical tone parameter, and it is possible to realize an inexpensive musical tone generator with a small circuit size.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a musical sound generating device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a relationship between a sampling period, a sound channel, and a time slot in the embodiment.

FIG. 3 is a memory map illustrating a storage area in a parameter ROM 6 in the embodiment.

FIG. 4 is a diagram illustrating loop reproduction performed in the embodiment.

FIG. 5 is a diagram illustrating an example of an envelope waveform.

FIG. 6 is a memory map illustrating a storage area of a shared RAM 7 in the embodiment.

FIG. 7 is a block diagram showing a configuration of a musical sound generation unit 51 in the embodiment.

FIG. 8 shows an envelope generator 60 according to the embodiment.
FIG. 3 is a block diagram showing a configuration of a 0.

FIG. 9 is a block diagram illustrating a configuration of a RAM connection control unit 8 according to the same embodiment.

FIG. 10 is a time chart showing waveforms of various control signals supplied to the RAM connection control unit 8;

FIG. 11 is a flowchart showing an operation of the CPU 11 in the embodiment.

FIG. 12 is a flowchart showing the operation of the CPU 11 in the embodiment.

FIG. 13 is a flowchart showing the operation of the CPU 11 in the embodiment.

FIG. 14 is a time chart showing the operation of the embodiment.

FIG. 15 is a time chart showing the operation of the embodiment.

FIG. 16 is a time chart showing the operation of the embodiment.

FIG. 17 is a diagram showing an envelope waveform of an echo sound generated in the embodiment.

[Explanation of symbols]

1 ... Control unit, 11 ... CPU, 5 ... Sound source unit, 7 ...
Shared RAM.

Claims (1)

(57) [Claims] 1. A method according to claim 1, wherein each storage location is specified by an address.
Data A writable storage means, comprising a first, corresponding to N sound channel storage areas of the N, each
Storage means for memorize a plurality of types of musical tone parameter in the storage area, in response to the sounding instruction, the allocation of at least one sound channel of the sound channel, said storage means, allocated the corresponding stored sound channel in the region, writes a plurality of types of musical tone parameters corresponding to the musical tone to be formed, a row intends control means generate instructions tone for each predetermined sampling period, the sound from the storage hand stage
Sequentially read out the plurality of types of tone parameters of the channel
In charge of readout means and multiple processes for one tone generation method
And a plurality of processing blocks connected in series.
At each sampling cycle , each processing block is processed based on the read out plural types of tone parameters of each sounding channel.
In addition to performing N time-division channel operations obtained by dividing the sampling period by N , the pipeline as a whole is performed.
Performing down operation, a musical tone generating apparatus having a musical tone forming means for generating N tone, and said storage means, each of said time-division channels to M divided M
, And the reading means accesses each of the M time slots in each time division channel.
In the im slot, the plurality of types of tone parameters corresponding to different tone generation channels for each type are shown.
Address generation means for sequentially generating read addresses is provided.
And the plurality of processing blocks respectively include the read address.
Multiple types of music read from the storage means in accordance with the
Of the sound parameters, the ease required for the processing of each processing block
Latch at the time slot where the sound parameter was read
Latch means for storing the plurality of data stored in the storage area corresponding to each sounding channel.
Several tone parameters are respectively assigned to the tone parameters.
Supports processing timing of each processing block that uses data
At the timing of the
Musical tone generating apparatus according to claim and this latched by the pitch means.