JP2968288B2 - Central processing unit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a central processing unit.

[Prior art] Conventionally, a programmable logic array (PLA)
) To achieve the desired logic,
Multi-stage logic circuits have been used as means for minimizing the number of product terms. A multi-stage logic circuit means that one PLA is basically formed by a two-stage logic circuit of an AND-OR circuit, and the output signal of the OR circuit is fed back to the AND circuit on the input side, and the PLA is synthesized. This is a circuit configured by combining PLAs in series and parallel. In particular, when instruction decoding is performed by a central processing unit (hereinafter abbreviated as CPU) by PLA, the above-described multi-stage logic circuit is used to process a complicated instruction system, or a large one having a large number of product terms is used. The technique of decoding with PLA was taken.

[Problems to be solved by the invention] However, when using a large PLA with a large number of product terms,
In order to reduce the number of product terms, there is a problem that a so-called convolution operation of logic involving complicated operations is required. The convolution is a method in which the input line of the PLA is divided into right and left, and the product term line is exchanged to remove unnecessary input lines, thereby minimizing the constituent parts of the PLA.

If such a convolution is performed, the area occupied by the PLA may be reduced, but in the case of a CPU, an instruction register for storing instruction information supplied to the PLA for the convolution or the stored instruction There is a case where a timing control circuit that controls the timing of transmitting information to the PLA is divided and arranged. In such a case, interconnections are required between each divided instruction register and timing control circuit, and even if the PLA main unit becomes smaller, these peripheral components become complicated and conversely the CPU area becomes larger. There is a problem that. Furthermore, the convolution operation is originally complicated, and when the number of product terms is large, the amount of operation becomes enormous. Also minimized in this way
If you want to change the logic of the PLA, there is also the disadvantage that it is difficult to make subsequent changes because the convolution is complicated. or,
The load in the AND plane of the signal sent from the instruction register or the timing control circuit to the AND plane is different due to convolution, and the decoding speed is different for each instruction information, so that it is difficult to guarantee the operation speed.

In addition, when a multi-stage logic circuit is used, there is a problem that a delay occurs at the time of decoding because a plurality of PLAs are connected.

The present invention has been made in order to solve such a problem, and a high-speed operation is possible and a CPU occupying a small area of the PLA is used.
The purpose is to provide.

[Means for Solving the Problem and Action Thereof] The present invention has a configuration provided with a PLA in which an AND plane is divided into a plurality of parts and each of the divided AND planes is connected to the same one OR plane.

The fact that a plurality of AND planes share one OR plane has the effect of reducing the number of signal passage stages and increasing the decoding speed of instruction information as compared with configuring a multi-stage logic circuit.

Further, according to the present invention, in a central processing unit having an instruction system in which information relating to addressing for designating an address of a data storage destination and information relating to an operation are divided, the information relating to the addressing is separated from the information relating to an operation. A first AND plane to which an information signal related to addressing transmitted by the separating unit is supplied; a second AND plane to which an information signal related to operation transmitted by the separating unit is supplied; One OR plane to which the signals transmitted by the first and second AND planes are supplied, and the timing of transmitting the addressing-related information signal and the computation-related information signal to the first and second AND planes And a PLA having one timing control unit.

Dividing the AND plane into, for example, the first and second two planes allows each AND plane to execute an independent function, so that the instruction information relating to the addressing and the instruction information relating to the operation are complicatedly combined. This eliminates the necessity, simplifies the instruction system, facilitates folding work in the AND plane, and works to reduce the element area of the AND plane. In addition, since the instruction information relating to the addressing and the instruction information relating to the operation are not combined in a complicated manner, the instruction information functions to increase the so-called orthogonality. Further, since a single timing control unit controls a plurality of AND planes, it works to reduce the element area of the entire CPU.

[Embodiment] First, an outline of a configuration in an embodiment of a central processing unit of the present invention will be described below with reference to FIG. 3 to FIG.

FIG. 4 shows a programming model in which the basic word length of this central processing unit (hereinafter referred to as CPU) is 8 bits.

When accessing a program, the address space of the program counter (hereinafter referred to as PC) is 24 bits (PBC, PC
H, PCL), making it possible to access 16 Mbytes with linear addresses. PBC is a program, bank counter register (hereinafter referred to as PBC), PCH is a program counter register H (hereinafter referred to as PCH), PCL
Is a program counter register L (hereinafter referred to as PCL).

On the other hand, when accessing data, a bank method is used, and as a bank address, a data bank register (hereinafter, referred to as DBR (8 bits)) is basically output, and therefore, 256 banks of 64 Kbytes linear are used. Use, 16
M-byte access is enabled.

The output of the DBR as the bank address will be described later with reference to the M1 and M0 flags.

There are a plurality of general-purpose registers (W0 to W3: 16 bits). In particular, both registers W0 and W1 are separated every 8 bits and can be used as 8-bit registers R0, R1, R2, and R3.

Therefore, in the present CPU, it is possible to discriminate and handle both data of 8 bits and 16 bits as the data size of the operation by the instruction.

Furthermore, as a stack space, a 16-bit register is prepared as a stack pointer register (hereinafter, referred to as SP), and accesses 64K bytes linearly.
However, the bank address is fixed to “00” h.

The program status register (hereinafter, referred to as PSR) indicates the current operation state of the CPU. Specifically, each flag of N, V, Z, and C changes according to the result of the operation.
The I flag indicates whether an interrupt request can be accepted, and the D flag relates to correction of the result of the addition / subtraction instruction. If D = 1, the execution result of the addition / subtraction instruction is automatically corrected to decimal.

The M1 and M0 flags are flags that enable selection of a bank address to be output when accessing the data space. Therefore, by setting the M1 and M0 flags to an arbitrary value (in this CPU, updating with an instruction), the bank address to be output at the time of data access can be set to a DBR value or a constant such as “00” h. Is selected and output to correspond to various memory applications.

The first page register (hereinafter referred to as FPR) is a register that serves as an address pointer when accessing data.
Used in an addressing mode called First Direct. Note that addressing refers to designating an address of a data storage destination.

In this addressing mode, only 8-bit data is fetched as operand data, the data is set to the low (bit 7 to bit 0) of the effective address, and the high (bit 15 to bit 8) is set to the FPR content. This register is valid in

However, at this time, the output bank address is M
According to the flag state of 1, M0.

In this addressing mode, since only one byte of operand data is fetched, high-speed data access within the same page address (bits 15 to 8 of the address are constant) is possible.

FIG. 5 shows the instruction format of this CPU. This CPU has a basic word length of 8 bits as described above, and fetches 1-byte data for instruction extension called a pre-byte before an operation code. Take the form

Basically, the pre-byte data has information relating to the addressing mode, and has the contents of the instruction to be executed by the operation code.

However, in the case of frequently used instructions, in order to reduce the instruction code length and execution time, addressing and instruction contents are included in an opcode without pre-byte called a shortened instruction, as shown in “Format 1”. Prepare an instruction.

Further, the operand data has two types of arrangement formats. "Format 2" in FIG. 5 is a format in which an opcode is arranged after a pre-byte, and then operand data is arranged. In "format 3", operand data is also arranged between a pre-byte and an opcode.

In particular, operand data between the format 3 pre-byte and the opcode is used in the addressing with displacement.

Here, addressing with displacement means that when an effective address for data access is generated, the data fetched by the operand or the value of the register specified by the operand is added as an offset to the internal register data. Indicates addressing that generates an address.

When this addressing mode is used, if operand data arrangement format such as format 2 is adopted, it takes time to calculate the effective address after fetching the displacement operand data, and After fetching the displacement data, there will be multiple idle cycles.

However, if the displacement data is arranged between the pre-byte and the opcode using the format 3 arrangement at this time, the calculation for generating the effective address can be performed in an overlapping manner with the fetch cycle of the opcode, resulting in a wasteful idle operation. Prevent cycles from occurring.

FIG. 3 is a block diagram showing the configuration of the CPU. The CPU is mainly divided into two functional units, namely, a control unit 1 and a calculation unit 2.

First, the control unit 1 has a function of controlling execution of an instruction.

The operation is as follows. When an instruction is executed, the instruction code input to DIL15 from the outside via the data bus (D7-D0) is stored in each instruction register of the pre-byte IR3 or the operation code IR4 until the next instruction is generated. Will be retained.

A plurality of outputs 5 and 6 of these instruction registers and a TCU for controlling the timing of the instruction sequence.
Instruction decode circuit whose output is composed of AND-OR PLA
It is input to 8, 9, 10, and 11, and outputs a decoding result 13 according to the instruction and the timing.

Further, the decoded result generates a plurality of control signals 14 for controlling the arithmetic unit 2 by adjusting the timing for the arithmetic unit 2 via an interface circuit called ECI12.

However, in this CPU, the configuration of the PLA has two types of AND planes, one for pre-byte (component 8) and the other for opcode (component 10), and the OR planes 9 and 11 are shared.

This is because, as described in the instruction format above, the pre-byte part has addressing mode information, and the opcode part contains the operation contents of the instruction. Minimization of PL by function (pre-byte or opcode)
A (especially, an AND plane) is realized.

Then, the AND planes 8 and 10 of the two divided PLAs are
With the input signal 24 from the interrupt control 21, both the AND planes can be activated or the AND plane 10 can be deactivated. Here, the control code of the interrupt sequence is all AND
A code is allocated to the plane 8, and the AND plane 10 on the operation code side is in a non-operation state at the time of processing an interrupt.

The calculation unit 2 performs calculation and CP in accordance with the control signal.
U Access data with the outside.

The internal bus has three basic types of 8-bit buses, MB, DB, and SB, and exchanges data with each functional unit.

The function is to perform operations on registers and data and execution addresses shown in the above-mentioned programming model.
Bit ALU19 and 8-bit shifter 2 for performing shift operation
There is an ACU 13 that mainly performs address generation.

The ALU 19 has an IC 27 on the MB input side. The IC 27 can pass through or invert the signal input from the MB bus,
Generates constant data such as 0 "h to assist the calculation in ALU19.

Further, the ALU 19 includes a decimal correction circuit for realizing the function of the D flag.

And ZDT1 which detects zero of data of internal bus (MB)
There is also a BRDT18 that detects whether a branch condition is satisfied by a branch instruction 7 or from a PSR state.

Especially for the ACU that mainly generates addresses,
The function is separated in units of bits, and each has a configuration in which carry is propagated, and performs address operation of up to 24 bits. Here, not only an address operation but also a data operation is possible.

Specifically, the ACU has an increment / decrement function called INC / DEC every 8 bits, and internal buses ABL, ABH and SB (8 bits each)
From "00" h, "01" h, and "02" h.

The result calculated by INC / DEC is selectively stored in the latches of CALL, CALH, and CALB, and output via the address buffers of AOBL, AOBH, and AOBB.

Here, “selective” means that the operation result is not always latched, but may be latched only at the time of address operation and not latched at the time of data operation.

However, the RLT 235 is a data latch that always latches the result during the INC / DEC: B operation.

The ACU also has a VECL, VECH, VECB (vector address generation circuit) that forcibly generates an interrupt vector when an interrupt occurs, and a BS that outputs DB bus data directly as an address without going through INC / DEC. I have.

In this CPU, the generation of the effective address depends on the AU, especially in addressing with branching and displacement.
Calculations are performed using both ACUs. CSB, CSH25, 26
Used at that time.

In other words, the CSB, CSH25, and CS26 have a function as a carry selector for reflecting the carry or borrow based on the operation result from the ALU 19 in the ACU operation.

The calculation result latched from INC / DEC is SB, ABH, AB
The PC, DBR, TR, ADH, and ADL register data are selectively updated via the L bus.

Other functions include a clock generator 22 that controls the clock of the CPU and a system control 23 that generates a plurality of signals that notify the peripheral system of the operating state of the CPU.
There is.

Further, the instruction pre-decoder 33 performs pre-decoding of the instruction code to identify a shortened instruction and to select an illegal combination with an operation code with a pre-byte (hereinafter referred to as an illegal instruction).

Hereinafter, each functional unit of the arithmetic unit 2 of the CPU will be described.

○ General-purpose registers A general-purpose register group shown in FIGS. 3 and 4 for providing data at the time of operation and transfer and for storing results after the operation and transfer.

For W0 and W1, R0, R2, R1, R3
The 8-bit register can be used by discriminating between instructions, so that this CPU can handle not only 16-bit data but also 8-bit data.

W2 and W3 can also be used if they are specified in the addressing mode as pointers for data access.

Each register of the general-purpose register group is configured by a latch (no set or reset), and has the following connection relationship with the internal bus.

Basically, it latches data input from the MB bus and
Alternatively, the latched data is output to the MB bus.

Only the R2 register allows the DB bus to be selected as input for executing the division instruction.

R0 (W0L) → input from MB, output to DB or MB R2 (W0H) → input from MB or DB, output to DB or MB R1 (W1L) → input from MB, output to DB or MB R3 (W1H) → MB W2L → Input from MB, Output to DB or MB W2H → Input from MB, Output to DB or MB W3L → Input from MB, Output to DB or MB W3H → Input from MB, DB or MB FPR (first page register) The FPR shown in FIGS. 3 and 4 is used in an addressing mode referred to as the above-mentioned first direct addressing.

The FPR is configured with a latch (no set or reset), and has the following connection relationship with the internal bus.

Basically, it latches data input from the MB bus and
The data latched on the bus is output.

FPR → input from MB, output to DB ○ IC (input control related to ALU) IC27 (8 bits) shown in Fig. 3
Controls the data input to 9. Functionally, it has the following functions.

1. MB bus data → input to ALU 2. Inversion of MB bus data → input to ALU 3. “00” h constant → input to ALU (ignore MB bus data) 4. “01” h constant → Input to ALU (ignore MB bus data.) 5. Constant of “02” h → Input to ALU (ignore MB bus data.) 6. Constant of “03” h → Input to ALU (input MB bus data.) ALU (arithmetic logic element) The ALU 19 (8 bits) shown in FIG. 3 performs an arithmetic operation based on DB bus data and 8-bit inputs from the IC.

Functionally, AND (logical product), OR (logical sum), EXOR
(Exclusive OR) and SUM (addition).

Also, a circuit for performing decimal correction of addition and subtraction within the same operation cycle by setting the D flag in the PSR (if D = 1) is included.

Further, it has a function of detecting the occurrence of a carry borrow or overflow as a result of SUM and latching the carry borrow or overflow.

In particular, the carry result is held until the ALU 19 executes the next SUM. (It does not change with AND, OR, EXOR) ALU shifter (arithmetic element shifter) The ALU shifter 28 shown in FIG. 3 is a shift register that performs 1-bit shift writing of 8-bit data, and is mainly a multiplication instruction. Used in.

The data input to this shift register is SLU of ALU19.
UM (addition) result, the most significant bit of which is the SUM
The 1-bit data transmitted from the least significant bit as a result of the shift is finally held as the carry of the ALU19.

RLT (ALU result latch) RLT29 shown in FIG. 3 is an 8-bit latch that holds the operation result of ALU19. The internal bus has the following connection relationship.

RLT → Output to DB or MB However, the contents of RLT29 data are not updated until the next ALU operation is executed.

Shifter The shifter 20 shown in FIG. 3 is constituted by a flip-flop, and selectively executes one bit shift left, shift right or no shift of data by a control signal.

 The internal bus has the following connection relationship.

Shifter → input from MB to output to MB ○ ZDT (Zero detection circuit) ZDT17 shown in Fig. 3 monitors the status of the MB bus,
If all bits of the B bus are “00” h, the zero detection circuit generates a signal indicating that “00” h has been detected.

In particular, this signal acts on the Z flag in the PSR register 30. When the operation result of ALU19 or the like is output from the RLT 29 to the MB bus, the result "00" h is detected and the Z flag is set to "1". Used to prompt the setting operation.

PSR (Processor Status Register) The PSR30 shown in FIG. 3 is composed of a latch and has the following connection relationship with the internal bus.

PSR → Input from MB and output to DB The function of PSR register 30 is as described in the overview.
Indicates the current operating state of the CPU.

BRDT (branch detection circuit) The BRDT 18 shown in FIG. 3 is connected to the PSR 30 and generates a signal for determining whether or not to branch from the contents of the PSR 30 when a branch instruction occurs.

AOBB, AOBH, AOBL (address / output buffer) AOBB, AOBH, AOBL shown in FIG. 3 ACU 16 are buffers for address output.
7 to BA0, A15 to A0) are output.

The address output goes to a high impedance state when BE is low.

VECB, VECH, VECL (vector address generator) VECB, VECH, VECL shown in FIG. 3 ACU unit 16 generates a vector address (24 bits) in interrupt processing.

CALB, CALH, CALL (address calculation latch) CALB, CALH, CALL shown in Fig. 3 ACU unit 16 is INC / DEC:
A latch that selectively stores the result of B: H: L operation,
Latched only during address operation.

RLT2 (Result latch 2) RLT2 shown in the ACU unit 16 in FIG. 3 is a latch that always stores the result of the operation of INC / DEC: B.

○ INC / DEC: B: H: L (Increment / decrement
Unit) INC / DEC: B: H: L shown in ACU unit 16 in FIG. 3 increases or decreases data.

Each functional unit is configured in units of 8 bits, and the carry generated as a result of the operation is stored in the upper address increment / decrement unit (IN
(If C / DEC: L, go to INC / DEC: H; if INC / DEC: H, go to INC / DEC: B)
And eventually realizes 24-bit address generation.

However, this INC / DEC: B: H: L data (8 bits each)
Are input via SB, ABH and ABL data buses (8 bits each).

Each INC / DEC: B: H: L basically selectively performs the following operation on this data.

1. Retention of current data 2. Increment or decrement of “01” h.

3. Increment or decrement of “02” h.

BS (Bus Select) As shown in Fig. 3 ACU unit 16, BS generates data (8 bits) input from outside the CPU when generating an effective address.
It has a function of selecting data to be directly input to AOBL from the DB bus without going through / DEC: L.

In the case of the above-mentioned first direct addressing, the operand data (8
Bit), the effective address must be output immediately after the fetch cycle. In this case, INC / DE
There is a delay through C: L.

Therefore, using this BS, the operand data (DIL) is
AOBL can be rewritten at high speed by placing it on the B bus and selecting it with the BS.

○ CSB, CSH (Carry Selector) CSB, CSH 25 and 26 shown in the ACU unit 16 in FIG. 3 are used when the carry input to INC / DEC: B and INC / DEC: H is I during data operation.
It has a function to select from the lower side of NC / DEC (INC / DEC: L for INC / DEC: H, INC / DEC: H for INC / DEC: B) or to use the carry generated by ALU19. .

Therefore, in this CPU, the addition of displacement data at the time of generating an effective address and the calculation of an address at the time of branching with a program-relative address are performed by ALU19.
And ACU16.

For example, in the case of addressing in which an 8-bit displacement is added to 24-bit data to generate an effective address, ALU1 is added to bits 7 to 0 in the 24-bit data and the displacement data (8 bits).
A is done with 9 and the remaining 24 bits (bit 23 to bit 16) are A
The calculation is performed by the CU unit 16.

When a carry occurs as a result of the addition in the ALU 19, the carry is input to the ACUH via the CSH 25, and the ACU 16 can perform calculations including this carry.

On the other hand, in the case of a normal program counter increment operation, the ALU 19 can perform an operation for another operation using only the ACU 16.

At this time, the carry of ALU19 is ignored, and the carry generated from ACUL16 is input to ACUH via CSH25.

P PBC, PCH, PCL (program counter) These are 24-bit program counter registers.

The increment of this register is performed using INC / DEC: B: H: L.

 The internal bus has the following connection relationship.

PBD → Input from SB, Output to DB or SB PCH → Input from ABH, Output to MB or ABH PCL → Input from ABL, Output to DB or ABL ○ TR, ADH, ADL (temporary register) 8-bit temporary register Data latch. CPU
Invisible from outside. The result of the operation is temporarily stored.

 TR → Input from DB or SB, Output to SB ADH → Input from MB or ABH, Output to ABH ADL → Input from DB or ABL, Output to ABL ○ SPH, SPL (Stack Pointer Register) 16-bit stack pointer・ It is a register.

 The internal bus has the following connection relationship.

SPH → input from MB, output to MB or DB SPL → input from MB, output to DB ○ DBR (Data Bank Register) This is an 8-bit bank register. Basically, this register value is output as the bank address at the time of data access. However, the bank address value varies depending on the state of the mode flag (M1, M0) during PSR.

The DBR is input via the SB bus, and can arbitrarily cope with an increase or decrease in the DBR value.

The internal bus has the following connection relationship. DBR → M
Input from B or SB, output to DB or SB ○ DIL (Data input latch) This is an 8-bit latch. External data is input to this latch.

DIL15 supplies an instruction code to the control unit 1,
The arithmetic unit 2 supplies data to the internal buses (DB, MB, SB).

The following connection relationship is established inside the CPU. DIL → D7
D0 to input, output to DB, MB, SB or control unit DOL (data output latch) This is an 8-bit latch. Data output to the outside is input to this latch.

The following connection relationship is established inside the CPU. DIL → DB
Alternatively, input from MB, output to D7 to D0. Each functional unit of the control unit 1 of this CPU will be described below.

○ Instruction pre-decoder Basically, it has the following three functional units.

1. If the decoding by PLA does not meet the timing, the pre-decoder decodes in advance to generate a control signal.

[Detection of 1-cycle instruction, generation control of external control signal, TCU
7. Control etc.] 2. Assist decoding to minimize PLA code.

[Detection of shortened instructions, detection of data size handled by instructions, etc.] 3. Detection of illegal instructions and software interrupt instructions.

○ Lock generator Generates clock for CPU internal. Alternatively, a system clock for an external system is generated.

WAIT --- Processor stop input LSP--Bus cycle change input CLK--CPU clock input S1, S2--System clock output System control Generates multiple signals to notify CPU operating status .

BSVT --- Processor operating status output (indicating that vector address is being output) BSDA --- Processor operating status output (indicating data access) BSPA --- Processor operating status output (indicating program access) BSOF --- Program operation Status output (indicates instruction fetch) BSML --- Processor operation status output (indicates memory lock status) RWB, RB, WB --- Read / write status output BE --- Bus enable input ○ Interrupt control Controls CPU interrupts I do.

 RES---Reset interrupt input NMI--Non-maskable interrupt input IRO--Interrupt input ISE0 to 3----Interrupt (IRO) selection input WAKE--Processor stop instruction release input TCU (Timing control unit) instruction Controls the execution sequence of execution.

○ ECI (Exclusion Control Interface) ECI has a function of receiving a result of decoding the instruction of the PLA and generating a timing-controlled control signal in the arithmetic unit 2.

R Operation code IR (buffer), pre-byte IR (instruction register) Instruction register for storing instructions.

プ リ Instruction decoding PLA composed of pre-byte AND plane, opcode AND plane, and OR plane AND-OR.

FIG. 1 shows a PLA component of the CPU as described above. The configuration shown in FIG.
This is an example in U. The same components as those in FIG. 3 are denoted by the same reference numerals.

The output side of DIL15 that sends out the supplied input data is
The output of these components 4, 33 is connected to the prebyte instruction register 3 and the opcode instruction buffer 51. The instruction predecoder 33 and the opcode instruction register are connected to each other.

The AND plane is connected to the pre-byte instruction register 3 related to the addressing mode.
The plane is divided into two, that is, a plane 8 and an AND plane 10 to which the opcode instruction register 51 is connected. One TCU 7 is provided for each of the divided AND planes 8 and 10.
Are connected respectively. The output sides of the AND planes 8 and 10 are connected to OR planes 9 and 11 that are integrally formed. In FIG. 3, although the OR planes 9 and 11 are described as being divided into two by the TCU 7, the OR planes 9 and 11 (hereinafter referred to as the OR plane 50) are shown.
Are connected by a connection line and integrally formed. Therefore, the divided AND planes 8 and 10
Are connected to one OR plane 50. These an
The D plane 8, the AND plane 10, and the OR plane 50 are the second plane.
It is configured as shown in the figure.

That is, for the AND planes 8 and 10, the power source 1
P-channel MOS to which 00 is connected (hereinafter referred to as PMOS)
The drain of the transistor 101 is connected in series with the source-drain of a maximum of n N-channel MOS (hereinafter referred to as NMOS) transistors 102, and the NMOS transistor at the lowermost stage
The drain of 102n is grounded. A plurality of output lines 103 having such a configuration are formed in parallel. A precharge line is connected to the gate of each PMOS 101, and each PMOS transistor 101 receives a low-level precharge signal (P in FIG.
When RC is supplied, the output line is turned on.
Precharge 103. On the other hand, the output line 103 is grounded only when a high-level signal is supplied to the gates of all the connected NMOS transistors 102 and turned on, so that a low-level signal is transmitted from the output line 103.

In each output line 103, the drain side of the PMOS transistor 101 is connected to the gate of one or a plurality of NMOS transistors 105 constituting the OR plane 50 via the inverter 104.

The OR plane 50 has a configuration in which a plurality of output lines 106 are connected in parallel to the sources of a plurality of NMOS transistors 105 whose drains are grounded and whose output side of the inverter 104 is connected to the gate. Note that there are n output lines 106, and the number of NMOS transistors 105 connected to each output line 106 differs for each output line 106. Also, each output line 106
Is output to the outside via the inverter 107. Therefore, in the OR plane 50, when one of the NMOS transistors 105 connected to each output line 106 is turned on by a signal supplied from the AND plane 8 or 10, the output line 106 becomes low level and the inverter 107 Is inverted and output as a high level.

The operation of the PLA thus configured will be described below.

When the instruction sent from the DIL 15 has no pre-byte as shown in FIG. 5, the instruction is sent to the AND plane 10 via the opcode instruction buffer 51. For the supplied instruction, a control signal corresponding to the instruction is created in the AND plane 10 and the OR plane 50.

On the other hand, if the instruction sent from the DIL 15 includes a prebyte as shown in FIG. 5, the instruction is sent to the AND plane 8 via the prebyte instruction register 3. For the supplied instruction, a control signal corresponding to the instruction is created in the AND plane 8 and the OR plane 50.

Note that the common connection between the output sides of the AND planes 8 and 10 is connected to the OR plane 50 during the addressing operation.
Use not only U16 but also ALU19 and each register data.
Also when executing the operation of the instruction following the addressing operation
This is for using ALU19 and each register data. For this reason, the OR plane 50 can be minimized by sharing the OR plane 50 with an instruction including a pre-byte and an instruction including an operation code and not including a pre-byte.

Further, since the configuration of the PLA is not a multi-stage logic circuit but two logic circuits, decoding can be performed at high speed.

Further, there is one TCU 7, which is an addressing operation performed using the AND plane 8 and an AND plane 10
Is easily controlled as a series of instructions.

Furthermore, compared to performing convolution, the load on the AND plane is constant and the operation speed is stable.

Further, since the function is divided, the convolution operation can be easily performed, so that the number of input terms as the number of input signals to the AND plane can be reduced in the AND plane. Therefore, the number of the NMOS transistors 102 shown in FIG. 2 is reduced, so that the size of the AND plane in the direction indicated by the arrow y can be reduced.

Further, since a complicated instruction system does not need to be configured because of the function division, it is possible to easily change the logic particularly in the change of the addressing mode and the operation.

Furthermore, since the instruction decoding unit is formed by dividing the functions of the addressing and the operation code, the combination between the addressing and the operation code is free, and an instruction system with high orthogonality can be created.

[Effects of the Invention] As described in detail above, according to the present invention, it is not necessary to configure a multi-stage logic circuit, so that the instruction decoding speed can be increased. Also, by dividing the AND plane, each AND plane can decode an independent instruction and prevent the instruction system from becoming complicated.
Convolution in the plane can be easily performed, and the element area of the AND plane can be reduced, so that the element area of the entire CPU can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a PLA component in a CPU according to the present invention, and FIG. 2 is a diagram showing an AND plane and an OR shown in FIG.
FIG. 3 is a logic circuit diagram showing the configuration of a plane, and FIG.
FIG. 4 is a block diagram showing the overall configuration of U, FIG. 4 is a diagram showing a programming model of the CPU of the present invention, and FIG. 5 is a diagram showing an instruction format of the CPU of the present invention. 7 TCU, 8, 10 AND plane 50 OR plane

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-66627 (JP, A) JP-A-64-65634 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 9/30

Claims (1)

(57) [Claims] 1. A central processing unit of an instruction system in which information related to addressing for designating an address of a data storage destination and information related to an operation are separated, and the information related to the addressing and the information related to an operation are separated. A first AND plane to which an information signal related to addressing transmitted by the separating unit is supplied; a second AND plane to which an information signal related to operation transmitted by the separating unit is supplied; One OR plane to which the signals transmitted by the first and second AND planes are supplied, and the timing of transmitting the addressing-related information signal and the computation-related information signal to the first and second AND planes And one timing control unit that performs
A central processing unit equipped with a PLA.