JP2953447B2 - Manufacturing method of groove-separated semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a trench isolation type semiconductor device, and more particularly to a method for manufacturing a trench isolation type semiconductor device in which a flattening process of a trench-filled element isolation region is improved.

[0002]

2. Description of the Related Art As a method of flattening the surface of a semiconductor device, conventionally, an insulating film covering a step on a substrate surface is formed,
This insulating film is formed by CMP (Chemical Mechanical Polishin).
g: Chemical mechanical polishing) A method of flattening the surface by polishing is known (JP-A-6-310478).
issue). FIG. 3 is a sectional view showing the conventional planarization method in the order of steps.

First, as shown in FIG. 3A, a silicon oxide film 105a and a wiring layer 10 are formed on a silicon substrate 101.
8 is formed, and a buried oxide film 105b made of a silicon oxide film is formed by a CVD method or the like. Buried oxide film 1
05b is formed almost flat in a portion where the distance between the wiring layers 108 is small, but becomes concave in a region where the distance between the wiring layers is large.

Next, as shown in FIG. 3B, a coating film 105d is formed by a known spin coating method so as to cover the buried oxide film 105b and to make the surface thereof flat.

Further, as shown in FIG. 3C, CMP is performed until the buried oxide film 105b and the coating film 105d have substantially the same polishing rate until the coating film 105d disappears at the convex portion of the buried oxide film 105b. When the polishing is performed, the coating film 106 remains in the recess and the buried oxide film 1 is formed.
05b is flattened.

[0006] If the flattening is performed by this method, the flatness of the buried oxide film 105b is improved without any pattern dependence such as the size of the wiring interval.

[0007] Lai-Juh Chen et al apply this planarization method to the step of forming an element trench isolation region (Proceedings of
1996 CMP-MIC Conference, pp307-314 (1996)). FIG.
FIG. 4 is a cross-sectional view showing a groove separation region forming step.

First, as shown in FIG. 4A, a silicon oxide film 102 having a thickness of 25 nm and a silicon nitride film 103 having a thickness of 150 nm are sequentially formed in a predetermined region on a silicon substrate 101, and silicon is formed by a known method. 4 on the substrate 101
An element isolation groove 104 having a depth of 00 to 600 nm is formed. Then, a buried oxide film 105b is formed on the silicon substrate 101 by LP-CVD (low pressure chemical vapor deposition) using TEOS as a source, and thereafter, a heat treatment at 400 ° C. is performed.

Further, as shown in FIG. 4B, a coating film 105d is formed on the buried oxide film 105b by a spin coating method, and the step of the buried oxide film 105b is flattened.

Subsequently, as shown in FIG.
The coating film 105d and the buried oxide film 105b are sequentially polished and removed by a method until the silicon nitride film 103 is exposed, so that the silicon nitride film 103 is planarized.

As described above, the conventional method of polishing and flattening an insulating film reduces the pattern dependency of a step generated in a buried oxide film 105b formed underneath by flattening using a coating film 105d. This eliminates the dependence of polishing on the pattern.

[0012]

However, although planarization by a coating film is a useful method, it is formed by a spin-coating method by dissolving in a solvent regardless of an organic or inorganic type. Has the disadvantage that impurities are present.

Furthermore, since a heat treatment for discharging the solvent and densifying the film is required thereafter, it can be applied to a buried insulating film on a wiring which is not easily affected by impurities. It is difficult to apply the present invention to an element isolation region adjacent to a transistor in which the influence of a diffused impurity greatly affects characteristics.

Further, in the case of a coating film, cracks may occur depending on the film thickness to be formed and the heat treatment temperature, which causes a reduction in production yield.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has high reproducibility and high stability when polishing an insulating film embedded in a trench type element isolation region by polishing. Accordingly, it is an object of the present invention to provide a method of manufacturing a groove-separated semiconductor device which can simultaneously achieve high throughput and low cost, and can improve yield and productivity.

[0016]

According to a method of manufacturing a trench isolation type semiconductor device according to the present invention, a mask film composed of a substrate protective film and an etching stopper film thereover is formed in a predetermined region on a semiconductor substrate. Forming a device isolation groove having a predetermined depth by etching the exposed portion of the semiconductor substrate using the mask film as an etching mask;
Forming an insulating film on a side wall of the device isolation groove, depositing a single layer or a plurality of layers of a trench filling insulating film on the entire surface of the semiconductor substrate, and filling the device isolation groove; Forming a lubricating surfactant layer on an insulating film and flattening the surface thereof; polishing and removing the buried insulating film to expose the etching stopper film; and forming the etching stopper film and the substrate. Removing the protective film sequentially.

In this method of manufacturing a trench isolation type semiconductor device, the buried insulating film is constituted by two insulating films, and the two insulating films are formed by an oxide film formed by a chemical vapor deposition method. And an oxide film formed by a spin coating method. It is preferable that a layer containing nitrogen is present on the surface of the oxide film formed by the spin coating method.

The surfactant is preferably anionic, cationic, nonionic or amphoteric. For example, non-ionic is sorbitan fatty acid ester, and amphoteric is amidobetaine.

Further, the surfactant can be formed by a spin coating method or by immersing the semiconductor substrate in the surfactant.

According to the present invention, when the insulating film in which the trench-type element isolation region is buried is planarized by polishing using a surfactant layer, it is possible to reduce the thickness of the conventional coating film. The problems caused by the film used for planarization, such as the diffusion of impurities and the occurrence of cracks in the coating film, do not occur. Therefore, according to the present invention, a flattening process having high productivity and reproducibility at low cost can be performed. Since the manufacturing method is extremely easy, there is no increase in the number of steps, and there is no need to introduce new equipment, it is possible to form a groove-type element isolation structure with lower cost and higher yield than before.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be specifically described below with reference to the accompanying drawings. FIG.
3A to 3E are cross-sectional views illustrating a method of manufacturing the trench isolation type semiconductor device according to the first embodiment of the present invention in the order of steps.

First, as shown in FIG. 1A, a silicon oxide film 102 having a thickness of 5 to 20 nm is formed on a silicon substrate 101 as a protective film of the substrate by a thermal oxidation method or a CVD method. A silicon nitride film 103 having a thickness of 100 to 200 nm is formed as an etching stopper film and a mask film on the upper layer by, for example, a CVD method.

Further, the silicon oxide film 102 in a predetermined region is formed by photolithography and dry etching.
And the silicon nitride film 103 is removed, and the silicon substrate 1 is removed.
01 is partially exposed.

Thereafter, although not shown, the photoresist mask serving as an etching mask is removed to expose the silicon nitride film 103.

Subsequently, a dry etching method using the silicon nitride film 103 as an etching mask is performed on the silicon substrate 101 to have a width of 200 to 400 nm and a depth of 300 to 60.
A 0 nm device isolation groove 104 is formed.

Subsequently, as shown in FIG. 1B, a side wall silicon oxide film having a thickness of 10 to 20 nm is formed on the portion where the silicon substrate 101 is exposed by the heat treatment method, that is, on the surface of the side wall portion of the element isolation groove 104. Under the condition that deposition and etching occur simultaneously by applying a bias to the substrate and forming a substrate 105a, a high-density plasma, for example, electron cyclotron resonance plasma is used as a plasma source, and silane (SiH ₄ )
A buried oxide film 105b is formed on the silicon substrate 101 to a thickness of 500 to 800 nm by a plasma CVD method using oxygen (O ₂ ) as a gas source.
Embed completely.

This bias application is mainly intended to improve the step coverage. Also, unlike the conventional thermal CVD, LP-CVD and plasma CVD methods, the buried shape becomes flat in a concave portion such as an element isolation groove, but becomes buried in a buried oxide film in a convex portion such as a silicon nitride film. Protrusions are formed. Of course, the buried oxide film is not limited to the bias-applied high-density plasma CVD method, but may be an LP-CVD method, a thermal CVD method, or a plasma CVD method.
It may be formed by a VD method or the like. Further, if necessary, heat treatment may be performed for densification of the buried oxide film and improvement of the withstand voltage.

Then, a nonionic sorbitan fatty acid ester-based lubricating surfactant layer 106 is formed on the buried oxide film 105b by spin coating.

During the polishing and flattening of the buried oxide film, which will be performed later, the surfactant layer 106
The viscosity must be such that it does not easily fall off the surface of b.

Since the sorbitan fatty acid ester is nonionic, it does not affect the chemical stability of the chemicals and ions added to the slurry, and the sorbitan fatty acid ester is mixed with the surfactant even when the slurry is mixed. Original characteristics can be maintained.

Further, the thickness of the surfactant layer 106 to be formed varies depending on the viscosity of the surfactant and the coating conditions, but it is preferable that the thickness be at least enough to hide the protrusions of the buried oxide film.

The formation of the surfactant is not limited to the spin coating method, but may be formed by immersing the semiconductor substrate in the surfactant.

[0033] Subsequently, as shown in FIG. 1 (c), a main component hydroxide force potassium (KOH) and silica force (Si0 ₂₎ particles, or ammonia (NH ₃₎ and silica force (SiO ₂₎ element The buried oxide film 105b is polished and removed by a CMP method using a slurry until the silicon nitride film 103 serving as a polishing stopper layer is exposed.

In this step, as the polishing progresses, the surfactant layer 106 is also gradually removed, or flows into the concave portion of the buried oxide film 105b. This surfactant layer 1
The buried oxide film 105b of the convex portion exposed from 06 is rapidly polished because of its high frictional resistance to the polishing pad, but the other area is protected by the surfactant layer and the lubricating property of the surfactant layer 106 causes the pad to be polished. Is less polished because the frictional resistance to the surface is small.

Therefore, the buried oxide film 105b can be polished without being affected by the size and distribution of the unevenness of the underlying layer, and the polishing pattern dependence such as the occurrence of dishing in a large pattern, which has been a problem in the past, is reduced. Can be resolved.

Further, in the present invention, there is no problem caused by the film formed for flattening, such as diffusion of impurities from the coating film and generation of cracks in the coating film.

When the buried oxide film 105b is flattened, the surfactant layer 106 has been completely removed.
After that, a flat buried oxide film 105b exposed on the entire surface
1D, the size, shape, and distribution of the isolation trench are increased when the polishing is further performed and the silicon nitride film 103 functioning as a stopper film is exposed, as shown in FIG. A polished surface having high flatness independent of the like can be obtained.

Subsequently, as shown in FIG. 1E, when the silicon nitride film 103 and the silicon oxide film 102 are sequentially removed, the buried oxide film 105b and the side wall oxide film 105a are removed.
Is formed on the silicon substrate 101, which is divided by the flat device isolation region formed by the device isolation groove 104 filled with the semiconductor substrate 101. The transistor device may be formed in the exposed silicon substrate region. .

As described above, in the manufacturing method of the trench isolation type semiconductor device of the present embodiment, the flattening of the buried oxide film in the trench isolation type element isolation region having high reproducibility and stability can be achieved with high throughput and low cost. In addition, the manufacturing process is extremely easy, and there is no increase in the number of processes.

In the method of manufacturing a semiconductor device according to the present embodiment, any semiconductor device having a trench-type element isolation structure, such as MOS or Bipolar, can be applied.

Next, a method of manufacturing a groove-separated semiconductor device according to a second embodiment of the present invention will be described. FIG. 2 (a)
(D) is a sectional view showing the method of the second embodiment of the present invention in the order of steps. The second embodiment is effective in the case of a pattern in which the step of the element isolation groove is stricter than in the first embodiment, or in the case where excellent step coverage of the buried oxide film cannot be expected.

First, as shown in FIG. 2A, as in the first embodiment, a silicon oxide film 102 having a thickness of 10 to 20 nm, which is a substrate protective film, and a stopper film are formed on a silicon substrate 101. Silicon nitride film 103 having a thickness of 100 to 200 nm, a width of 200 to 400 nm, and a depth of 300 to 600 n
a device isolation groove 104, a sidewall silicon oxide film 105a having a thickness of 10 to 20 nm is formed.
A buried oxide film 105b is formed on the entire surface of the silicon substrate 101 to a thickness of 500 to 800 nm by a P-CVD method, and the element isolation trench 104 is completely buried. Further, the buried oxide film is heat-treated as necessary.

Then, as shown in FIG. 2B, the silicon substrate 101 is placed in a decompression chamber (not shown) by N2.
The buried oxide film 10 is exposed to H ₃ plasma (not shown).
The surface of 5b is doped with nitrogen.

When the nitrogen doping by the NH ₃ plasma is performed, the doped nitrogen becomes S
combined with i and O, the surface of the buried oxide film has a thickness of 10
An oxynitride film 105c of about nm is formed.

Also, depending on the doping conditions, the oxynitride film 1
A layer of a silicon oxide film containing nitrogen may be formed below the layer 05c, but this layer does not cause a problem because it does not deteriorate the barrier property against impurities described later.

The conditions of nitrogen doping were as follows: bonding using a single-wafer type decompression chamber; substrate temperature = 200 to 400 ° C .;
NH ₃ = 50-100 sccm, pressure = 0.2-5.0
Torr, power = 0.1 to 0.4 Watt / cm ² ,
It is desirable that the plasma doping time is about 3 to 10 minutes. However, since the amount of nitrogen doping and the doping depth on the surface of the buried oxide film 105b change depending on the doping conditions, the type, structure and specifications of the semiconductor device to be applied may vary. In addition, it is necessary to optimize the doping conditions.

The nitrogen doping by the plasma is not only possible in the single-wafer type decompression chamber, but can be similarly performed in the case of using the batch type decompression chamber.

The source used for nitrogen doping is also NH
The gas is not limited to _3, and another gas containing nitrogen may be used. For example, doping with nitrogen gas (N ₂ ) is also possible. However, although N ₂ is less expensive than NH ₃ , the doping characteristics of air are low and NH ₃ is more advantageous for doping a high concentration of nitrogen in a short time.

The formed oxynitride film 105c has a high barrier property against impurities, and according to experiments performed by the present inventors, even if heat treatment is performed at 450 ° C. for 30 minutes, for example, Cu Even an element having a large influence on the transistor does not diffuse into the buried oxide film 105b.

Then, a coating film 105d is formed by a spin coating method.
Is formed on the oxynitride film layer 105c, followed by a heat treatment at 400 ° C. to reduce the step of the buried oxide film 105b.

During this heat treatment, impurities contained in the coating film diffuse in the direction of the buried oxide film, but the oxynitride film 105c formed on the surface of the buried oxide film 105b is formed.
Therefore, the diffusion is prevented, and the buried oxide film 105b does not enter. Therefore, there is no influence on a transistor formed in a later step.

Subsequently, as shown in FIG. 2C, a lubricating surface-active agent layer 106 containing amphoteric amidobetaine as a main component is formed on a silicon substrate by a spin coating method, and a coating film 105d is formed. Flatten the top.

Since amidobetaine is amphoteric, it does not affect the chemical stability of substances and ions added to the slurry, and maintains the inherent properties of the slurry even when the surfactant and the slurry are mixed. Can hold.

Further, the thickness of the formed surfactant layer 106 varies depending on the viscosity of the surfactant and the application conditions.
It is preferable that the film thickness is such that at least the convex portion of the buried oxide film 105b is hidden.

In this embodiment, as in the first embodiment, the surfactant layer 106 may be formed by an immersion method.

Then, as shown in FIG. 2D, a slurry containing, as main components, hydroxide (KOH) and silicic acid (SiO ₂ ) particles or ammonia (NH ₃ ) and silicic acid particles. Then, the coating film 105d, the oxynitride film 105c, and the buried oxide film 105b are polished and removed by CMP until the silicon nitride film 103 serving as the polishing stopper layer is exposed.

In this step, as the polishing proceeds, the surfactant layer 106 flows into the concave portion formed by the polishing. The exposed convex portions are quickly polished because of high frictional resistance to the polishing pad, but other concave regions are protected by the surfactant layer, and the frictional resistance to the pad is small due to the lubricity of the surfactant layer. Is difficult to be polished.

When the buried oxide film 105b is flattened, the surface active agent 106 has been completely removed. After that, only the flat buried oxide film 105b exposed on the entire surface of the silicon substrate 101 is polished, and further polishing proceeds to expose the silicon nitride film 103 functioning as a stopper film. A polished surface having high flatness independent of the size, shape, distribution, etc.

Therefore, the dependence of polishing on the pattern, such as the occurrence of dishing in a large pattern, which has conventionally been a problem, can be eliminated.

Further, there is no problem caused by diffusion of impurities from the coating film due to the barrier effect of the oxynitride film.

Subsequently, as shown in FIG. 2E, when the silicon nitride film 103 and the silicon oxide film 102 are sequentially removed, a flat element isolation region constituted by the element isolation groove 103 filled with the oxide film is formed. Since the divided element formation region 107 is formed on the silicon substrate 101, the transistor element may be formed in the exposed silicon substrate region.

As described above, in the method of manufacturing the semiconductor device of this embodiment, the buried oxide film in the trench isolation type element isolation region having high reproducibility and stability can be flattened at high throughput and low cost. In addition, the manufacturing process is extremely easy and there is no increase in the number of processes.

The present invention can be applied to any semiconductor device having a trench-type element isolation structure, regardless of the type of the semiconductor device, such as MOS or Bipolar.

The method of manufacturing a semiconductor device according to the present invention
The present embodiment is similar to the first embodiment in that the present invention can be applied to any type of semiconductor device such as S and BiPolar.

[0065]

As described above, in the method of manufacturing a semiconductor device according to the present invention, the planarization of the buried insulating film in the groove-type element isolation region does not depend on the size, shape, distribution, etc. of the element isolation groove. Thus, a polished surface having high flatness in an arbitrary pattern can be obtained.

For this reason, the dependence of polishing on the pattern, such as the occurrence of dishing in a large pattern, which has conventionally been a problem, can be eliminated.

Since the manufacturing process is extremely simple and there is no increase in the number of steps, it has higher electric characteristics and better long-term reliability than conventional ones under high controllability, high uniformity and high reproducibility. There is an effect that the groove-type element isolation region can be formed with a high yield.

[Brief description of the drawings]

FIGS. 1A to 1E are sectional views showing a method of a first embodiment of the present invention in the order of steps.

FIGS. 2A to 2D are cross-sectional views showing a method of a second embodiment of the present invention in the order of steps.

FIGS. 3A to 3C are cross-sectional views showing a conventional method.

4A to 4C are cross-sectional views showing another conventional method.

[Explanation of symbols]

 101; silicon substrate 102; silicon oxide film 103; silicon nitride film 104; device isolation groove 105a; sidewall silicon oxide film 105b; buried oxide film 105c; oxynitride film layer 105d; coating film 106; surfactant layer 107; device isolation Region 10; wiring layer

Claims (9)

(57) [Claims] A step of forming a mask film composed of a substrate protective film and an etching stopper film thereover in a predetermined region on the semiconductor substrate, and etching the exposed portion of the semiconductor substrate using the mask film as an etching mask. Forming an element isolation groove having a predetermined depth by forming an insulating film on a side wall of the element isolation groove; and forming a single-layer or plural-layer groove-filling insulating film on the entire surface of the semiconductor substrate. Depositing the element isolation trenches, forming a lubricating surfactant layer on the filling insulating film and flattening the surface thereof, and polishing and removing the buried insulating film. A method for manufacturing a trench isolation type semiconductor device, comprising: a step of exposing an etching stopper film; and a step of sequentially removing the etching stopper film and the substrate protection film. 2. The method according to claim 1, wherein the buried insulating film is composed of two insulating films. 3. The semiconductor device according to claim 2, wherein said insulating film for burying is embedded in said insulating film.
3. The method according to claim 2, wherein the insulating films of the layers are an oxide film formed by a chemical vapor deposition method and an oxide film formed by a spin coating method. . 4. The method according to claim 3, wherein a layer containing nitrogen exists on the surface of the oxide film formed by the spin coating method. 5. The method according to claim 1, wherein the surfactant is anionic, cationic, nonionic or amphoteric. . 6. The method according to claim 5, wherein the surfactant includes a nonionic sorbitan fatty acid ester. 7. The method according to claim 5, wherein the surfactant includes amphoteric amidobetaine. 8. The method according to claim 1, wherein the surfactant is formed by a spin coating method.
13. The method for manufacturing a groove separation type semiconductor device according to item 13. 9. The groove separation type semiconductor according to claim 1, wherein the surfactant is formed by immersing the semiconductor substrate in the surfactant. Device manufacturing method.