JP2940406B2 - Phase comparison circuit and PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase comparison circuit and a PLL circuit suitable for obtaining a clock for timing extraction from a multilevel signal waveform in an electronic device such as a VTR, a disc player, or a communication device. It is.

[0002]

2. Description of the Related Art Conventionally, when performing ternary detection such as partial response class 4 detection, a "prototype PCM-VTR experimental machine" (Technical Report of the Institute of Electronics, Information and Communication Engineers MR79-8) As shown in the example, a path for data detection and a path for clock generation are separately provided. FIG. 10 shows this state, and the amplifier 10
The input reproduction signal amplified by 0 is subjected to waveform equalization by a waveform equalizer 102, and then to a partial response detector 104,
The signals are supplied to the clock generation circuit 106, respectively. The D-flip-flop 108 extracts data based on the extracted clock supplied from the clock generation circuit 106. Thus, the data detection path indicated by arrow F1 and the clock generation path indicated by arrow F2 are separate.

[0003] This is because it is difficult to obtain a signal that directly determines the phase of a clock from a ternary signal. For this reason, for example, the signal is integrated into a binary signal for generation of a clock and converted to a binary value, and a zero-cross comparator or the like is performed to convert the signal into a signal different from the input signal of the partial response detector and generate the clock. doing. As a result, a phase shift occurs between the paths of F1 and F2 due to a circuit delay, so that it is necessary to correct the phase shift by inserting a delay line or the like. Furthermore, if the data rate changes during variable speed reproduction, there is also the inconvenience that it is difficult to lock to the optimum strobe point with a fixed correction amount.

The present invention focuses on the above points,
It is an object of the present invention to provide a phase comparison circuit and a PLL circuit that can generate a clock directly from a multi-level signal waveform and are suitable for a PLL or the like that does not require phase shift correction.

[0005]

In order to achieve the above object, a phase comparison circuit according to the present invention comprises an n value (n) of a digital code.
Detection signal output means obtains a detection signal of logic value for any one level from n-value signal waveform indicating an integer of 2 or more); and a first edge of the detection signal pulse, the first
Outputs a first control signal indicating the distance between the first strobe point of the clock signal immediately following the edges, the first
If there is a second edge of the detection signal between the strobe point to a second strike rope point follows,
Outputs a second control signal indicating a distance between the first strobe point and the second edge, said first strobe
Between the point and the next second strobe point
If there is no second edge of the detection signal, the first switch
Indicates the interval of one cycle of the clock signal from the trobe point
Outputting a third control signal, and the third control signal
The half-cycle interval of the clock signal from the end point of the signal
N-1 control signal outputs for outputting the indicated fourth control signal
Means; a difference between the first control signal and the second control signal, or
Is the sum of the first and fourth control signals and the third control signal.
Using the difference as an error signal, a digital code
The optimal extraction timing for obtaining the logical value of the signal and the clock
Where the phase shift from the strobe point of the
Phase shift detecting means;

One of the main modes is that each waveform of the n-value signal waveform is
N-1 detection signal output means corresponding to each bell
For each of the detection signals obtained
The n-1 control signal output means outputs a control signal.
It is characterized by that. Another embodiment is a method of detecting the phase shift.
The stage receives the next control signal from the control signal output means.
Until the detected phase shift value is
It is a dipump means. PLL of the present invention
The circuit is characterized by using any one of the above-mentioned phase comparison circuits.
Sign. The above and other objects, features and advantages of the present invention will become apparent from the following detailed description and the accompanying drawings.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS While there may be many embodiments of the phase comparator and PLL circuit of the present invention, a suitable number of embodiments will be shown and described in detail. <First Embodiment> FIG. 1 shows a main part of a first embodiment. This example is an application example in which a partial response detection class 4 (PR4) is used for data detection of a digital magnetic recording VTR.

In FIG. 1, a signal recorded on a tape 10 is read by a reproducing head 12. The signal output side of the reproduction head 12 is the reproduction amplifier 1
4 is connected to the waveform equalizer 16. The output side of the waveform equalizer 16 is connected on one side to the delay line 18 and on the other side to the analog adder 20. The output side of the delay line 18 is connected to an analog adder 20, and the output side is connected to signal detectors 22 and 24, respectively. Signal detector 2
Output sides of the circuits 2 and 24 are connected to a PLL circuit 26 and a signal reproduction circuit 28, respectively.

Next, on the input side of the PLL circuit 26, phase comparators 30 and 32 are provided. Phase comparator 30,
The output side of the charge signal C of 32 is connected to the OR gate 34, and the output side of the discharge signal D is connected to the NOR gate 36. These OR gates 34, N
The output side of the OR gate 36 is connected to an analog adder 38, and these constitute a charge pump circuit 40. The output side of the analog adder 38 is connected to the loop filter 42. This loop filter 42
Is connected to a VCO (Voltage Controlled Oscillator) 44. The output side of the VCO 44 is connected to the phase comparators 30, 3
2. It is connected to the clock input side of the signal reproduction circuit 28, respectively.

[0010] Of the above components, the delay line 18
Is for delaying an input signal by a clock cycle and outputting the same. The analog adder 20 is for adding the input signals in an analog manner, and the signal obtained by the addition takes three values at the information transmission point. FIG. 2 shows this state. Assuming that the output of the waveform equalizer 16 has, for example, a signal waveform as shown in FIG. 3A, the output of the analog adder 20 is 3 as shown in FIG.
It becomes a value level signal. The three signal levels are + A,
Assuming that 0 and −A are set, ± A becomes the logical value “H” of the binary digital signal, 0 becomes the logical value “L” of the binary digital signal, and Each corresponds.

The signal detector 22 is for detecting + A of the input ternary signal. FIG. 2 shows an example. In the figure, (A) is a signal waveform after waveform equalization, and the output of the analog adder 20 is as shown in (B) of the figure. By comparing the added signal of (B) at the + A slice level, the upper data shown in FIG. Further, the signal detector 24 is for detecting -A of the input ternary signal. The lower data shown in FIG. 3D is obtained by comparing the addition signal of FIG. 3B at the -A slice level.

Next, the phase comparator 30 of the PLL circuit 26,
32 has a configuration as shown in FIG. The phase comparators 30 and 32 have the same configuration. Also, DF
The two outputs of F are represented as Q and QN (inversion of Q). In the figure, upper data and lower data output from the signal detectors 22 and 24 are D-flip-flops (hereinafter referred to as “D-flip-flops”).
FF ”) is provided to the D input of the FF. D
The D input and Q output of the FF 50 are connected to the AND gate 52, and the D input and QN output are connected to the AND gate 5
4 is connected.

The Q output of the D-FF 50 is connected to the D input of the D-FF 56. The D input and Q output of the D-FF 56 are connected to an AND gate 58, and the QN output is output from the AND gate 52 together with the output of the AND gate 60.
It is connected to the. The output of the AND gate 60 is a discharge signal output. On the other hand, the output of the AND gate 58 is connected to the D input of the D-FF 62. The D input and QN output of this D-FF 62 are AND
AND gates 54 and 64
Are connected to an OR gate 66. The output of the OR gate 66 is a charge signal output.

The reproduced clock supplied from the VCO 42 of the PLL circuit 26 is input to a buffer 68. The non-inverting output side of the buffer 68 is connected to the clock inputs of the D-FFs 50 and 56, and the inverting output side is connected to the D-FF 6
2 clock inputs.

Next, referring to FIG.
The operation of 0, 32 will be described. Since the operations of both are the same, the phase comparator 30 will be described as a representative. FIG. 3A shows the reproduced clock, and FIG. 3B shows the upper data supplied from the signal detector 22. Since the upper data is latched by the D-FF 50 at the strobe point (rising timing) of the reproduced clock, the Q output of the D-FF 50 is as shown in FIG. This is D-FF56
, The Q output of the D-FF 56 is as shown in FIG.

As a result, the output of the AND gate 52 is as shown in FIG. 3E by ANDing the signals in FIGS. 3B and 3C. The output of the AND gate 54 is as shown in FIG. 11F by ANDing the inverted values of FIGS. 11B and 11C. Also, the output of the AND gate 58 is as shown in FIG. 11G by ANDing the signals of FIGS. 11C and 11D, and the output of the AND gate 60 is the inverted value of FIG. (K) is obtained by ANDing (E) with (E). This becomes the discharge signal D1.

On the other hand, in the D-FF 62, the AND of (G)
Since the output of the gate 58 is latched at the falling timing of the reproduced clock of (A), the Q output is as shown in FIG. The output of the AND gate 64 is D-FF6
The AND of the D input and QN output of No. 2, ie, the inverted values of (G) and (H), is as shown in FIG. When this is ORed with the output of the AND gate 54 shown in (F), the output of the OR gate 66 is obtained as shown in FIG. 10J, and this becomes the charge signal C1.

The charge signal C1 and the discharge signal D1 are output from the phase comparator 30. Therefore, the output of the charge pump circuit 40 is as shown in FIG. In the other phase comparators 32, the same processing is performed on the lower data output from the signal detector 24, and the charge signal C2 and the discharge signal D2 are output.

Returning to FIG. 1, the charge pump circuit 40
Is configured as shown in FIG. 9 as a specific example.
In the figure, a charge signal output from an OR gate 34 is supplied to a differential amplifier 40 via a buffer BA and a resistor R.
A is supplied to the inverting input side of A. The discharge signal output from the OR gate 36 is supplied to the inverting input side of the differential amplifier 40A via the inverter BN and the resistor R. On the other hand, also on the non-inverting input side of the differential amplifier 40A,
The parallel circuit of the buffer BA and the resistor R and the inverter BN and the resistor R are connected, but they are grounded.

A capacitor C is connected between the inverting input side and the output of the differential amplifier 40A to form an integrating circuit. That is, in the charge pump circuit 40, the charge signal acts on + with respect to the integrated value, and the discharge signal acts on-. Next, the signal reproduction circuit 28 performs an OR operation on the upper data and the lower data detected by the signal detectors 22 and 24, latches the resulting data with the reproduction clock of the PLL circuit 26, and Restored to digital signal.

Next, the operation of the first embodiment having the above configuration will be described. In the case of PR class 4, a signal reproduced from the tape 10 by the reproducing head 12 is amplified by the reproducing amplifier 14. This signal is equalized in waveform by the waveform equalizer 16, and then added by the analog adder 20 to the signal delayed by the clock period T in the delay line 18. The addition signal is supplied to signal detectors 22 and 24, where upper data and lower data are detected as shown in FIG. The detected upper data and lower data are input to the phase comparators 30 and 32 of the PLL circuit 26, respectively. Phase comparators 30, 3
In 2, the operation shown in FIG. 4 is performed.

(1) When the pulse in the upper data and the lower data is short and includes only one strobe point of the reproduced clock In this case, the reproduced signal after waveform equalization, that is, the output signal of the analog adder 20 is , For example, as shown in FIG. The upper data and lower data output from the signal detectors 22 and 24 are as shown in FIGS. Here, assuming that the reproduced clock is as shown in FIG. 4D, the charge signal C1 + C2 (OR gate 3) obtained as a result of the phase comparison shown in FIG.
4 (e) is as shown in FIG. Also, the discharge signal D1 + D2 (the output of the OR gate 36)
Is as shown in FIG.

Here, these signals will be further examined. Regarding the first pulse of the upper data, the charge signal CA is from the first edge EA1 of the upper data to the strobe point SPA, and the discharge signal DA is from the strobe point SPA to the second edge EA2 of the upper data. Has become. The same applies to other pulses of upper data and lower data.

The charge signal and the discharge signal thus obtained are supplied to an analog adder 38. When there is a phase (frequency) shift between the reproduction signal and the reproduction clock, a difference (a difference in area) occurs between the charge signal and the discharge signal. This difference is supplied to the VCO 44 via the loop filter 42, and the phase (frequency) is controlled according to the difference.

In the example shown, when the charge signal CA and the discharge signal DA are added in an analog manner, a difference corresponding to CA-DA is generated. Based on the difference, the strobe point SPA of the reproduced clock shown in FIG. Is performed. In this way, a reproduced clock for a ternary reproduced signal can be obtained favorably.

(2) Case where the pulse in the upper data and the lower data is long and includes two or more strobe points of the reproduced clock. In this case, the phase shift of the reproduced clock is favorably performed by the method shown in FIG. (Frequency shift) cannot be detected. In this case, the reproduced signal after the waveform equalization, that is, the output signal of the analog adder 20 is, for example, as shown in FIG. The upper data and lower data output from the signal detectors 22 and 24 are as shown in FIGS. The charge signal and the discharge signal with respect to the reproduced clock of FIG. 3D are as shown in FIGS.

Considering these signals, the charge signal CB1 is from the first edge EB1 of the upper data to the strobe point SPB1, the discharge signal DB1 is from the strobe point SPB1 to the next strobe point SPB2, and the end of this signal. Therefore, a half cycle of the reproduction clock is the charge signal CB2. The same applies to other pulses of upper data and lower data.

The charge signal and the discharge signal thus obtained are supplied to an analog adder 38. The discharge signal DB1 corresponds to one cycle of the reproduction clock, and the half cycle thereof is canceled by adding the charge signal CB2. Then, the difference between the remaining half cycle of the discharge signal DB1 and the charge signal CB1 corresponds to the phase shift between the reproduced signal and the reproduced clock, and this is obtained by the analog adder 38. This difference is supplied to the VCO 44 via the loop filter 42, and the phase (frequency) is controlled according to the difference. In this manner, similarly, a reproduced clock for a ternary reproduced signal can be obtained favorably.

For example, as shown in the latter half of FIG. 6, when the charge signals CC1, CC2 and the discharge signal DC1 are added in an analog manner, a difference corresponding to CC1 + CC2-DC1 is generated.
Based on this, phase (frequency) control is performed such that the strobe point SPC1 of the reproduced clock shown in FIG. 3D moves in the direction of arrow FB. The operations of FIGS. 5 and 6 are performed in the phase comparators 30 and 32. 7A and 7B show both operations, and FIGS. 7B to 7F show signal waveforms of the respective parts with respect to the reproduced signal as shown in FIG.

In this way, the reproduced clock satisfactorily obtained from the reproduced signal is supplied to the phase comparison circuit 30,
32, and on the other hand, a signal reproducing circuit 28
Supplied to In the signal reproducing circuit 28, an OR operation is performed on the inputted upper data and lower data, and the data is reproduced by being latched by the flip-flop at the strobe point of the reproduced clock.

As described above, the first embodiment has the following effects. (1) A single path for data generation and clock generation can be used, the circuit configuration is simple, and the cost is low. (2) Since the phase error information is generated based on the strobe point of the clock, the strobe point can be obtained at the center of the data period interval. Therefore, a means for adjusting the strobe point based on the input data is required. And stable clock reproduction is possible.

(3) Since data generation and clock generation are performed on the same path, there is no phase shift due to a plurality of paths unlike the conventional method. Therefore, a means for correcting a phase shift between a plurality of paths is not required, and more accurate clock generation can be performed. (4) Since phase information is obtained based on detection signals respectively corresponding to a plurality of levels of a multi-level signal waveform, compared with a case where phase information is obtained based on a detection signal corresponding to a single level. A lot of phase information can be obtained, and a stable reproduced clock can be obtained with a short lock-in time.

(5) Since the charge pump is used in the PLL, even if the input data rate slightly changes from the reference value in the variable speed reproduction, the clock frequency and the strobe point automatically follow the change. And a good clock can be generated. Further, even if the data inversion period becomes long, the phase shift information is held, so that good clock reproduction is possible.

Embodiment 2 Next, Embodiment 2 will be described with reference to FIG.
The first embodiment is an example of detection of a reproduced clock in a three-valued equalized waveform. For example, a multi-valued equalized waveform represented by partial response detection (1,1,0, -1, -1) is used. However, the present invention is applicable. As shown in FIG. 8, a number of the signal detectors 80a, 80b, ~, 80n and the phase comparator 82a, 82b, ~, required number of 82n (2 or more integer
(N-1)) was prepared for the n value is a number, their charge signal, and supplies a discharge signal to the charge pump circuit 84 so as to analog addition. And
By operating the PLL based on the result of the addition in the same manner as in the first embodiment, it is possible to obtain a reproduced clock for the multilevel waveform.

<Other Embodiments> The present invention can be variously modified based on the above disclosure, and includes, for example, the following. (1) In the above embodiment, the present invention is applied to the detection of PR class 4 data. However, the present invention is also applicable to the case of integration detection (PR (1)) and amplitude detection (PR (1, -1)). Applicable. That is, in the case of integration detection, the slice level of the reproduction signal waveform is set to one, and in the case of amplitude detection, clock reproduction can be performed in exactly the same manner as in the above embodiment. Further, it is not necessary to generate a control signal (charge signal, discharge signal) based on the detection signals obtained from all the detection levels of the multi-level signal waveform, and the control signal is generated based on the detection signals obtained from at least one level. May be generated.

(2) In the above embodiment, the present invention is applied to a reproduced signal of a VTR. However, any multi-level signal such as a disk device and digital transmission may be used. Also, the circuit configuration can be changed in design so as to achieve the same operation. (3) The PLL circuit in the above embodiment can lock if the reproduction clock frequency is within a range of 0.75 to 1.5 times the data rate, but the lock range can be expanded and the lock-in can be performed. A frequency detection circuit may be added to shorten the time. Specifically, in FIG. 9, the frequency of the reproduction clock is detected, and when the reproduction clock frequency is higher than a predetermined range, the discharge input is set to a high level. When the reproduction clock frequency is lower than the predetermined range, the charge input is set to a high level. May be added.

[0037]

As described above, according to the present invention, the following effects can be obtained. (1) A single path for data generation and clock generation can be used, the circuit configuration is simple, and the cost is low. (2) Since the phase error information is generated based on the strobe point of the clock, the strobe point can be obtained at the center of the data period interval. Therefore, a means for adjusting the strobe point based on the input data is required. And stable clock reproduction is possible.

(3) Since data generation and clock generation are performed on the same path, there is no phase shift due to a plurality of paths unlike the conventional method. Therefore, a means for correcting a phase shift between a plurality of paths is not required, and more accurate clock generation can be performed. (4) Since phase information is obtained based on detection signals respectively corresponding to a plurality of levels of a multi-level signal waveform, compared with a case where phase information is obtained based on a detection signal corresponding to a single level. A lot of phase information can be obtained, and a stable reproduced clock can be obtained with a short lock-in time.

(5) Since the charge pump is used in the PLL, even if the input data rate slightly changes from the reference value in the variable speed reproduction, the clock frequency and the strobe point automatically follow the change. And a good clock can be generated. Further, even if the data inversion period becomes long, the phase shift information is held, so that good clock reproduction is possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a graph showing an equalization signal waveform and a detection signal waveform.

FIG. 3 is a circuit diagram illustrating a configuration example of a phase comparison circuit.

FIG. 4 is a time chart illustrating an operation of the phase comparison circuit.

FIG. 5 is a time chart illustrating a clock phase control operation.

FIG. 6 is a time chart illustrating a clock phase control operation.

FIG. 7 is a time chart illustrating a clock phase control operation.

FIG. 8 is a block diagram illustrating a main part of a second embodiment.

FIG. 9 is a circuit diagram showing a specific example of a charge pump circuit.

FIG. 10 is a block diagram illustrating an example of a background art.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Tape 12 ... Reproduction head 14 ... Reproduction amplifier 16 ... Waveform equalizer 18 ... Delay line 20 ... Analog adder 22, 24, 80a-80n ... Signal detector (detection signal output means) 26 ... PLL circuit 28 ... Signal Reproduction circuits 30, 32, 82a to 82n: phase comparators (control signal detection means) 34: OR gate 36: NOR gate 38: analog adders 40, 84 ... charge pump circuits (phase shift detection means) 42: loop filter 44 ... VCO

Continuation of the front page (56) References JP-A-64-60132 (JP, A) JP-A-1-226238 (JP, A) JP-A-8-46606 (JP, A) JP-A-4-313386 (JP) JP-A-6-188727 (JP, A) JP-A-6-131823 (JP, A) JP-A-6-16337 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB G11B 20/14 G11B 20/10 H03L 7/085 H04L 7/033

Claims (4)

(57) [Claims] (1)N value of digital code (n is an integer of 2 or more)
N)Value signal waveform to any one level
Detection signal output means for obtaining a detection signal of a logical value to be obtained; a first edge of a pulse of the detection signal;First edge
Comes right afterClock signalFirstStrobe point
And outputs a first control signal indicating the interval ofThe firstStrike
Next from robe pointSecondTo the strobe point
If there is a second edge of the detection signal betweenThe said
OneIndicates the distance between the strobe point and the second edge
Outputting a second control signal;The first strobe point
Between the second and the next strobe point
If there is no second edge of the signal, the first straw
The third indicating the interval of one cycle of the clock signal from the
And a control signal of the third control signal.
The second half-cycle interval of the clock signal from the end point
N-1 control signal output means for outputting 4 control signals; The difference between the first control signal and the second control signal, or
The difference between the sum of the first and fourth control signals and the third control signal is incorrect.
As a difference signal, a digital code
Optimal extraction timing for obtaining a theoretical value and the clock signal
Phase shift to detect phase shift with strobe point
Detection means;  The phase comparison circuit provided with. 2. Each corresponding to each level of the n-value signal waveform
N-1 detection signal output means for
Each of the detection signals obtained by the above-mentioned n-1
The phase comparison circuit according to claim 1, wherein the control signal output means outputs a control signal . 3. The apparatus according to claim 2 , wherein said phase shift detecting means is provided with a control signal.
Detected until the next control signal is input from the output means
Charge pump means for holding the value of the phase shift
The phase comparison circuit according to claim 1 . 4. The method according to claim 1, 2 or 3.
PLL circuit using the phase comparison circuit of FIG.