JP2822734B2 - Noise shaper - Google Patents
Noise shaperInfo
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- JP2822734B2 JP2822734B2 JP3315882A JP31588291A JP2822734B2 JP 2822734 B2 JP2822734 B2 JP 2822734B2 JP 3315882 A JP3315882 A JP 3315882A JP 31588291 A JP31588291 A JP 31588291A JP 2822734 B2 JP2822734 B2 JP 2822734B2
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- Japan
- Prior art keywords
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- circuit
- signal
- integration
- constant
- Prior art date
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Description
【０００１】[0001]
【産業上の利用分野】本発明は特に入力信号が無信号の
時は出力信号も零になり、低周波数領域に雑音を生じな
いノイズシェイパに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise shaper in which an output signal becomes zero when an input signal is absent and does not generate noise in a low frequency region.
【０００２】[0002]
【従来の技術】従来の３値を出力とするノイズシェイパ
は、例えば図６に示す様な構成になっている。即ち、第
１及び第２の積分器Ｓ１，Ｓ２と、第２の積分器の出力
を入力とし、３値の信号を出力とする量子化器Ｃと、量
子化器の出力を第１及び第２の積分器Ｓ１，Ｓ２に帰還
する遅延器Ｄを有する帰還回路とで構成されている。第
１の積分器Ｓ１の出力は増幅器Ａで２倍に増幅された遅
延器Ｄの出力と減算されて第２の積分器に入力されてい
る。また、積分器はディジタル回路によって構成され、
図７に示す回路によって実現されている。2. Description of the Related Art A conventional noise shaper which outputs three values has, for example, a configuration as shown in FIG. That is, the first and second integrators S1 and S2, the quantizer C that receives the output of the second integrator and outputs a ternary signal, and outputs the first and second integrators to the first and second integrators. And a feedback circuit having a delay device D that feeds back to the two integrators S1 and S2. The output of the first integrator S1 is subtracted from the output of the delay unit D, which has been amplified twice by the amplifier A, and input to the second integrator. The integrator is constituted by a digital circuit,
This is realized by the circuit shown in FIG.
【０００３】次に、図６を用いて従来のノイズシェイパ
の動作を説明する。第１段目の積分器Ｓ１には、遅延器
Ｄで遅延された量子化器Ｃの出力信号と入力信号との差
信号が入力され積分される。また、第１段目の積分器Ｓ
１の出力信号と遅延器Ｄで遅延された量子化器Ｃの出力
信号の２倍との差信号が、第２段目の積分器Ｓ２に入力
され積分される。第２段目の積分器Ｓ２の出力は、量子
化器Ｃに入力される。この時、＋１／２より大きい時は
出力は＋１に、−１／２から＋１／２の間場合は０が、
また−１／２よりも小さい時は−１が出力される。この
様な構成を持つ事によって、量子化器Ｃで発生する量子
化雑音をＱとすると、ノイズシェイパ入力信号Ｘと出力
信号Ｙの間には次式に示す関係がある。Next, the operation of the conventional noise shaper will be described with reference to FIG. The difference signal between the output signal of the quantizer C delayed by the delay unit D and the input signal is input to the first integrator S1 and integrated. The first stage integrator S
A difference signal between the output signal of No. 1 and twice the output signal of the quantizer C delayed by the delay device D is input to the second-stage integrator S2 and integrated. The output of the second stage integrator S2 is input to the quantizer C. At this time, when the output is greater than + ／, the output is +1. When the output is between-／ and + ／, 0 is output.
When it is smaller than -1/2, -1 is output. With such a configuration, assuming that quantization noise generated by the quantizer C is Q, there is a relationship expressed by the following equation between the noise shaper input signal X and the output signal Y.
【０００４】 Ｙ（ｚ）＝Ｘ（ｚ）＋（１−ｚ-1）2 ・Ｑ（Ｚ） …… （１） 従って、ノイズシェイパの出力スペクトラムは、ノイズ
シェイパの入力に量子化雑音を２階微分した信号を重畳
したスペクトラムを有する事になる。即ち、量子化雑音
が高周波領域にシェイピングされて重畳されるため、信
号帯域内における雑音総和を大幅に減少する。Y (z) = X (z) + (1−z −1 ) 2 · Q (Z) (1) Therefore, the output spectrum of the noise shaper is obtained by differentiating the quantization noise to the input of the noise shaper by the second order. Will have a spectrum in which the resulting signal is superimposed. That is, since the quantization noise is shaped and superimposed in the high frequency region, the total noise in the signal band is significantly reduced.
【０００５】ところで、このノイズシェイパに無信号が
入力された場合を考える。図７に示すように積分器Ｓ
１，Ｓ２を構成する遅延器Ｄ１，Ｄ２のデータが、初期
状態で零であると出力信号は零になる事は明らかであ
る。一方、積分器Ｓ１，Ｓ２を構成する遅延器Ｄ１，Ｄ
２のデータが初期状態で零ではなく、例えば第１段目の
積分器Ｓ１の初期値が０．５であると仮定する。この
時、ノイズシェイパの出力は、＋１及び−１を繰り返
し、零にはならない。また、第１段目の積分器Ｓ１の初
期値が０．５よりも小さく、例えば０．１の場合は、＋
１、−１、８回連続零、＋１、−１、８回連続零・・を
定常的に繰り返す。これらの事から、第１段目の積分器
Ｓ１の初期値が零ではない場合、ノイズシェイパの出力
は零にはならない事がわかる。また、第１段目の積分器
Ｓ１の初期値が小さい程、＋１、−１の次に続く０の回
数が増え、従って、出力に含まれるスペクトラムに低周
波成分が現われる。Now, consider a case where a no signal is input to the noise shaper. As shown in FIG.
It is apparent that the output signal becomes zero when the data of the delay units D1 and D2 constituting S1, S2 is zero in the initial state. On the other hand, the delay devices D1, D constituting the integrators S1, S2
It is assumed that the data of No. 2 is not zero in the initial state, and for example, the initial value of the integrator S1 in the first stage is 0.5. At this time, the output of the noise shaper repeats +1 and -1 and does not become zero. Further, when the initial value of the first-stage integrator S1 is smaller than 0.5, for example, 0.1, +
1, −1, 8 consecutive zeros, +1, −1, 8 consecutive zeros... Are constantly repeated. From these facts, it can be seen that when the initial value of the first-stage integrator S1 is not zero, the output of the noise shaper does not become zero. Further, as the initial value of the first-stage integrator S1 becomes smaller, the number of 0s following +1 and -1 increases, and accordingly, a low-frequency component appears in the spectrum included in the output.
【０００６】[0006]
【発明が解決しようとする課題】図６に示す上述した従
来のノイズシェイパでは、無信号が入力された場合で第
１段目の積分器Ｓ１の初期値が小さければ小さい程、出
力信号に含まれるスペクトラムにより低周波成分が現わ
れる問題があった。In the above-described conventional noise shaper shown in FIG. 6, when no signal is input, the smaller the initial value of the first-stage integrator S1 is, the smaller the initial value is included in the output signal. There is a problem that low frequency components appear due to the spectrum.
【０００７】[0007]
【課題を解決するための手段】本発明によれば、１段以
上の積分回路と、０及び±１を出力とする３値量子化器
と帰還回路とで構成されるノイズシェイパにおいて、ノ
イズシェイパの入力信号と前記帰還回路の１つ以上の出
力信号とを前記積分回路に入力する接続と、前記積分回
路の出力信号を前記量子化器に入力する接続と、前記量
子化器とノイズシェイパの出力端子との接続とを有し、
少なくとも１つ以上の積分回路の積分動作が１サンプル
遅延前の蓄積データと現データと絶対値が一定値あるい
は零である定数との加算によって実現される不完全積分
動作であって、前記１サンプル遅延前の蓄積データの符
号に応じて定数の符号を制御する手段を有したノイズシ
ェイパを得る。According to the present invention, in a noise shaper comprising one or more stages of an integrating circuit, a ternary quantizer outputting 0 and ± 1 and a feedback circuit, an input of the noise shaper is provided. A connection for inputting a signal and one or more output signals of the feedback circuit to the integration circuit, a connection for inputting the output signal of the integration circuit to the quantizer, and output terminals of the quantizer and the noise shaper; Having a connection with
The integration operation of at least one or more integration circuits is an incomplete integration operation realized by adding accumulated data before one sample delay, current data, and a constant whose absolute value is constant or zero. A noise shaper having means for controlling the sign of a constant according to the sign of accumulated data before delay is obtained.
【０００８】[0008]
【実施例】次に、本発明について図面を参照して説明す
る。Next, the present invention will be described with reference to the drawings.
【０００９】図１は本発明の一実施例である。Ｓ１は第
１段目の積分器、Ｓ２は第２段目の積分器、Ｃは±０．
５をしきい値として３値のレベルを出力する量子化器、
Ｄは遅延器、Ａは増幅率２の増幅器である。第１段目の
積分器Ｓ１には、遅延器Ｄで遅延された量子化器Ｃの出
力信号と入力信号との差信号が入力され積分される。ま
た、第１段目の積分器Ｓ１の出力信号と遅延器Ｄで遅延
された後増幅器Ａで増幅された量子化器Ｃの出力信号の
２倍との差信号が、第２段目の積分器Ｓ２に入力され、
積分される。第２，段目の積分器Ｓ２の出力は、量子化
器Ｃに入力される。量子化器Ｃにおいては、入力が＋１
／２より大きい時は出力は＋１に、−１／２から＋１／
２の間場合は０が、また−１／２よりも小さい時は−１
が出力される。また、積分器Ｓ１，Ｓ２は、例えば図２
に示すように構成することができる。図２に示す様に、
第１段目の積分器Ｓ１は、１サンプル遅延前の蓄積デー
タと現データと固定定数（±２-18 ）との加算を行う。
この時、固定定数の符号は、１サンプル遅延前の蓄積デ
ータが正の時は負に、１サンプル遅延前の蓄積データが
負の時は正に、１サンプル遅延前の蓄積データが零の時
は固定定数を零に符号制御回路ＣＯＮＴ１で制御され
る。また第２段目の積分器Ｓ２は、１サンプル遅延前の
蓄積データと現データとの加算によって実現される完全
積分器である。FIG. 1 shows an embodiment of the present invention. S1 is a first-stage integrator, S2 is a second-stage integrator, and C is ± 0.
A quantizer that outputs a ternary level with 5 as a threshold,
D is a delay unit, and A is an amplifier with an amplification factor of 2. The difference signal between the output signal of the quantizer C delayed by the delay unit D and the input signal is input to the first integrator S1 and integrated. The difference signal between the output signal of the first-stage integrator S1 and twice the output signal of the quantizer C that has been delayed by the delay unit D and then amplified by the amplifier A is the integration signal of the second stage. Input to the vessel S2,
Is integrated. The output of the second-stage integrator S2 is input to the quantizer C. In the quantizer C, the input is +1
If it is greater than / 2, the output is +1, and -1/2 to + 1 /
0 if between two, -1 if less than -1/2
Is output. Further, the integrators S1 and S2 are provided, for example, in FIG.
Can be configured as shown in FIG. As shown in FIG.
The first-stage integrator S1 adds the accumulated data before the delay of one sample, the current data, and the fixed constant (± 2 -18 ).
At this time, the sign of the fixed constant is negative when the accumulated data before the delay of one sample is positive, positive when the accumulated data before the delay of one sample is negative, and is zero when the accumulated data before the delay of one sample is zero. Is controlled by the sign control circuit CONT1 to a fixed constant of zero. The second-stage integrator S2 is a complete integrator realized by adding the accumulated data before the delay of one sample and the current data.
【００１０】この様な構成を持つ事によって、量子化器
Ｃで発生する量子化雑音をＱとすると、ノイズシェイパ
入力信号Ｘと出力信号Ｙの間にはおおむね次式に示す関
係がある。With such a configuration, if the quantization noise generated by the quantizer C is assumed to be Q, the relationship between the noise shaper input signal X and the output signal Y is approximately expressed by the following equation.
【００１１】 Ｙ（ｚ）＝ｚ-1・Ｘ（ｚ）／Ｐ（ｚ）＋（１−ｚ-1）2 ・Ｑ（ｚ）…（２） 従って、ノイズシェイパの出力スペクトラムは、ノイズ
シェイパの入力に量子化雑音を殆ど２階微分した信号を
重畳したスペクトラムを有する事になる。即ち、量子化
雑音が高周波領域にシェイピングされて重畳されるた
め、従来のノイズシェイピングの特性をそれ程劣化させ
ることなく信号帯域内における雑音総和は大幅に減少す
る。Y (z) = z -1 · X (z) / P (z) + (1 -z -1 ) 2 · Q (z) (2) Therefore, the output spectrum of the noise shaper is the input of the noise shaper. Has a spectrum obtained by superimposing a signal obtained by second-order differentiation of quantization noise. That is, since the quantization noise is shaped and superimposed in the high-frequency region, the noise sum in the signal band is greatly reduced without significantly deteriorating the characteristics of the conventional noise shaping.
【００１２】以上示した動作において、ノイズシェイパ
に無信号が入力された場合を考える。今、第１段目，第
２段目の積分器Ｓ１，Ｓ２の初期値が零の場合は出力コ
ードは零になる事は明かである。次に第１段目の積分器
Ｓ１の初期値が零以外の一定の値の場合は、蓄積データ
の符号によって符号が制御される一定定数の加算によっ
て次第に絶対値が小さくなりやがては零になる。従っ
て、ノイズシェイパの出力は常に零になる。In the operation described above, it is assumed that no signal is input to the noise shaper. It is apparent that the output code becomes zero when the initial values of the first and second stage integrators S1 and S2 are zero. Next, when the initial value of the first-stage integrator S1 is a constant value other than zero, the absolute value gradually decreases by adding a constant constant whose sign is controlled by the sign of the stored data, and eventually becomes zero. . Therefore, the output of the noise shaper is always zero.
【００１３】次に、本発明の第二の実施例について説明
する。第一の実施例では、第１段目の積分器Ｓ１を図２
に示す回路で実現した。図３に第二の実施例に用いた積
分器の回路図を示す。図３に示す様に、１段目の積分器
Ｓ１は、１サンプル遅延前の蓄積データと現データと固
定定数（±２-16 ）との加算を行う。この時、固定定数
の符号は、１サンプル遅延前の蓄積データが正の時は負
に、１サンプル遅延前の蓄積データが負の時は正に、１
サンプル遅延前の蓄積データが零の時は固定定数を零に
符号制御回路ＣＯＮＴ２で制御される。また第２段目の
積分器Ｓ２は、１サンプル遅延前の蓄積データと現デー
タとの加算によって実現される完全積分器である。Next, a second embodiment of the present invention will be described. In the first embodiment, the first-stage integrator S1 is
This was realized by the circuit shown in Figure 1. FIG. 3 shows a circuit diagram of the integrator used in the second embodiment. As shown in FIG. 3, the first-stage integrator S1 adds the accumulated data before the delay of one sample, the current data, and the fixed constant (± 2 -16 ). At this time, the sign of the fixed constant becomes negative when the accumulated data before the delay of one sample is positive, and becomes positive when the accumulated data before the delay of one sample is negative.
When the stored data before the sample delay is zero, the fixed constant is set to zero and controlled by the sign control circuit CONT2. The second-stage integrator S2 is a complete integrator realized by adding the accumulated data before the delay of one sample and the current data.
【００１４】この様な構成を持つ事によって、量子化器
Ｃで発生する量子化雑音をＱとすると、ノイズシェイパ
入力信号Ｘと出力信号Ｙの間にはおおむね次式に示す関
係がある。With such a configuration, if the quantization noise generated by the quantizer C is assumed to be Q, the relationship between the noise shaper input signal X and the output signal Y is approximately expressed by the following equation.
【００１５】 Ｙ（ｚ）＝ｚ-1・Ｘ（ｚ）／Ｐ（ｚ）＋（１−ｚ-1）2 ・Ｑ（ｚ）…（３） 従って、ノイズシェイパの出力スペクトラムは、ノイズ
シェイパの入力に量子化雑音を殆ど２階微分した信号を
重畳したスペクトラムを有する事になる。即ち、量子化
雑音が高周波領域にシェイピングされて重畳されるた
め、従来のノイズシェイパの特性をそれ程劣化させるこ
となく信号帯域内における雑音総和は大幅に減少する。Y (z) = z -1 · X (z) / P (z) + (1 -z -1 ) 2 · Q (z) (3) Therefore, the output spectrum of the noise shaper is the input of the noise shaper. Has a spectrum obtained by superimposing a signal obtained by second-order differentiation of quantization noise. That is, since the quantization noise is shaped and superimposed in the high-frequency region, the noise sum in the signal band is significantly reduced without deteriorating the characteristics of the conventional noise shaper.
【００１６】以上に示した動作において、ノイズシェイ
パに無信号が入力された場合を考える。今、第１段目，
第２段目の積分器Ｓ１，Ｓ２の初期値が零の場合は出力
コードは零になる事は明かである。次に第１段目の積分
器Ｓ１の初期値が零以外の一定の値の場合は、蓄積デー
タの符号によって符号が制御される一定定数の加算によ
って次第に絶対値が小さくなりやがては零になる。従っ
て、ノイズシェイパの出力は常に零になる。In the operation described above, consider a case where a no signal is input to the noise shaper. Now, the first stage,
It is clear that the output code becomes zero when the initial values of the second-stage integrators S1 and S2 are zero. Next, when the initial value of the first-stage integrator S1 is a constant value other than zero, the absolute value gradually decreases by adding a constant constant whose sign is controlled by the sign of the stored data, and eventually becomes zero. . Therefore, the output of the noise shaper is always zero.
【００１７】次に、第三の実施例について説明する。図
４は第三の実施例を示す回路図である。図４において、
Ｓ１は第１段目の積分器、Ｓ２は第２段目の積分器、Ｃ
は±０．５をしきい値として３値のレベルを出力する量
子化器、Ｄは遅延器である。第１段目の積分器Ｓ１に
は、遅延器Ｄで遅延された量子化器Ｃの出力信号と入力
信号との差信号が入力され積分される。また、第１段目
の積分器Ｓ１の出力信号と遅延器Ｄで遅延された量子化
器Ｃの出力信号との差信号が、第２段目の積分器Ｓ２に
入力され、積分される。第２段目の積分器Ｓ２の出力
は、量子化器Ｃに入力される。この時、＋１／２より大
きい時は出力は＋１に、−１／２から＋１／２の間場合
は０が、また−１／２よりも小さい時は−１が出力され
る。また、積分器Ｓ１，Ｓ２は、例えば図５に示すよう
に構成することができる。図５に示す様に、１段目の積
分器Ｓ１は、１サンプル遅延前の蓄積データと現データ
と固定定数（±２-18 ）との加算を行う。この時、固定
定数の符号は、１サンプル遅延前の蓄積データが正の時
は負に、１サンプル遅延前の蓄積データが負の時は正
に、１サンプル遅延前の蓄積データが零の時は固定定数
を零に符号制御回路３で制御される。また第２段目の積
分器は、１サンプル遅延前の蓄積データと現データとの
加算によって実現される完全積分器である。Next, a third embodiment will be described. FIG. 4 is a circuit diagram showing a third embodiment. In FIG.
S1 is the first-stage integrator, S2 is the second-stage integrator, C
Is a quantizer that outputs three levels with ± 0.5 as a threshold, and D is a delay unit. The difference signal between the output signal of the quantizer C delayed by the delay unit D and the input signal is input to the first integrator S1 and integrated. The difference signal between the output signal of the first-stage integrator S1 and the output signal of the quantizer C delayed by the delay unit D is input to the second-stage integrator S2 and integrated. The output of the second stage integrator S2 is input to the quantizer C. At this time, the output is +1 when the value is larger than + 、, 0 when the value is between -−１ and + ／, and −1 when the value is smaller than-／. Further, the integrators S1 and S2 can be configured as shown in FIG. 5, for example. As shown in FIG. 5, the first-stage integrator S1 adds the accumulated data before the delay of one sample, the current data, and the fixed constant (± 2 −18 ). At this time, the sign of the fixed constant is negative when the accumulated data before the delay of one sample is positive, positive when the accumulated data before the delay of one sample is negative, and is zero when the accumulated data before the delay of one sample is zero. Is controlled by the sign control circuit 3 to a fixed constant of zero. The second-stage integrator is a complete integrator realized by adding the accumulated data before one sample delay and the current data.
【００１８】この様な構成を持つ事によって、量子化器
Ｃで発生する量子化雑音をＱとすると、ノイズシェイパ
入力信号Ｘと出力信号Ｙの間にはおおむね次式に示す関
係がある。With such a configuration, assuming that the quantization noise generated by the quantizer C is Q, the relationship between the noise shaper input signal X and the output signal Y is generally expressed by the following equation.
【００１９】 Ｙ（ｚ）＝ｚ-1・Ｘ（ｚ）／Ｐ（ｚ）＋（１−ｚ-1）2 ・Ｑ（ｚ）…（４） 従って、ノイズシェイパの出力スペクトラムは、ノイズ
シェイパの入力に量子化雑音を殆ど２階微分した信号を
重畳したスペクトラムを有する事になる。即ち、量子化
雑音が高周波領域にシェイピングされて重畳されるた
め、従来のノイズシェイピングの特性をそれ程劣化させ
ることなく信号帯域内における雑音総和は大幅に減少す
る。Y (z) = z -1 · X (z) / P (z) + (1 -z -1 ) 2 · Q (z) (4) Accordingly, the output spectrum of the noise shaper is the input spectrum of the noise shaper. Has a spectrum obtained by superimposing a signal obtained by second-order differentiation of quantization noise. That is, since the quantization noise is shaped and superimposed in the high-frequency region, the noise sum in the signal band is greatly reduced without significantly deteriorating the characteristics of the conventional noise shaping.
【００２０】以上に示した動作において、ノイズシェイ
パに無信号が入力された場合を考える。今、第１段目、
第２段目の積分器Ｓ１，Ｓ２の初期値が零の場合は出力
コードは零になる事は明かである。次に第１段目の積分
器Ｓ１の初期値が零以外の一定の値の場合は、蓄積デー
タの符号によって符号が制御される一定定数の加算によ
って次第に絶対値が小さくなりやがては零になる。従っ
て、ノイズシェイパの出力は常に零になる。In the operation described above, consider the case where a no signal is input to the noise shaper. Now, the first stage,
It is clear that the output code becomes zero when the initial values of the second-stage integrators S1 and S2 are zero. Next, when the initial value of the first-stage integrator S1 is a constant value other than zero, the absolute value gradually decreases by adding a constant constant whose sign is controlled by the sign of the stored data, and eventually becomes zero. . Therefore, the output of the noise shaper is always zero.
【００２１】以上に示した第一〜第三の実施例の、不完
全積分を実現するための１サンプル遅延前の蓄積データ
によって符号を制御された一定定数の加算において、１
サンプル遅延前の蓄積データが零の時に零を加算するの
ではなく、正、あるいは負の一定定数を加算しても動作
上殆ど相違なく、無信号入力時の出力は零になる事は明
かである。In the above-described first to third embodiments, the addition of a fixed constant whose sign is controlled by the accumulated data before one sample delay for realizing incomplete integration is 1
It is clear that the operation is almost the same even if a positive or negative constant is added instead of adding zero when the accumulated data before the sample delay is zero, and the output when no signal is input becomes zero. is there.
【００２２】[0022]
【発明の効果】以上説明したように、本発明のノイズシ
ェイパでは、Ｓ／Ｎ特性を損なう事なく、無信号が入力
された場合は出力信号を零にする事ができる。As described above, in the noise shaper of the present invention, the output signal can be made zero when no signal is input without deteriorating the S / N characteristics.
【図１】本発明の第一の実施例の回路図。FIG. 1 is a circuit diagram of a first embodiment of the present invention.
【図２】本発明の第一の実施例を構成する積分器の回路
図。FIG. 2 is a circuit diagram of an integrator constituting the first embodiment of the present invention.
【図３】本発明の第二の実施例を構成する積分器の回路
図。FIG. 3 is a circuit diagram of an integrator constituting a second embodiment of the present invention.
【図４】本発明の第三の実施例の回路図。FIG. 4 is a circuit diagram of a third embodiment of the present invention.
【図５】本発明の第三の実施例を構成する積分器の回路
図。FIG. 5 is a circuit diagram of an integrator constituting a third embodiment of the present invention.
【図６】従来のノイズシェイパの回路図。FIG. 6 is a circuit diagram of a conventional noise shaper.
【図７】従来のノイズシェイパを構成する積分器の回路
図。FIG. 7 is a circuit diagram of an integrator constituting a conventional noise shaper.
Ｓ１ 第１の積分器 Ｓ２ 第２の積分器 Ｄ，Ｄ１，Ｄ２ 遅延器 Ｃ 量子化器 Ａ 増幅器 S1 first integrator S2 second integrator D, D1, D2 delay unit C quantizer A amplifier
Claims (3)
前記第１の積分回路の出力が印加される第２の積分回路
と、前記第２の積分回路の出力が印加され量子化した信
号を出力する量子化器と、前記量子化器の出力信号を１
サンプル遅延前の蓄積データとして前記第１および第２
の積分回路に印加する帰還回路とを備えるノイズシェイ
パであって、前記第１の積分回路の積分動作が、前記１
サンプル遅延前の蓄積データと前記現データと定数との
加算によって実現される不完全積分動作であって、前記
１サンプル遅延前の蓄積データが正の時は前記定数の符
号を負とし、前記１サンプル遅延前の蓄積データが負の
時は前記定数の符号を正とし、前記１サンプル遅延前の
蓄積データが零の時は前記定数を零とする符号制御回路
を有する事を特徴とするノイズシェイパ。A first integration circuit to which current data is applied;
A second integration circuit to which an output of the first integration circuit is applied
And a quantized signal to which the output of the second integration circuit is applied and quantized.
A quantizer for outputting a signal, and an output signal of the quantizer is set to 1
The first and second data are stored data before the sample delay.
And a feedback circuit applied to the integrating circuit
Wherein the integration operation of the first integration circuit is performed by the first integration circuit.
Wherein the sample delay preceding accumulated data is incomplete integration operation realized by adding the current data and constants, the accumulation data before said one sample delay time of positive and negative sign of the constant, the 1 A noise shaper comprising a sign control circuit that sets the sign of the constant to positive when the accumulated data before the sample delay is negative, and sets the constant to zero when the accumulated data before the one-sample delay is zero.
前記第１の積分回路の出力が印加される第２の積分回路
と、前記第２の積分回路の出力が印加され量子化した信
号を出力する量子化器と、前記量子化器の出力信号を１
サンプル遅延前の蓄積データとして前記第１および第２
の積分回路に印加する帰還回路とを備えるノイズシェイ
パであって、前記第１の積分回路の積分動作が、前記１
サンプル遅延前の蓄積データと前記現データと定数との
加算によって実現される不完全積分動作であって、前記
１サンプル遅延前の蓄積データが正あるいは零の時は前
記定数の符号を負とし、前記１サンプル遅延前の蓄積デ
ータが負の時は前記定数の符号を正とする符号制御回路
を有する事を特徴とするノイズシェイパ。2. A first integration circuit to which current data is applied,
A second integration circuit to which an output of the first integration circuit is applied
And a quantized signal to which the output of the second integration circuit is applied and quantized.
A quantizer for outputting a signal, and an output signal of the quantizer is set to 1
The first and second data are stored data before the sample delay.
And a feedback circuit applied to the integrating circuit
Wherein the integration operation of the first integration circuit is performed by the first integration circuit.
Wherein the sample delay preceding accumulated data is incomplete integration operation realized by adding the current data and the constant, the time accumulation data before said one sample delay is positive or zero and negative sign of the constant, A noise shaper having a sign control circuit for setting the sign of the constant to be positive when the accumulated data before the one-sample delay is negative.
前記第１の積分回路の出力が印加される第２の積分回路
と、前記第２の積分回路の出力が印加され量子化した信
号を出力する量子化器と、前記量子化器の出力信号を１
サンプル遅延前の蓄積データとして前記第１および第２
の積分回路に印加する帰還回路とを備えるノイズシェイ
パであって、前記第１の積分回路の積分動作が、前記１
サンプル遅延前の蓄積データと前記現データと絶対値が
一定値の定数との加算によって実現される不完全積分動
作であって、前記１サンプル遅延前の蓄積データが正の
時は前記定数の符号を負とし、前記１サンプル遅延前の
蓄積データが負あるいは零の時は前記定数の符号を正と
する符号制御回路を有する事を特徴とするノイズシェイ
パ。3. A first integration circuit to which current data is applied,
A second integration circuit to which an output of the first integration circuit is applied
And a quantized signal to which the output of the second integration circuit is applied and quantized.
A quantizer for outputting a signal, and an output signal of the quantizer is set to 1
The first and second data are stored data before the sample delay.
And a feedback circuit applied to the integrating circuit
Wherein the integration operation of the first integration circuit is performed by the first integration circuit.
Wherein the sample delay preceding accumulated data is incomplete integration operation current data and the absolute value is achieved by addition of a constant of predetermined value, when the stored data before the one sample delay is positive sign of the constant A sign control circuit that sets the sign of the constant to be positive when the accumulated data before the one-sample delay is negative or zero.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3315882A JP2822734B2 (en) | 1991-11-29 | 1991-11-29 | Noise shaper |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3315882A JP2822734B2 (en) | 1991-11-29 | 1991-11-29 | Noise shaper |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0722951A JPH0722951A (en) | 1995-01-24 |
| JP2822734B2 true JP2822734B2 (en) | 1998-11-11 |
Family
ID=18070739
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3315882A Expired - Lifetime JP2822734B2 (en) | 1991-11-29 | 1991-11-29 | Noise shaper |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2822734B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB9724713D0 (en) | 1997-11-21 | 1998-01-21 | Procter & Gamble | Delivery systems |
| JP4129811B2 (en) | 2002-04-30 | 2008-08-06 | 株式会社吉野工業所 | Dispensing container |
| JP2009088924A (en) * | 2007-09-28 | 2009-04-23 | Fujitsu Ltd | Method and device for modulating signal, electronic device and signal modulating program |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5911027A (en) * | 1982-07-10 | 1984-01-20 | Fujitsu Ltd | Adaptive differential pcm system |
| JPS6119230A (en) * | 1984-07-05 | 1986-01-28 | Nec Corp | Method and apparatus of over sample coding |
| JPS6184914A (en) * | 1984-10-03 | 1986-04-30 | Sony Corp | Noise shaping filter |
| JPS63238724A (en) * | 1987-03-26 | 1988-10-04 | Nippon Precision Saakitsutsu Kk | D/a converter |
| JPH01112822A (en) * | 1987-10-26 | 1989-05-01 | Nippon Telegr & Teleph Corp <Ntt> | Noise shaping type d/a converter |
| JPH01212123A (en) * | 1988-02-19 | 1989-08-25 | Nippon Telegr & Teleph Corp <Ntt> | Quantizer |
| JPH01221021A (en) * | 1988-02-29 | 1989-09-04 | Sony Corp | Digital signal processing unit |
| JPH01233824A (en) * | 1988-03-14 | 1989-09-19 | Sony Corp | Digital signal processor |
| JPH01254023A (en) * | 1988-04-01 | 1989-10-11 | Matsushita Electric Ind Co Ltd | Oversampling type bit compressor |
| JPH01274510A (en) * | 1988-04-27 | 1989-11-02 | Matsushita Electric Ind Co Ltd | Double integration type noise shaper |
| JPH02309820A (en) * | 1989-05-25 | 1990-12-25 | Sony Corp | Digital signal processor |
| JPH03145822A (en) * | 1989-10-31 | 1991-06-21 | Toshiba Corp | Sigma/delta modulator |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS648729A (en) * | 1987-07-01 | 1989-01-12 | Sony Corp | Da converting circuit |
-
1991
- 1991-11-29 JP JP3315882A patent/JP2822734B2/en not_active Expired - Lifetime
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5911027A (en) * | 1982-07-10 | 1984-01-20 | Fujitsu Ltd | Adaptive differential pcm system |
| JPS6119230A (en) * | 1984-07-05 | 1986-01-28 | Nec Corp | Method and apparatus of over sample coding |
| JPS6184914A (en) * | 1984-10-03 | 1986-04-30 | Sony Corp | Noise shaping filter |
| JPS63238724A (en) * | 1987-03-26 | 1988-10-04 | Nippon Precision Saakitsutsu Kk | D/a converter |
| JPH01112822A (en) * | 1987-10-26 | 1989-05-01 | Nippon Telegr & Teleph Corp <Ntt> | Noise shaping type d/a converter |
| JPH01212123A (en) * | 1988-02-19 | 1989-08-25 | Nippon Telegr & Teleph Corp <Ntt> | Quantizer |
| JPH01221021A (en) * | 1988-02-29 | 1989-09-04 | Sony Corp | Digital signal processing unit |
| JPH01233824A (en) * | 1988-03-14 | 1989-09-19 | Sony Corp | Digital signal processor |
| JPH01254023A (en) * | 1988-04-01 | 1989-10-11 | Matsushita Electric Ind Co Ltd | Oversampling type bit compressor |
| JPH01274510A (en) * | 1988-04-27 | 1989-11-02 | Matsushita Electric Ind Co Ltd | Double integration type noise shaper |
| JPH02309820A (en) * | 1989-05-25 | 1990-12-25 | Sony Corp | Digital signal processor |
| JPH03145822A (en) * | 1989-10-31 | 1991-06-21 | Toshiba Corp | Sigma/delta modulator |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0722951A (en) | 1995-01-24 |
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