JP2821419B2 - Logic simulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a logic simulator, and more particularly to a logic simulator for verifying logic timing of a semiconductor circuit in circuit design.

[0002]

2. Description of the Related Art At present, semiconductor circuits, for example, LSI (L
arge Scale Integrated circuit
(unit: large-scale integrated circuit) or the like, a logic simulation using an electronic computer is performed as verification of the LSI circuit design.

[0003] There are various LSI design methods. In the field of ASICs (ICs for specific applications), for example, a method of combining unit circuits called cells is used.
Designing. Therefore, the ASIC prepares data in units of cells on the layout side and the simulation library side, and performs logic simulation using them.

In a conventional logic simulation performed at the time of circuit design, delay data for each cell, which is a simulation library, is prepared, and a logic simulation for confirming a logic operation and timing analysis is performed on a netlist of an LSI circuit to be verified. Do.

However, for example, Japanese Patent Application Laid-Open No. 1-292472
Since a conventional logic simulator for performing this kind of logic simulation described in Japanese Unexamined Patent Publication (Kokai) No. H10 (Document 1) and the like is made in consideration of only a single cell, it is necessary to connect a cell existing inside the cell to each other. No consideration was given to the capacitance existing between the wiring passing over the cell (hereinafter referred to as the intra-cell wiring and the capacitance between the passing wirings on the cell).

For example, referring to FIG. 4 which shows a flow chart of a conventional logic simulator described in Document 1, this conventional logic simulator first has a circuit design (step S).
In 1), an arbitrary circuit is designed, and a logic simulation with provisional delay is performed as a first logic simulation on a netlist as circuit connection information obtained therefrom (step S2). In this logic simulation with provisional delay, a logic simulation is performed using a simulation library 101 which is delay and timing information in cell units. At this time, the expected length of wiring between a plurality of cells in an LSI chip, that is, the virtual wiring length Is estimated and the provisional wiring capacity related to this is estimated.

After that, in step S3, the layout design of the LSI chip is performed based on the netlist which has been simulated in step S2. The actual wiring length can be estimated from the result of the automatic layout and wiring of the layout design. I can do it.

Next, as a second logic simulation, a logic simulation with a real delay (step S4) is performed using the real wiring capacity estimated from the real wiring length obtained in step S3. As a result, logic simulation can be performed in consideration of the actual wiring capacity, and logic verification can be realized with respect to delay and timing in accordance with the actual LSI.

Finally, based on the specification judgment (step S5), whether there is a large difference between the provisional wiring capacitance and the actual wiring capacitance obtained in steps S2 and S4, and from the simulation result, an error such as a logic error or a timing error. It was verified whether or not there was any, and it was determined whether or not the LSI chip could be manufactured.

As described above, by performing the above verification flow, the operation guarantee of the LSI to be verified is confirmed, and the manufacture of the LSI chip has been started.

However, the actual wiring capacitance is between the wiring 51 existing inside the cell 53 as shown in FIG. 5 and the wiring 52 passing over the cell 53 to connect the cells. The capacitance 54 (capacitance between the wirings passing through the cells in the cell) is ignored.

At present, high speed and high integration of LSI chips are required, and the cell size mounted on LSIs is becoming smaller and smaller. Under such a trend, the accuracy of the simulation library is naturally required to be improved, and in the future, the capacitance between the wirings passing through the wirings in the cells as shown in FIG. 5 cannot be ignored.

However, if all the capacitances between the intra-cell wiring and the on-cell wiring are considered in the conventional logic simulator, the number of simulation libraries is required to be almost infinite, and it is difficult to perform a realistic simulation.
Here, the meaning of infinity means that there is an infinite number of capacitances and the like between the wiring passing over the cell in the LSI chip and the wiring or element existing inside the cell in the combination of the positional relationship. means. That is, cell internal elements,
This means that a library of each cell depending on the on-cell wiring pattern is required.

[0014]

The above-described conventional logic simulator is practical because the number of simulation libraries is required to be almost infinite when all the capacitances between the intra-cell wiring and the passing wiring on the cell are considered. Since a simple simulation is difficult, a library that considers only the single cell is used and the capacitance between the wirings passing through the wiring inside the cell is ignored, so the cell size required for high-speed and high-integration of LSI chips is reduced. There was a drawback that it was not possible to meet the demand for improved accuracy of the corresponding simulation library.

An object of the present invention is to create a simulation library in consideration of the capacitance between wirings passing through cells in a cell, and to reduce the number of data to a value close to that of a conventional library, while keeping the number of data close to that of a conventional library. An object of the present invention is to provide a logic simulator capable of realizing a logic simulation with high accuracy.

[0016]

A logic simulator according to the present invention generates a netlist as connection information of a circuit to be verified designed by a combination of cells as unit circuits.
And a temporary wiring capacitance corresponding to an expected wiring length between the plurality of cells in the circuit to be verified with respect to the netlist using a first library for simulation including delay and timing information in cell units. A second step of executing a first logic simulation including a provisional delay in consideration of the above, and designing a layout of the circuit to be verified based on the netlist that has passed the first logic simulation result, and A third step of obtaining a real wiring length of the first and a second logic simulation including a real delay for the netlist in consideration of the real wiring capacity corresponding to the real wiring length using a first library; A logic simulator for verifying the logic design of the LSI chip which is the circuit to be verified. A third library storing a second library including delay information due to a parasitic capacitance between a wiring passing above the cell and a wiring inside the cell inside the cell in the first library; A fourth library including actual delay information due to a parasitic capacitance between the actual on-cell wiring and the intra-cell wiring for execution of the second logic simulation is selected from the third library based on a layout design result. And a fifth step of performing the following.

[0017]

FIG. 4 shows an embodiment of the present invention.
Referring to FIG. 1, which is similarly shown in a flowchart with common reference characters / numerals attached to the same constituent elements, the logic simulator of this embodiment shown in FIG. In addition, a common library 1 between the layout design of step S3 and step 4 is used.
01 and a grid utilization rate library 12 which is a library of delay information in consideration of the intra-cell wiring and the capacitance between the on-cell wirings for each ratio of the on-cell wiring, and the actual cells obtained from the layout design results. The method further includes a step S6 of selecting the library 13 of the actual delay information in consideration of the capacitance between the internal wiring and the passing wiring on the cell.

In step S6, a grid use rate of the wiring passing over the cell is extracted from the layout design result data in step S61, and an optimal simulation selection library 13 is selected from the grid use rate library 12 based on the grid use rate. Selecting step S62.

Next, the operation of the present embodiment will be described with reference to FIG. 1. First, as in the prior art, at the time of development of an LSI, a designer designs a circuit (step S1) and designs an arbitrary circuit. I do. The logic simulation with temporary delay (step S2), which is the first simulation, is performed on the netlist designed here. In the simulation in step S2, the simulation is performed using the same simulation library 11 as the conventional one. Further, as in the conventional case, a virtual wiring capacitance corresponding to an expected wiring length of a planned wiring between a plurality of cells in an LSI chip is added to a netlist, and a logic simulation is performed to a certain extent closer to an actual device.

Next, in step S2, simulation O
The layout design step S3 at the LSI chip level is performed using the netlist that has become K. The actual wiring length can be estimated from the wiring result after the automatic placement and routing in this layout design, and a final logic simulation with an actual delay in step S4 is performed using the actual wiring length.

Before starting the description of the logic simulation with the actual delay, the outline of the simulation library 11 and the library 12 of the grid utilization rate and the selection library 13 used in step S4, which are the features of the present invention, and their creation. -The extraction method will be described.

The method of creating the simulation library 11 used in the present embodiment will be described with reference to FIG. Information Library 1
Prepare 2 The library 12 calculates the grid usage rate of the wiring passing over the cell of each cell by 0, 50, 100
% Of each cell layout 211, 212, 2
A net list is extracted from the layout data 22 composed of the data 13 and is constituted by delay information obtained by using the extracted net list.

From the library 12 obtained for each ratio of the wiring passing above the cell, a graph 23 of the grid utilization rate and the delay value is obtained.
Get.

For example, as can be seen from the cell layout 213 in which wiring is added on the cell, the wiring passing through the cell is set to the entire grid of the cell as compared with the conventional delay value which does not consider the wiring passing through the cell. In the added 100% library, the delay value is naturally increased because the capacity value is increased. That is, an approximate expression of the slope as shown in the graph 23 is obtained.

The obtained approximate expression, that is, the coefficient, is stored in the conventional simulation library 101 to generate the library 11 of the present embodiment. That is, the library 101 corresponds to the library 11 when the ratio of the wiring passing above the cell is 0%.

As a result, it is possible to realize the simulation library 11 in which the capacitance between the intra-cell wiring and the passing wiring on the cell is taken into consideration, and the data amount is reduced to about the conventional level.

Next, in step S61, the chip internal area 30 is divided (9 in this example) with respect to the layout information of the LSI chip obtained in the layout design step S3, as shown in FIG. The grid utilization rate in the region is calculated. From the grid usage rate information, it is possible to determine the on-cell passing wiring ratio (= grid usage rate) for each cell arranged in each area.

Next, in step S62, step S61
The most appropriate simulation library 13 is selected on the basis of the information obtained in step (1). The selection here means that desired library data is extracted by using an approximate expression (coefficient) in the library 11 corresponding to the selected cell-passing wiring ratio. For example, when the grid utilization rate is 40% in the area 31 of FIG. 3, for the cells arranged in this area, the delay value when the on-cell passing wiring ratio is 40% is calculated by an approximate expression. , Only the desired simulation library 13 is selected.

Next, using the selected simulation library 13, a logic simulation with an actual delay in consideration of the actual wiring capacity (step S4) is performed. here,
As in the prior art, a final LSI chip logic simulation is performed using the actual wiring capacitance estimated in the layout design (step S3), so that the actual wiring capacitance can be considered, and a simulation library closer to the actual device can be used. By using this, it is possible to realize logic verification with higher accuracy than before.

In the prior art, there is a problem that the number of simulation libraries becomes enormous when all the capacitances between the intra-cell wiring and the passing wiring on the cell are taken into consideration. Was not considered at all, but in the present embodiment,
It is possible to make the number of library data in consideration of the parasitic capacitance between the passing wirings on the cell equal to that of the related art.

As a result, it is possible to realize a highly accurate logic simulation corresponding to the high speed and high integration of the currently promoted LSI chip.

Finally, the specification is determined (step S
According to 5), a determination is made as to whether there is a logic error, timing error, or the like in the simulation result. However, it is possible to make a determination (guaranteed operation of the LSI) suitable for the actual device as compared with the related art.

In this embodiment, the method of estimating the grid usage rate by dividing the chip has been described. In addition, the grid usage rate is estimated on a cell basis or on a macro basis such as a set of a plurality of cells and a memory. Thus, a method of selecting the simulation library 13 is also possible. Also,
With regard to the prepared simulation library in consideration of the capacitance between the interconnects passing through the cells, the plurality of simulation libraries 12 for each grid usage rate of each cell layout as shown in FIG. 2 when the storage capacity of the machine is sufficient. It is also possible to use such a method and to select a corresponding library from them.

[0034]

As described above, in the logic simulator of the present invention, the first library stores the second library including the delay information due to the parasitic capacitance between the on-cell wiring and the intra-cell wiring. A third library including the third library and selecting a fourth library including the actual delay information from the third library based on the layout design result, so that the number of data is reduced to about the same as that of the conventional library. By using the third library, there is an effect that a high-accuracy logic simulation can be performed in consideration of a delay variation caused by a capacitance between a wiring in a cell and a wiring passing through a cell.

[0035]

[Brief description of the drawings]

FIG. 1 is a flowchart showing one embodiment of a logic simulator of the present invention.

FIG. 2 is an explanatory diagram showing an example of a method for creating a simulation library used in the logic simulator according to the embodiment.

FIG. 3 is an explanatory diagram illustrating a concept of a grid usage rate.

FIG. 4 is a flowchart showing an example of a conventional logic simulator.

FIG. 5 is an explanatory diagram showing a concept of a parasitic capacitance generated between a wiring in a cell and a wiring passing above a cell.

[Explanation of symbols]

 11, 12, 13, 101 Library 21 Layout data 23 Graph 30 Chip internal area 31 Grid utilization rate 51 Internal wiring 52 Pass-on-cell wiring 53 Cell 211, 212, 213 Cell layout

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-9-198419 (JP, A) JP-A-8-241926 (JP, A) JP-A-5-81365 (JP, A) JP-A-4- 137653 (JP, A) JP-A-7-14927 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 21/82 G06F 17/50

Claims (7)

(57) [Claims] 1. A first step of generating a netlist as connection information of a circuit to be verified designed by a combination of cells as unit circuits, and a first for simulation including delay and timing information of the cell unit. A second step of executing a first logic simulation including a provisional delay in consideration of a provisional wiring capacity corresponding to an expected wiring length between the plurality of cells in the circuit to be verified using the library with respect to the netlist; A third step of performing a layout design of the circuit to be verified based on the netlist that has passed the first logic simulation result to determine an actual wiring length between the plurality of cells; and A second logic simulation including an actual delay in consideration of the actual wiring capacity corresponding to the actual wiring length is performed on the netlist. A logic simulator for verifying the logic design of the LSI chip, which is the circuit to be verified, including a fourth step, wherein a first-library passing wiring on the first library and an intra-cell wiring inside the cell are provided. And a third library storing a second library including delay information due to parasitic capacitance between the third library and the actual library for executing the second logic simulation based on the layout design result. A fifth step of selecting a fourth library including actual delay information due to parasitic capacitance between the pass-on-cell wiring and the intra-cell wiring. 2. A method according to claim 1, wherein the second library is a ratio of an occupied area of the wiring on the cell to an area of the grid area for each of a plurality of grid areas generated by dividing a predetermined unit circuit area. The logic simulator according to claim 1, further comprising: a wiring usage rate; and the delay information for each of the plurality of grid regions calculated from the parasitic capacitance corresponding to the wiring usage rate. 3. The method according to claim 2, wherein the delay information is an approximate relational expression between the grid use rate and the delay time, and the actual delay information is calculated using an actual grid use rate obtained from the layout result. 3. The logic simulator according to claim 1, wherein 4. The method according to claim 1, wherein the fifth step is a step of obtaining an actual grid usage rate, which is the actual grid usage rate, from the layout result, and including the real delay information corresponding to the real grid usage rate. 7. The logic simulator according to claim 1, further comprising a seventh step of selecting a fourth library. 5. The logic simulator according to claim 2, wherein the unit circuit area is the entire circuit to be verified. 6. The logic simulator according to claim 2, wherein the unit circuit area is the cell. 7. The logic simulator according to claim 2, wherein the unit circuit area is a macro which is a set of a plurality of the cells.