JP2814939B2 - Waveform processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform processing apparatus for performing waveform processing such as multiplication and time delay on a generated waveform sample and outputting the processed waveform sample. Things.

[0002]

2. Description of the Related Art Conventionally, in order to process and output input waveform sample data, a waveform processing device such as a digital signal processor (DSP) is conventionally used. A delay RAM for delaying the waveform sample data is provided. In this case, in order to reduce the storage capacity of the delay RAM, the waveform sample data to be delayed is compressed and written, and the waveform sample data delayed for a predetermined time is read and decompressed to obtain the delayed waveform sample data. It has been done to get you.

[0003] Thus, since the compressed waveform sample data having a small data amount is written in the delay RAM, a long delay can be performed by the delay RAM having a small capacity. In addition, when performing a processing process by multiplying the waveform sample data by the level data, a multiplier including a shifter is provided so as to cope with a case where the level data is floating data including an exponent part and a mantissa part. It is provided in a waveform processing device.

[0004]

However, a compression circuit for compressing the waveform sample data for writing to the delay RAM and a circuit for expanding and returning the compressed waveform sample data read from the delay RAM are provided. However, there is a problem that the circuit scale of the waveform processing apparatus for processing the waveform sample data is increased.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a waveform processing device which can use both a compression circuit and an expansion circuit.

[0006]

In order to achieve the above object, a waveform processing apparatus according to the present invention comprises a waveform sample generating means for generating waveform sample data which is linear data, and a level data which is floating data. Generating means, a delay memory for delaying data, a multiplying means having a shifter, and generating new waveform sample data by multiplying the waveform sample data by the level data set as the floating data. In this case, the multiplying means multiplies the waveform sample data by mantissa data in the level data, and shifts the multiplication result by the shifter based on the exponent data in the level data. Control, and when writing the waveform sample data to the delay memory, And a control unit for performing control such that the waveform sample data is logarithmically compressed using the multiplication means by shifting the waveform sample data, and then written to the delay memory. .

[0007]

According to the present invention, compression of waveform sample data and expansion of the compressed waveform sample data are performed by using a shifter provided in a multiplier for level multiplication. Therefore, compression is performed by a multiplier having a shifter. The circuit can be configured to serve as both a circuit and a decompression circuit. Therefore, the circuit scale of the waveform processing device can be reduced.

[0008]

FIG. 1 is a block diagram showing the configuration of an electronic musical instrument in which a waveform processing device according to the present invention is provided as a waveform processing unit in a sound source. In FIG. 1, reference numeral 1 denotes a microprocessor (CPU) that performs a main routine process and an interrupt process by transmitting and receiving data via a CPU bus 11 based on a CPU program stored in a ROM 2;
Reference numeral 2 denotes a ROM (Read Only Memory) in which a CPU program and preset tones are stored. 3 denotes a RAM (Random Access Memory) used as a storage area of tone data stored by a user and a work area of the CPU. Is a panel switch which is operated when setting is made, 5 is a display for displaying a tone color number and the like, and 6 is a keyboard which is a performance operator.

Further, reference numeral 7 denotes a sound source for generating waveform sample data based on the transferred tone color information, note information, volume information and the like, 8 a delay DRAM used by the sound source 7 for delaying the waveform sample data, and 9 a sound source. 7 converts the waveform sample data output from 7 into an analog signal.
An analog converter (DAC) is a sound system that produces a tone signal converted into a 10 analog signal from a speaker.

In the electronic musical instrument configured as described above,
If the keyboard 6 is depressed, the note-on is executed by the CPU.
The tone channel, tone volume information, note information, and the like set for the tone channel are transferred to the sound source 7. The sound source 7 generates and outputs waveform sample data in a built-in waveform processing unit based on the transferred information. The generated waveform sample data is converted into an analog signal by the DAC 9 and supplied to the sound system 10 so that a tone is generated. Note that the effect information is also transferred to the sound source 7, and the waveform sample data generated in the built-in waveform processing unit is processed based on the effect information.

Next, FIG. 2 is a block diagram showing a detailed configuration of the sound source 7. The CPU bus 11 is connected to the sound source 7 and a delay DRAM 8 is connected to the sound source 7.
In this figure, various information transferred to the sound source 7 via the CPU bus 11 is stored in the control register 21. The control register 21 supplies necessary information to the waveform generator 22, the multiple function generator 24, and the waveform calculator 23 according to the present invention. In the sound source 7, for example, since the number of sounding channels is 32, the waveform sample data of each of the 32 channels is generated by the time division processing, and the control register 21 is synchronized with the processing timing of each channel.
The necessary information of each channel is given to each unit from the.

The waveform generator 22 is supplied with timbre information, note information, and the like, and based on this information, generates waveform sample data (WAVE) in a time-division manner.
3 is output. A volume parameter and the like are given to the multiple function generator 24, and six envelope data (EGO) are provided for each time-division channel based on this information.
UT) are generated in a time-division manner and output to the waveform calculator 23. This envelope data is floating data composed of an exponent part and a mantissa part. Further, the waveform calculation unit 23 performs processing such as filter calculation, level multiplication, and output accumulation on the waveform data of each time division channel provided from the waveform generator 22 according to the microprogram. Performs an effect process such as a chorus effect and a reverb effect to generate new waveform sample data.
C / O) 25 to the DAC 9.

In this case, if it is necessary to delay the waveform sample data in the effect processing such as the chorus effect and the reverb effect, the waveform arithmetic unit 23 converts the address MA and the compressed waveform sample data MWD into
The waveform sample data MWD supplied to the delay DRAM 8
After a predetermined time, the same address MA as that at the time of writing is supplied to the delay DRAM 8, and the compressed waveform sample data MRD is read and expanded to obtain waveform sample data delayed for a predetermined time. I have. The MP provided in the waveform calculation unit 23
M23-1 is a microprogram memory for storing a microprogram of a digital signal processor (DSP) constituting the waveform operation unit 23.
1 is a temporary register for temporarily storing waveform sample data, and CRAM 23-2 is a coefficient memory for storing operation coefficients.

FIG. 3 is a block diagram showing a detailed configuration of the waveform calculator 23. In the waveform calculator 23, a frequency component control process (filter process) using a DCF filter is performed, and envelope data is added to waveform samples. A volume change control process for multiplying (level multiplication), a channel accumulation process for accumulating each channel data (output accumulation), and a sound effect control process (effect process) are performed. In this figure, a multiplier 33 multiplies 10-bit data by 24-bit data, 10-bit data is selected and input by a selector A31, and 24-bit data is selected by a selector B32. Has been entered. The selector (A31) stores the coefficient (COE) read from the coefficient memory CRAM23-2.
F), the calculation result (YM), and the data to be multiplied by the envelope data (EGOUT) generated by the plurality of function generators 24 are supplied as floating data or linear data, and a temporary register (TRAM) is provided to the selector B32. ) 41, or output latch L
From 24, the waveform sample data converted to linear data to be multiplied is supplied.

When the data selected by the selector A31 is floating data including an exponent part and a mantissa part, the exponent part data of the upper 5 bits is supplied to the variable shifter 37 via the selector D. Along with
The lower 10 bits of the mantissa data are input to the multiplier 33 and multiplied by the waveform sample data selected by the selector B32. The multiplication result output from the multiplier 33 is input to the variable shifter 37 via the selector C34, and is shifted up / down according to the 5-bit exponent part data. New waveform sample data obtained by multiplying the waveform sample data) and the floating data (for example, envelope data) can be obtained. This new waveform sample data is input to the TRAM 41 via the selector F38 and the 25-bit adder / subtractor 39, and is temporarily stored. Note that the envelope data EGOUT is
Is multiplied by the output latch L at the selector B32.
The filtered waveform sample data stored in 24 is selected.

In the multiplier 33, the multiplied output is 4
Since the data is output after being delayed by the clock, the data from the selector B32 is transferred to the selector C3 without being delayed by four clocks.
4, the detour L1 that bypasses the multiplier 33
Is used. Further, the selector D35 selects the shift amount of the variable shifter 37, and the selector E35
Reference numeral 36 is used to select data to be shifted. When the linear data is multiplied by using the multiplier 33, there is no exponent part data and the variable shifter 37 becomes unnecessary, so that the selector E36 and the variable shifter 37 are used.
Is multiplied by a selector F3 via a bypass L2 that bypasses
8 may be supplied.

The waveform sample data WAVE output from the waveform generator 22 is input to the selector G40. When the number of sounding channels is 32, the waveform sample data WAVE is 32 channels. WAVE is input in a time-division manner. Then, the addition / subtraction output data added / subtracted by the addition / subtraction unit 39 is input to the TRAM 41 and stored. When the selector G40 selects the output from the adder / subtractor 39, a loop is formed by the selector G40 and the adder / subtractor 39, so that the accumulation can be performed.
Thus, the waveform sample data output from the selector F38 can be accumulated.

The output of the adder / subtractor 39 is input to an exponent generator 42, and exponent data EXP1 and EXP2 are generated based on the input waveform sample data. The generated exponent part data EXP2 is input to the variable shifter 37 via the selector D35. The exponent part data EXP2 passes through the exponent generator 42 and converts the linear data before compression input to the variable shifter 37 via the selector E36. , The mantissa part data is generated by shifting up with the exponent part data EXP2, and the delay DRAM interface (I
/ O) 44. At this time, the exponent generator 42 outputs exponent part data EXP1 having a sign opposite to that of EXP2 to the DR for delay.
The data is supplied to the AM I / O 44, and the exponent part data EXP1 is combined with the mantissa part data to form a delay DRAM I / O 44.
Output from O44.

The exponent generator 42 performs an EXP so that the mantissa data resulting from the shift-up operation can omit upper bits having the same value as the sign of the linear data before compression.
2, EXP1 is generated. Thus, the DR for delay
The floating data output from the AM I / O 44 is waveform sample data that has been subjected to compression processing. The compressed waveform sample data is divided into two data of 8 bits each, and becomes write data DMWD to be written to the DRAM 8 for delay. The write data DMWD is floating data composed of 12 bits of mantissa data output from the variable shifter 37 and 16 bits of exponent data EXP1 of 4 bits.

Further, the output of the adder / subtractor 39 is also input to a multiplier generator 43, and is combined with the exponent part data EXP1 from the exponent generator 42 to obtain a calculation result YM which is converted into 15-bit floating data. Have been. The read data DMRD read from the delay DRAM 8 after a predetermined time is input to the DRAM I / O 45, and the separated mantissa data is input to the variable shifter 37 via the selector E36. The separated exponent data EXP1 is supplied to the variable shifter 3 via the selector D35.
7, the mantissa data is shifted down. Therefore, the read data DMRD is expanded to be linear waveform sample data delayed by a predetermined time and stored in the TRAM 41. Note that the exponent part data generated by the exponent generator 42 corresponds to the number of “0” from the upper bit to the first appearance of “1”.

In the thus configured waveform calculation unit 23, the waveform sample data WAVE of the 32 channels are processed by the time division processing as described above, and each of them is multiplied by 6 levels to obtain the 32 channels. Six outputs are generated by accumulating the minute waveform sample data. These outputs are output from the waveform calculation unit 23 for each sampling clock of the DAC 9. In other words, the waveform calculation unit 23 performs the time division processing based on the sampling clock of the DAC 9, and performs the time division processing in units of a clock cycle obtained by dividing the sampling clock cycle of the DAC 9 by 768, for example. The 768 clocks are the number of clocks for 32 channels assigned to each sounding channel by 24 clocks.

FIG. 4 shows a timing chart of the waveform calculating section 23. In this timing chart, only 24 clocks for one tone generation channel are shown. As shown in this figure, in one sounding channel, the processing of filter operation, time division channel (CH) output accumulation, effect operation 1 and effect operation 2 are sequentially performed in quadruple every three clocks. For this reason,
The multiplier 33 and the adder / subtractor 39 are provided with delay means for four clocks indicated as 4D, respectively.

As described above, the filter calculation and the time-division CH output accumulation performed for each sounding channel are performed for one sounding channel by six clocks, while the effect calculation 1 and the effect calculation 2 are different from the sounding channel. Since they are irrelevant, the operation is performed by 192 clocks respectively allocated in the sampling clock cycle of the DAC 9, and six clocks among them are shown in FIG. In this allocated clock, the microprogram operation of effect calculation 1 and effect calculation 2 each consisting of 192 steps is performed one by one. Also, DRAM for delay
8 can be accessed twice with 24 clocks.
Since the delay DRAM 8 is accessed in the effect operation 1 or the effect operation 2, the delay DRAM 8 is accessed once every three steps when viewed from the microprogram side.
Data can be written to or read from the RAM 8.

Next, as an example, FIG. 5 is a table showing the processing content of time-division CH output accumulation in the waveform computing section 23. In this table, as shown as (6), in the sixth step of the previous channel, the waveform sample data TRAM (D2), which has been subjected to the filter operation processing described later, of the tone generation channel to be processed in the TRAM 41 is stored in the output latch L24. Shall be In the first step, the volume data EG (REV) for reverb and the waveform sample data from the output latch L24 are multiplied by the multiplier 33 to obtain a multiplied output MPYO. At the same time, the multiplication output MPYO multiplied last time (four clocks earlier) and the accumulated reverb data TRAM (REV) from the TRAM 41 are added by the adder / subtractor 39 to newly accumulate the reverb TRAM. (REV) data is generated and stored in the TRAM 41.

Next, in the second step, the L channel,
In the third step, the process for pan control of the R channel is performed. In the second step, the volume data EG (DL) and the waveform sample data from the output latch L24 are multiplied by the multiplier 33 to obtain a multiplied output. MPYO. At the same time, the multiplied output MPYO multiplied last time and the TRAM 41
The accumulated data TRAM (DL) is added by the adder / subtractor 39 to generate newly accumulated pan L-channel TRAM (DL) data.
1 is stored. In the third step, the same processing as in the second step is performed, and newly accumulated R channel TRAM (DR) data for pan is generated and TR.
Stored in AM41. In addition, “D” of (DL) and (DR) indicates that it is dry (output as it is without passing through the effector).

Further, in the fourth step, the L channel,
In the fifth step, processing for chorus control of the R channel is performed. In the fourth step, the volume data EG (CH
L) and the waveform sample data from the output latch L24 are multiplied by a multiplier 33 to obtain a multiplied output MPYO. At the same time, the multiplied outputs MPYO and TR
Data TRAM for accumulated chorus from AM41
(CHL) is added by the adder / subtractor 39 to newly accumulate an L-channel TRAM (CHL) for chorus.
Data is generated and stored in the TRAM 41. Also,
In the fifth step, the same processing as in the fourth step is performed, and the newly accumulated chorus R channel TRA
M (CHR) data is generated and stored in the TRAM 41.

Then, in the sixth step, the volume data EG
(VA) and the waveform sample data from the output latch L24 are multiplied by a multiplier 33 to obtain a multiplied output MPYO. At the same time, the multiplied outputs MPYO and T
The data TRAM (VA) for variation accumulated from the RAM 41 is added by the adder / subtractor 39, and
TRAM (VA) for newly accumulated variations
The data is stored in the TRAM 41.

Here, since the selector G40 outputs "0" at the timing of the first of the 32 time-division channels, six data in the TRAM 41, that is, TRAM (REV) and TRAM (D
L), TRAM (DR), TRAM (CHL), TRA
M (CHR) and TRAM (VA) are filtered sample data TRAM ₁ (D2) of the first channel.
, Each volume data EG ₁ (REV) of the first channel,
EG ₁ (DL), EG ₁ (DR), EG ₁ (CHL),
Six multiplication results obtained by multiplying EG ₁ (CHR) and EG ₁ (VA) are written. Subsequently, at the timing of the second channel, six multiplication results of six sound volume data EG ₂ (REV) to EG ₂ (VA) are added to the value and the waveform sample data TRAM ₂ (D2) of the second channel. Then, the six accumulated values of the first two channels are written to TRAM (REV) to TRAM (VA). In this manner, the accumulation progresses sequentially, and at the timing of the 32nd channel, six data, TRAM (RE
As V) to TRAM (VA), data of each sounding channel for 32 channels is accumulated for six systems, and the six accumulation results are supplied as input values for effect calculation 1 and effect calculation 2.

Next, FIG. 6 shows a DCF algorithm of the DCF filter, and FIG. 7 shows a chart of the waveform calculation processing of the DCF filter. Therefore, a DCF algorithm for each time-division channel executed by the waveform calculation unit 23 will be described with reference to FIG. In step 1, the coefficient data EG (-q) and the data TRAM (D1) read from the TRAM 41 are multiplied by the multiplier 33 to obtain a multiplied output MPYO. At the same time, the multiplied output MPYO multiplied last time (four clocks ago) and the input data WAVE are added by the adder / subtractor 39 to form an adder / subtractor output FAO. In this first step, a third coefficient multiplier K3 is added to the output of the first delay means D1 for delaying one sample.
Is multiplied by a coefficient q, and the first subtracter A1 subtracts the input data WAVE.

Next, in the second step, (-1) is TR
The data TRAM (D2) read from the AM 41 is multiplied to obtain a multiplied output MPYO. At the same time, the multiplication output MPYO and the addition / subtraction output FAO, which have been multiplied last time, are added by the addition / subtraction unit 39, and the addition / subtraction output TRAM (X) is added.
Is stored in the TRAM 41. In this second step,
It has been calculated that the output of the second delay means D2 which performs one sample delay from the output of the first subtractor A1 is subtracted by the second subtractor A2. In the subsequent third step, the multiplier 33
, And at the same time, the TRAM (D1) read from the TRAM 41 in the adder / subtractor 39.
And "0" are added to form an addition / subtraction output FAO. In the third step, the first adder A3 supplies the first
The data from the delay means D1 is created.

Further, in the fourth step, the coefficient data EG
(K) and data TRAM read from TRAM 41
(X) is multiplied by a multiplier 33 and a multiplied output MPY
O. At the same time, the multiplication output MPYO multiplied last time and the addition / subtraction output FAO data generated in the third step are added by the addition / subtraction unit 39, and the addition / subtraction output TR
AM (D1) is stored in TRAM41. In the fourth step, it is calculated that the output of the second subtractor A2 is multiplied by the coefficient K by the first multiplier K1 and added to the output of the first delay means D1 by the first adder A3.

Next, in a fifth step, the multiplier 33
The other processing is performed at the same time, and at the same time, the TRAM (D2) read from the TRAM 41 by the adder / subtractor 39.
And "0" are added to form an addition / subtraction output FAO. In this fifth step, the second adder A4
The data from the delay means D2 is created. In a subsequent sixth step, the multiplier 33 multiplies the coefficient EG (K) by the data TRAM (D1) read from the TRAM 41 to obtain a multiplied output MPYO. At the same time, the multiplication output MPYO multiplied last time and the addition / subtraction output FAO data generated in the fifth step are added by the addition / subtraction unit 39, and the addition / subtraction output TRAM (D2) is stored in the TRAM 41.

In the sixth step, it is calculated that the output of the first adder A3 is multiplied by the coefficient K by the second multiplier K2, and the output of the second adder A4 is added to the output of the second delay means D2. ing. As a result, the waveform sample data filtered by the DCF filter is stored in the TRAM.
41 will be stored as TRAM (D2),
In the algorithm shown in FIG. 6, the data is output from the second adder A4. Note that the coefficient data EG is treated as negative dB (decibel) data in the waveform calculator 23.

As described above, in the waveform calculating section 23 of the present invention, when the floating data composed of the exponent part data and the mantissa data and the linear data are multiplied by the multiplier 33 for level control, By providing the bypass L2 in the variable shifter 37 that shifts the multiplication output obtained by multiplying the mantissa data and the linear data by the exponent data, and selecting the multiplication output to pass through the bypass L2, the variable shifter 37 is selected. By using the variable shifter 37 in a state where is empty, the write data DMWD to be written to the delay DRAM 8 can be compressed simultaneously with the multiplication operation. Similarly, when the read data DMRD read from the delay DRAM 8 is expanded by the variable shifter 37, the multiplication operation and the expansion operation are performed simultaneously by bypassing the multiplication data from the multiplier 33 using the bypass L2. Like that. Further, since the data compression means and the data decompression means are shared, the circuit size of the waveform calculation unit 23 can be reduced.

[0035]

As described above, according to the present invention, the shifter built in the multiplier used for performing the operation of the level control is used as the compression means for compressing the sample data. Since it is also used as a decompression means for decompression, a data compression circuit and a data decompression circuit can be configured by a multiplier with a shifter for level control. Furthermore, since the detour is provided in the shifter, the multiplication operation and the data compression / expansion processing can be performed simultaneously, and the circuit size of the waveform processing device can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an electronic musical instrument provided with a waveform processing device of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of a sound source incorporating a waveform processing device of the present invention.

FIG. 3 is a block diagram illustrating a detailed configuration of a waveform calculation unit that is an embodiment of the waveform processing device according to the present invention.

FIG. 4 is a timing chart of the waveform processing unit of the present invention.

FIG. 5 is a table showing the content of arithmetic processing for time-division CH output accumulation by the waveform processing unit of the present invention.

FIG. 6 is a diagram illustrating an algorithm of a DCF filter.

FIG. 7 is a table showing the contents of calculation processing of a filter calculation of the waveform processing unit of the present invention.

[Explanation of symbols]

1 Microprocessor (CPU), 2 ROM, 3
RAM, 4 panel SW, 5 display, 6 keys, 7
Sound source, 8 delay DRAM, 9 DAC, 10 sound system (SS), 11 CPU bus, 21 control register, 22 waveform generator, 23 waveform calculator, 24 multiple function generator, 25 DAC I / O, 33 multiplier ,
37 variable shifter, 39 adder / subtracter, 41 temporary register (TRAM), 42 exponent generator, L1, L2
Detour

Claims (1)

(57) [Claims] 1. A waveform sample generating means for generating waveform sample data which is linear data, a level generating means for generating level data which is floating data, a delay memory for delaying data, and a shifter And multiplying the waveform sample data by the level data set as the floating data to generate new waveform sample data. In the multiplying means, the multiplying unit adds the mantissa in the level data to the waveform sample data. When multiplying the partial data and controlling the result of the multiplication by the shifter based on the exponent part data in the level data, and writing the waveform sample data to the delay memory, By shifting the waveform sample data, Waveform processing apparatus characterized by after performing a logarithmic compression of the waveform sample data using means, and a control section for controlling to write to the delay memory.