JP2806774B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2806774B2 JP2806774B2 JP5338814A JP33881493A JP2806774B2 JP 2806774 B2 JP2806774 B2 JP 2806774B2 JP 5338814 A JP5338814 A JP 5338814A JP 33881493 A JP33881493 A JP 33881493A JP 2806774 B2 JP2806774 B2 JP 2806774B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- package
- chip capacitor
- semiconductor device
- semiconductor package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特
に、半導体パッケージの小型化及び、高密度化に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to miniaturization and high density of a semiconductor package.
【０００２】[0002]
【従来の技術】まず、従来の半導体パッケージに素子を
実装した例として、チップコンデンサーをパッケージ上
に実装した例を図４に示し、また、図４におけるＢ−Ｂ
´線断面図を図５に示す。このチップコンデンサーは、
外部から供給される電源に高調波のノイズが重なった
時、そのノイズを除去し、ＬＳＩの誤動作を防止するた
めに実装するものである。これらの従来の構成は半導体
パッケージ（１）上にチップ（２）、チップコンデンサ
ー（４）とパッケージの中央部にチップを実装のための
キャビティ（８）、その周囲にボンディングステッチ
（７）を有し、その外側にコンデンサ等の素子接続用の
引きだしパッド（１０）からなる。次に組立て手順を説
明する。まず、目的のチップ（２）をキャビティ（８）
にＡｕ−Ｓｉ又は銀ペーストを用いてマウントし、各端
子にＡｌ線のボンディングを行う。その後キャップ等を
用い封入を行ない、組立が終了する。その後、チップコ
ンデンサー（４）をパッケージ上の引き出しパッド（１
０）に半田等を用いて接着する。2. Description of the Related Art First, as an example of mounting a device on a conventional semiconductor package, FIG. 4 shows an example in which a chip capacitor is mounted on a package, and FIG.
FIG. This chip capacitor is
When harmonic noise is superimposed on a power supply supplied from the outside, the noise is removed to prevent malfunction of the LSI. These conventional structures have a chip (2) on a semiconductor package (1), a chip capacitor (4), a cavity (8) for mounting the chip in the center of the package, and a bonding stitch (7) around the cavity. A pad (10) for connecting a device such as a capacitor is provided on the outside thereof. Next, an assembling procedure will be described. First, insert the target chip (2) into the cavity (8)
Is mounted using Au-Si or silver paste, and Al terminals are bonded to each terminal. Thereafter, sealing is performed using a cap or the like, and the assembly is completed. Thereafter, the chip capacitor (4) is connected to the lead-out pad (1) on the package.
0) is bonded using solder or the like.
【０００３】[0003]
【発明が解決しようとする課題】以上述べたように、従
来の技術では、チップコンデンサーを接着する場合、図
４に示すように、チップコンデンサー用引き出しパッド
をパッケージ上に形成し、チップの横に平面的に接着し
ていた。そのため、引き出しパッドに必要な領域を別に
確保しなければならず、パッケージ面積の大型化をもた
らし、高密度化の低下の要因となっていた。また、チッ
プコンデンサーをキャビティ周辺に装着するため引き出
しリードが長くなり、配線抵抗が高くなり、チップコン
デンサーの効果の低下をもたらしていた。なお、従来技
術して挙げられてる特開昭５９−１１１３５０号では、
キャップにチップコンデンサーを装着する例があるが、
この例ではパッケージの小型化は出来るもののリード引
きまわし距離を短くすることは出来ないという問題があ
る。As described above, in the prior art, when a chip capacitor is bonded, a lead pad for a chip capacitor is formed on a package as shown in FIG. It was glued flat. For this reason, a necessary area for the drawer pad must be separately secured, which results in an increase in the package area and a reduction in the density. Further, since the chip capacitor is mounted around the cavity, the lead lead becomes long, the wiring resistance increases, and the effect of the chip capacitor is reduced. In Japanese Patent Application Laid-Open No. 59-111350, which is cited as a prior art,
There is an example of attaching a chip capacitor to the cap,
In this example, there is a problem that the size of the package can be reduced, but the lead routing distance cannot be reduced.
【０００４】[0004]
【課題を解決するための手段】本発明は、能動素子およ
び／または受動素子を搭載可能で、前記各々の素子と電
気的接続可能な配線パタ−ンを有するＴＡＢ（Ｔａｐｅ
ＡｕｔｏｍａｔｅｄＢｏｎｄｉｎｇ）テ−プを半導体
パッケ−ジ内のキャビティ上かつキャップ内に備えたこ
とを特徴とする半導体装置であり、この半導体装置にお
いて、受動素子としてチップコンデンサ、抵抗、インダ
クタンスを備えたことを特徴とするものであり、能動素
子としてトランジスタ、ダイオ−ド、ペルチェ素子を備
えたことを特徴とするものであり、また、ＴＡＢテ−プ
の代わりにセラミック配線基板、又はプリント配線基板
を備えたことを特徴とするものである。SUMMARY OF THE INVENTION The present invention provides a TAB (Tape) having a wiring pattern on which an active element and / or a passive element can be mounted and which can be electrically connected to each of the elements.
(Automatic Bonding) Tape is provided on the cavity in the semiconductor package and in the cap, and the semiconductor device is provided with a chip capacitor, a resistor, and an inductance as passive elements. Wherein a transistor, a diode, and a Peltier element are provided as active elements, and a ceramic wiring board or a printed wiring board is provided in place of the TAB tape. It is characterized by the following.
【０００５】[0005]
【作用】本発明の半導体装置においては、マウント及
び、ボンディングしたチップの上にチップコンデンサー
などの素子を形成したＴＡＢテープを立体的に重なるよ
うに装着しているので半導体パッケージ自身の小型化、
高密度化を図ることができるものである。In the semiconductor device of the present invention, a TAB tape having elements such as chip capacitors formed thereon is mounted on the mount and the bonded chip so as to be three-dimensionally overlapped, so that the semiconductor package itself can be miniaturized.
It is possible to increase the density.
【０００６】[0006]
【実施例】次に本発明の実施例について図面を参照して
説明する。Next, an embodiment of the present invention will be described with reference to the drawings.
【実施例１】図１は本発明の第１の実施例であり、図２
は図１のＡ−Ａ´線における断面図である。また本発明
の第１実施例の組立フローを図３（ａ）〜（ｄ）に示
す。図１、図２に示すように、ＴＡＢテープ（３）を半
導体用パッケージ（１）内のキャビティー（８）上かつ
キャップ内に備えているもので、ピン（６）を有する半
導体パッケージ（１）上にチップ（２）を設けている。
半導体パッケージ（１）のボンディングステッチ（７）
の周囲に、ＴＡＢ用接続リード（５）を形成し、引きだ
しパッド（１０）にチップコンデンサー（４）のついた
ＴＡＢテープ（３）をパッケージに装着されている構成
である。Embodiment 1 FIG. 1 shows a first embodiment of the present invention, and FIG.
FIG. 2 is a sectional view taken along line AA ′ of FIG. FIGS. 3A to 3D show an assembly flow according to the first embodiment of the present invention. As shown in FIGS. 1 and 2, a TAB tape (3) is provided on a cavity (8) in a semiconductor package (1) and in a cap, and has a semiconductor package (1) having pins (6). ) Is provided with a chip (2).
Semiconductor package (1) bonding stitch (7)
A TAB connection lead (5) is formed around the TAB tape, and a TAB tape (3) with a chip capacitor (4) attached to a lead pad (10) is attached to the package.
【０００７】次に、本発明の第１の実施例のものの製造
方法を図３（ａ）〜（ｄ）を用いて説明する。まず、目
的のチップ（２）を半導体用パッケージ（１）内のケー
スキャビティ（８）にＡｕ−Ｓｉ又は銀ペーストを用い
てマウントし、Ａｌ線でボンディングを行う（図３
（ａ））。次いで、引きだしパッド（１０）にチップコ
ンデンサー（４）のついたＴＡＢテープ（３）を、半導
体用パッケージ（１）内のキャビティー（８）上かつキ
ャップ内で半導体パッケージ（１）のボンディングステ
ッチ（７）の周囲に、ＴＡＢ用接続リード（５）に圧着
する。このとき、チップコンデンサーの効果を上げるた
め、チップコンデンサー（４）とチップ（２）の間の引
きまわし距離を短くするため、チップコンデンサーはＴ
ＡＢテープ（３）の端の方に付けておく（図３（ｂ），
（ｃ））。本発明のパッケージを真上から見た場合、チ
ップコンデンサー（４）はチップ（２）と重なるように
配置される構造となる。最後にキャップ（９）をＡｕ−
Ｚｎシール膜により封入する（図３（ｄ））。Next, a method of manufacturing the first embodiment of the present invention will be described with reference to FIGS. First, the target chip (2) is mounted on the case cavity (8) in the semiconductor package (1) using Au-Si or silver paste, and is bonded with an Al wire (FIG. 3).
(A)). Next, a TAB tape (3) having a chip capacitor (4) attached to the extraction pad (10) is bonded to the bonding stitch () of the semiconductor package (1) on the cavity (8) in the semiconductor package (1) and in the cap. Around 7), crimp to TAB connection lead (5). At this time, in order to increase the effect of the chip condenser, the chip condenser is set to T in order to shorten the routing distance between the chip condenser (4) and the chip (2).
Attach it to the end of the AB tape (3) (FIG. 3 (b),
(C)). When the package of the present invention is viewed from directly above, the chip capacitor (4) has a structure arranged so as to overlap the chip (2). Finally, the cap (9) is Au-
It is sealed with a Zn seal film (FIG. 3D).
【０００８】例えば、ピン（６）ピッチ１．２８ｍｍで
１５ｍｍ口のチップ（２）を実装する５２８ピンパッケ
ージの場合、従来の（図５のチップコンデンサー
（４））チップコンデンサーの取り付け領域（片側０．
５ｍｍずつ）が不要になるため５ｃｍ口のサイズを４ｃ
ｍ口に小型化できる。また、２次的な効果としてＴＡＢ
テープ（３）の端にチップコンデンサーつけることが出
来るのでチップコンデンサー（４）のリード引きまわし
距離を約６ｍｍから約２ｍｍに低減でき、配線抵抗を約
１／３に抑えることが出来るので、チップコンデンサー
の効果を上げる。[0008] For example, the pin (6) when the pitch 528 pin package implementing the 15mm opening of the chip (2) by 1.28 mm, conventional (chip capacitor (4 of FIG. 5)) attachment region of the chip capacitors (one side 0 .
(5mm each) becomes unnecessary, so the size of 5cm mouth is 4c
It can be reduced in size in m opening. As a secondary effect, TAB
Since the chip capacitor can be attached to the end of the tape (3), the lead routing distance of the chip capacitor (4) can be reduced from about 6 mm to about 2 mm, and the wiring resistance can be suppressed to about 1/3. Increase the effect.
【０００９】[0009]
【実施例２】また、第２の実施例として、ＴＡＢテープ
（３）上に終端抵抗又はインダクタンスを接着する。パ
ッケージ構造や装着方法は、第１の実施例と同様であ
り、図は、省略する。以下同様にしてＴＡＢ上にトラン
ジスタ、ダイオードなどの能動素子、また配線などを形
成することも出来る。また、ＴＡＢテープの代わりにセ
ラミック板、プリント基板を備えることも出来る。Embodiment 2 As a second embodiment, a terminating resistor or inductance is adhered on a TAB tape (3). The package structure and mounting method are the same as in the first embodiment, and the drawings are omitted. In the same manner, an active element such as a transistor and a diode, a wiring, and the like can be formed on the TAB. Further, a ceramic plate or a printed circuit board can be provided instead of the TAB tape.
【００１０】[0010]
【発明の効果】以上説明したように、本発明によれば、
素子をパッケージのキャビティー内にＴＡＢテープを用
いて立体的に形成するので半導体パッケージ自身の小型
化を図ることができ、引き出しパッドに必要な領域を別
に確保する必要がなく、高密度化が図れるものである。
また、引き出しリードが短くすむので、配線抵抗を低く
抑えることが出来るので、チップコンデンサーの効果を
上げることも出来るという効果を奏するものである。As described above, according to the present invention,
Since the element is formed three-dimensionally in the cavity of the package using a TAB tape, the size of the semiconductor package itself can be reduced, and it is not necessary to secure a separate area required for a lead-out pad, and high density can be achieved. Things.
Further, since the length of the lead-out lead can be shortened, the wiring resistance can be suppressed low, so that the effect of the chip capacitor can be enhanced.
【図１】 本発明の実施例の半導体パッケージを示す
図。FIG. 1 is a diagram showing a semiconductor package according to an embodiment of the present invention.
【図２】 図１のＡ−Ａ´線における断面図。FIG. 2 is a sectional view taken along line AA ′ of FIG.
【図３】 （ａ）〜（ｄ）本発明の実施例の組立てフロ
ーを示す図。FIGS. 3A to 3D are views showing an assembly flow of the embodiment of the present invention.
【図４】 従来の半導体パッケージの例。FIG. 4 is an example of a conventional semiconductor package.
【図５】 図４のＢ−Ｂ´線における断面図。FIG. 5 is a sectional view taken along line BB ′ of FIG. 4;
１：半導体パッケージ ２：チップ ３：ＴＡＢテープ ４：チップコンデンサー ５：接続リード ６：ピン ７：ボンディングステッチ ８：キャビティ ９：キャップ １０：引き出しパッド 1: Semiconductor package 2: Chip 3: TAB tape 4: Chip capacitor 5: Connection lead 6: Pin 7: Bonding stitch 8: Cavity 9: Cap 10: Pull-out pad
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 25/00 H01L 21/60──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 25/00 H01L 21/60
Claims (4)
可能で、前記各々の素子と電気的接続可能な配線パタ−
ンを有するＴＡＢテ−プを半導体パッケ−ジ内のキャビ
ティ上かつキャップ内に備えたことを特徴とする半導体
装置。1. A wiring pattern on which an active element and / or a passive element can be mounted and which can be electrically connected to each of the elements.
A TAB tape having a pattern is provided on a cavity in a semiconductor package and in a cap.
抗、インダクタンスを備えたことを特徴とする請求項１
に記載の半導体装置。2. A passive element comprising a chip capacitor, a resistor, and an inductance as passive elements.
3. The semiconductor device according to claim 1.
ド、ペルチェ素子を備えたことを特徴とする請求項１に
記載の半導体装置。3. A transistor or a diode as an active element.
2. The semiconductor device according to claim 1, further comprising a Peltier element.
基板、又はプリント配線基板を備えたことを特徴とする
請求項１、２、または３のいずれかに記載の半導体装
置。4. The semiconductor device according to claim 1, further comprising a ceramic wiring board or a printed wiring board instead of the TAB tape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5338814A JP2806774B2 (en) | 1993-12-02 | 1993-12-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5338814A JP2806774B2 (en) | 1993-12-02 | 1993-12-02 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07161923A JPH07161923A (en) | 1995-06-23 |
| JP2806774B2 true JP2806774B2 (en) | 1998-09-30 |
Family
ID=18321709
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5338814A Expired - Lifetime JP2806774B2 (en) | 1993-12-02 | 1993-12-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2806774B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3943096B2 (en) | 2004-03-31 | 2007-07-11 | シャープ株式会社 | SEMICONDUCTOR DEVICE, ITS ELECTRIC INSPECTION METHOD, AND ELECTRONIC DEVICE HAVING THE SAME |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5399460A (en) * | 1977-02-10 | 1978-08-30 | Nippon Electric Co | Integrated circuit device |
-
1993
- 1993-12-02 JP JP5338814A patent/JP2806774B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07161923A (en) | 1995-06-23 |
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