JP2803565B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a PN junction is formed on an insulating film formed on a surface of a semiconductor substrate. 2. Description of the Related Art As shown in, for example, JP-A-58-151051 and JP-A-57-141962, an insulating film is formed on a semiconductor substrate.
A semiconductor device in which an -N junction is formed is known. Since such a semiconductor device does not have a parasitic operation, it is possible to easily connect a plurality of elements constituted by PN junctions in series, and the applicable range Is the big one. For example, a plurality of diodes constituted by PN junctions can be constituted in a state of being connected in series, and a temperature detecting element can be easily constituted by utilizing the temperature characteristics of the forward voltage of these diodes. . FIGS. 8, 9 and 10 show specific examples of a semiconductor device in which a plurality of diodes are connected in series. 8 is a sectional view, FIG. 9 is a plan view thereof, and FIG. 10 is an electric circuit diagram thereof. In the figure, reference numeral 100 denotes a semiconductor substrate on which an insulating film 101 is formed. An island 102 made of polycrystalline silicon is formed in a predetermined region on the insulating film 101, and an n ⁺ region 102a and a P ⁺ region 102b are respectively implanted into the polycrystalline silicon by ion implantation of phosphorus or boron. Forming
The n ⁺ region 102a and the P ⁺ region 102b are formed concentrically on a plurality of PN junctions such that they are formed adjacent to each other. After the surface of the polycrystalline silicon island 102 is sequentially covered with an oxide film 103 and a surface protection film 104, an opening is formed, and the n ⁺ region 102a disposed at the center of the concentric circle and the outermost region are formed. A semiconductor device is formed by forming electrodes 105a and 105b in the n ⁺ region 102a to be arranged, respectively. [0005] However, in the conventional semiconductor device having such a configuration, the current capacity of the PN junction is limited by the current density per unit length of the PN junction. Therefore, since the current capacity of the semiconductor device is determined by the inner PN junction length having the shortest junction length, when a sufficient current capacity is to be obtained, It is necessary to lengthen the inner PN junction length, which is the shortest junction length, and accordingly, the outer PN junction length becomes longer. The area occupied by each increases, and the area efficiency in design deteriorates. In such a configuration, the n ⁺ region 102a (or the P ⁺ region 10
2b), inside the P ⁺ region 102, which is a region of the opposite conductivity type,
As a result, b (or n ⁺ region) is formed, and since the shape has a corner, current is concentrated at the corner, and the breakdown strength is reduced. Therefore, a diode having a lateral structure made of polycrystalline silicon as shown in FIGS. 1 and 2 or FIGS. 5 and 6 can be considered. This is because the PN junction area can be made substantially the same in any diode, so that the area efficiency is improved as compared with the conventional diode, so that high integration is possible. Further, it is conceivable that the corner portion unlike the conventional diode can be eliminated, so that the electric field concentration portion can be reduced and the breakdown strength can be improved. There is a demand for further improving the breakdown strength. Accordingly, an object of the present invention is to provide a semiconductor device that further improves the breakdown strength by focusing on the structure of the polycrystalline silicon layer. In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming an insulating film on a substrate and a step of forming an insulating film on a predetermined region on the insulating film. Forming a crystalline silicon layer, and a surface of the polycrystalline silicon layer
Thermally oxidizing the polycrystalline silicon layer , and thereafter,
Annealing at a temperature of 100 ° C. or more for 15 minutes or more, and forming a rectangular P-region and an N-region adjacent to each other by selectively injecting impurities into the polycrystalline silicon layer; Forming at least one PN junction that is cut at a peripheral portion of the crystalline silicon layer so as to have cut surfaces facing each other and extends linearly from one cut surface to the other cut surface; Providing a predetermined wiring to the silicon layer. According to the present invention, a rectangular P
A region and an N region are formed adjacent to each other, are cut so as to have cut surfaces facing each other at a peripheral portion of the polycrystalline silicon layer, and extend linearly from one cut surface to the other cut surface. Since at least one PN junction cut at the peripheral portion of the crystalline silicon layer is formed, the area efficiency is improved, high integration is possible, and the breakdown strength is improved. Can be. Further, in the present invention, after forming the polycrystalline silicon layer, the surface of the polycrystalline silicon layer is thermally oxidized.
As a result, when forming the polycrystalline silicon layer,
Fine irregularities formed on the surface undesirably can be improved,
When a PN junction is formed in the polycrystalline silicon layer,
Local withstand voltage drop caused by minute unevenness of
It is necessary to suppress a decrease in breakdown strength due to current concentration.
Can be. In addition, the polycrystalline silicon layer
Since annealing is performed later at a temperature of 1100 ° C. or more for 15 minutes or more, as shown in FIG. 11, the unpaired electron density can be sufficiently reduced, and minute defects in the polycrystalline silicon layer can be reduced. Therefore, a decrease in the breakdown strength due to the minute defect can be suppressed, and the breakdown strength can be further improved. Also when the time for the annealing is 15 minutes or more, as shown in FIG. 11, the reduction characteristics of the unpaired electron density is as nearly saturated with respect to the annealing time, not
Variations in electron density itself are greatly reduced between devices.
Swell . Therefore, for example, even if the annealing process slightly varies between wafers and lots, the film quality of the obtained polycrystalline silicon layer can be made as good as that of the polycrystalline silicon layer, and there is no variation in the characteristics such as the breakdown strength. There is an excellent effect that a layer can be obtained. An embodiment of the present invention will be described below with reference to the drawings. FIGS. 1, 2 and 3 are views showing a first embodiment of the present invention, and FIGS. 1 (a) to 1 (g) are cross-sectional views for explaining the first embodiment in the order of manufacturing steps. 2 is a plan view of the semiconductor device according to the first embodiment, and FIG. 3 is an electric circuit diagram thereof. A method of manufacturing a semiconductor device according to the first embodiment will be described. First, as shown in FIG. 1A, 1050 is formed on a main surface of a semiconductor substrate 1 made of, for example, a single crystal of silicon.
An insulating film 2 of a thermal oxide film of about 1 μm is formed over the entire surface under the conditions of ° C and wet HCl. Then, as shown in FIG. 2B, non-doped polycrystalline silicon is deposited on the insulating film 2 by, for example, a CVD method at a temperature of about 600 ° C. to a thickness of about 4000 °, followed by photoetching. This polycrystalline silicon is patterned by
One island 3 is formed by polycrystalline silicon by etching by a dry etching method such as reactive ion etching (RIE). At this time, the polycrystalline silicon island 3
Has an irregular shape due to the variation in the deposition state of the polycrystalline silicon itself during the deposition of the polycrystalline silicon or the influence of the RIE (reactive ion etching) process. Next, as shown in FIG. 1C, the surface of the polycrystalline silicon island 3 is thermally oxidized in a dry O ₂ gas atmosphere at a temperature of 900 to 1200 ° C., preferably about 1050 ° C. , 600-700 ° thick thermal oxide film 4 is formed. At this time, the thermal oxide film 4 has inherited the irregular shape of the surface of the polycrystalline silicon island 3, but the surface of the polycrystalline silicon island 3a after the thermal oxidation is substantially smoothed. Next, as shown in FIG. 1D, after the thermal oxide film 4 is removed by wet etching,
As shown in (e), a thermal oxide film 5 having a thickness of 500 to 700 ° is formed. The thermal oxidation condition at this time is, for example, 1000
About 50 ° C. in a dry O ₂ gas atmosphere at a temperature of about 50 ° C.
And then about 20 minutes in a N ₂ gas atmosphere. Here, since the thermal oxide film 5 is formed on the polycrystalline silicon island 3 whose surface has been substantially smoothed in the previous step, the surface of the thermal oxide film 5 is also substantially smooth. I have. Next, high-temperature annealing is performed at, for example, about 1170 ° C. in an atmosphere of an inert gas such as N _{2 for} 170 minutes to improve the film quality of the polycrystalline silicon. As can be seen from the graph shown in FIG. 11, if the high-temperature annealing is performed at a temperature of 1100 ° C. or more and for a time of 15 minutes or more, the unpaired electron density can be reduced and the minute defects can be reduced. Can be obtained. [0014] Next, resist coating, exposure processing is performed resist selective removal, and a series of steps of ion implantation, respectively, as shown in FIG. 1 (f), P ⁺ regions in the island 3 of polycrystalline silicon 3a and the n ⁺ region 3b are formed. still,
When forming the P ⁺ region 3a, a P-type impurity such as boron
0KeV, 8 × 10 implanted at ¹⁴ dose, n ⁺ when forming a region 3b is 100Ke the n-type impurity such as phosphorus
V, 5 × 10 ¹⁵ dose ion implantation. As shown in FIG. 2, each of the P ⁺ region 3a and the n ⁺ region 3b is formed in a vertically long rectangular shape, and the P ⁺ region 3a and the n ⁺ region 3b are formed.
Are formed alternately adjacent to each other. That is, a plurality of PN junctions are formed at substantially equal intervals from one side of the island 3 to the other side opposite thereto, and the PN junctions are It is terminated at each side of the polycrystalline silicon island 3. Next, a heat treatment is performed at 1000 to 1100 ° C. for 20 minutes or more in an atmosphere of an inert gas such as N ₂ to drive in the impurities implanted into the polycrystalline silicon and at the same time, simultaneously with the P ⁺ region 3a. Drain the boron inside. In this regard, the suction of boron utilizes the difference between the eccentricity coefficients of boron and phosphorus, which lowers the surface concentration and increases the breakdown voltage. Next, as shown in FIG. 1 (g), BPSG is applied on the thermal oxide film 5 on the polycrystalline silicon island 3 by about 700 bp.
0 ° is deposited, an interlayer insulating layer 6 is formed, an opening is formed in the interlayer insulating layer 6, and Al-Si is formed in the P ⁺ region 3a and the n ⁺ region 3b located at both ends of the island 3, respectively.
To form electrodes 7a and 7b. Also, a plurality of PN junctions formed by a pair of the P ⁺ region 3a and the n ⁺ region 3b are sequentially connected to form the electrode 7c.
Is formed. The semiconductor device thus formed is
The diode is wired as shown in FIG.
The forward direction is set in the direction of the arrow in the figure. Therefore,
According to the first embodiment, the lengths of the plurality of PN junctions are set to be equal by the width of the polysilicon island 3. Accordingly, there is no longer a portion designed to be extra long as in the conventional configuration shown in FIGS. 8, 9 and 10, and the area efficiency is improved, so that high integration is possible. When the PN junction length of the first embodiment is designed to be equal to the innermost PN junction length in the conventional device, the element area of the first embodiment is reduced to about 1/3. Can be reduced. According to the first embodiment, a plurality of PN junctions are formed at substantially equal intervals from one side of the island 3 to the other side opposite to the PN junction. The termination is made, and since there is no corner as in the conventional case, the current flows uniformly without concentration and the breakdown strength is improved. FIG. 12 is a characteristic diagram showing a relationship between a PN junction length and a breakdown current, and a characteristic A is a schematic plan view of FIG.
As shown in FIG. 13 (a), the characteristic in the shape of a diode (hereinafter, referred to as "sample A") using the technical concept of the present invention, and the characteristic B is, as shown in FIG.
⁺ Region inside the diode forming a P ⁺ region (hereinafter,
As shown in FIG. 13 (c), the characteristics of the sample (hereinafter referred to as "sample B") and the characteristics of the sample (hereinafter referred to as "sample C") are modified so that the corners are further increased by modifying the conventional shape. ). When the breakdown current density (= breakdown current / PN junction length) is determined from these characteristics, the characteristic A is 1.64 mA / μm, and the characteristic B is 0.88 mA / μm.
m, the characteristic C is 0.61 mA / μm, and the density is smaller as the number of corners is larger, and the sample A has the highest density. , PN junction length can be minimized, so that the area can be further reduced. It is considered that the reason why the density of the sample A is highest is that the current flows uniformly as described above. FIGS. 14 (a) and 14 (b) show voltage-current characteristics when a diode is set and a reverse bias is applied as shown in the electric circuit diagram of FIG. 14 (c).
Figure (a) characteristics of the sample A that by in FIG. 13 (a), FIG. (B)
There respectively show characteristics of the sample B by in Figure 13 (b). The breakdown voltage of each sample is 6.04 V in sample A and 5.97 V in sample B. According to the present invention, the breakdown voltage can be set high. A point to be particularly noted in FIG. 14 is the bending of the characteristic indicated by the middle arrow in FIG. 14B, which is broken twice at the corner of the P ⁺ region and at the straight line portion. Since the breakdown occurs and the breakdown voltage at the corner is smaller, it can be inferred that such characteristics are obtained. FIG. 15 is a diagram showing the variation amount ΔVz of the withstand voltage, which is obtained by setting a diode in an electric circuit as shown in FIG. 16 and flowing a current of 1 mA at 150 ° C. for 3 hours. Each plot represents samples A, B, and C according to FIGS. This figure 1
As can be seen from FIG. 5, according to the sample A, the fluctuation amount ΔVz of the breakdown voltage can be effectively reduced, and when the diode according to the present invention is used as, for example, a Zener diode, a good element having stable characteristics can be provided. The effects of the present invention have been described using experimental data. In the manufacturing process of the first embodiment, the following considerations have been made to further improve the breakdown strength. First, when a thermal oxide film is formed on the surface of the polycrystalline silicon island 3, a thermal oxide film 4 is formed once under predetermined conditions, and then removed to form a thermal oxide film 5 again. whereby the surface and thermal acid islands 3 of polycrystalline silicon
Since the surface of the passivation film 5 is substantially flat, the concentration of the electric field due to the uneven shape can be reduced, and the surface of the polycrystalline silicon island 3 can be cleaned. Can be reduced. At the same time as the drive-in of the impurities implanted in the polycrystalline silicon is performed, the boron in the P ⁺ region 3a is sucked out. At this time, the PN junction is terminated at the side of the island 3. Boron is absorbed from the upper and side surfaces of the island 3 at the portion where the island 3 is formed, so that the surface concentration of the portion is further reduced and the withstand voltage is increased. can do.
Note that the breakdown strength at the terminal portion also depends on the distance between each of the electrodes 7a, 7b, 7c formed on the island 3 and the terminal portion, and as shown in FIG. When formed, the distance to the terminal portion is set to be longer than the distance to the other portions, so that the resistance increases and the leakage current is suppressed. In the first embodiment, a semiconductor device in which only a diode made of polycrystalline silicon is formed on the insulating film 2 has been described. However, another semiconductor element may be formed on the insulating film 2. As shown in FIG. 4, another semiconductor element may be formed in a semiconductor substrate. FIG. 4 shows an example in which a power MOS is formed using an n-type semiconductor substrate 1a, and a P-type diffusion layer 8 and an n ⁺ -type diffusion layer 9 are formed in the semiconductor substrate 1a by a known technique. After that, the polysilicon 3 serving as a gate is interposed via the insulating film 2.
c is selectively formed, and an interlayer insulating film 6 and an electrode 7d are sequentially formed in the same manner as in the above-described steps to form a power MOS. Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 5 is a sectional view of a semiconductor device according to the second embodiment, FIG. 6 is a plan view thereof, and FIG. 7 is an electric circuit diagram thereof. In the second embodiment, the electrode 7c in the first embodiment is eliminated, and the outermost region of the polycrystalline silicon island 3 is selectively ionized so that both regions are n ⁺ regions 3b. It is formed by injection. Since almost the same steps as those in the first embodiment are formed in the same steps, the same reference numerals are given to the respective components, and the description will be omitted. Then, with such a configuration, a plurality of diodes are connected to the bi-directional PN junction as shown in FIG. 7 , so that they can be used as zener diodes. Although the present invention has been described with reference to the first and second embodiments, the present invention is not limited to these embodiments and can be variously modified without departing from the gist of the present invention.
For example, the number of PN junctions formed on the insulating film 2 does not have to be plural, and at least one PN junction is sufficient. Further, a PN junction may be formed on each of two or more islands made of polycrystalline silicon.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1G are cross-sectional views for explaining a first embodiment of the present invention in the order of manufacturing steps. FIG. 2 is a plan view of the semiconductor device according to the first embodiment. FIG. 3 is an electric circuit diagram of the semiconductor device according to the first embodiment. FIG. 4 is a sectional view illustrating a modification of the semiconductor device according to the first embodiment. FIG. 5 is a sectional view of a semiconductor device according to a second embodiment of the present invention. FIG. 6 is a plan view of a semiconductor device according to a second embodiment. FIG. 7 is an electric circuit diagram of a semiconductor device according to a second embodiment. FIG. 8 is a sectional view of a conventional semiconductor device. FIG. 9 is a plan view of a conventional semiconductor device. FIG. 10 is an electric circuit diagram of a conventional semiconductor device. FIG. 11 is a graph showing the relationship between the annealing time and temperature and the unpaired electron density. FIG. 12 is a graph showing a relationship between a PN junction length and a breakdown current. FIGS. 13A to 13C are schematic plan views showing the shape of each diode. 14 (a) and (b) are FIGS. 13 (a) and 13 (b), respectively .
It is a characteristic view showing the voltage-current characteristic of the diode in (b). (C) is an electric circuit diagram showing a measurement state in FIGS. 14 (a) and (b). 15 is a diagram showing the variation of the breakdown voltage of the diode in FIG. 13 (a) ~ (c) . It is an electric circuit diagram showing a measurement state in FIG. 16 FIG. [Description of Signs] 1 Semiconductor substrate 2 Insulating film 3 Island 3a P ⁺ region 3b n ⁺ region 4 Thermal oxide film 5 Thermal oxide film 7a Electrode 7b Electrode 7c Electrode

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-56-114381 (JP, A) JP-A-57-153463 (JP, A) JP-A-61-289618 (JP, A) JP-A 58-114 85522 (JP, A) JP-A-48-84576 (JP, A) JP-A-61-129867 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 29/861 H01L 21 / 324

Claims (1)

(57) Claims (1) A step of forming an insulating film on a substrate, a step of forming a polycrystalline silicon layer in a predetermined region on the insulating film, and heating the surface of the polycrystalline silicon layer by heat. A step of oxidizing, and thereafter, a step of annealing the polycrystalline silicon layer at a temperature of 1100 ° C. or more for 15 minutes or more; and a P region extending in a rectangular shape by selectively injecting impurities into the polycrystalline silicon layer. And N regions are formed adjacent to each other, and are cut at the periphery of the polycrystalline silicon layer so as to have cut surfaces facing each other, and extend linearly from one cut surface to the other cut surface.
A method of manufacturing a semiconductor device, comprising: forming two PN junctions; and providing a predetermined wiring to the polycrystalline silicon layer. (2) The step of forming the PN junction includes the step of introducing an impurity into the polycrystalline silicon layer and thermally diffusing the impurity at a high temperature of about 1000 ° C. 2. The method according to claim 1, wherein the temperature is higher than the temperature of the thermal diffusion. 3. The method for manufacturing a semiconductor device according to claim 1, wherein said annealing atmosphere is a nitrogen or other inert gas atmosphere. (4) the annealing temperature the method of manufacturing a semiconductor device according to any one of the range paragraphs 1 through the third term of the claims is higher than the temperature of the thermal oxide. (5) The step of thermally oxidizing the surface of the polycrystalline silicon layer
Before, the polycrystalline silicon layer is patterned into an island shape
What is claimed in claims 1 to 4 further comprising a step
A method for manufacturing a semiconductor device according to any one of the preceding claims.