JP2893594B2 - Semiconductor memory - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor memory.

[Conventional technology]

Recently, a TFT memory array in which a memory element is configured by a TFT (thin film transistor) has been considered.

9 to 11 show a conventional TFT memory array. FIG. 9 is a plan view of the TFT memory array, and FIG. 10 is a sectional view of one memory element portion. In FIGS. 9 and 10, reference numeral 1 denotes an insulating substrate made of glass or the like, and a plurality of gate lines (address lines) GL are formed on the substrate 1 in parallel with each other. A plurality of source lines (data lines) SL and drain lines (data lines) DL orthogonal to the gate lines GL
Are formed. At the intersection of the gate line GL and the source line SL and the drain line DL, a memory element M composed of an inverse staggered TFT is formed. The memory element M includes a memory element region portion (hereinafter referred to as a gate electrode) G of the gate line GL, a memory insulating film 2 formed over the entire surface of the substrate 1 on the gate electrode G, An i-type semiconductor layer 3 made of ia-Si (i-type amorphous silicon) formed on the gate electrode G and a memory element region portion of the source line SL and the drain line DL (hereinafter referred to as a source electrode And a drain electrode D). The source electrode S and the drain electrode D are n ⁺ -a-Si (n-type impurity) on both sides of the i-type semiconductor layer 3 sandwiching the channel region. Is formed via an n-type semiconductor layer 4 made of amorphous silicon doped with (a). The memory insulating film 2 is made of silicon atom Si
The stoichiometric ratio of the composition ratio of Si / N to nitrogen atoms N (Si / N = 0.7
5) It is made of silicon nitride (SiN) which is larger (Si / N = 0.85 to 1.15) and has a charge storage function.

FIG. 11 shows an equivalent circuit of the above-mentioned TFT memory array. Writing, erasing and reading of this TFT memory array are performed as follows.

Write operation is performed by applying a positive voltage + 1 / 2V _P corresponding to 1/2 of the write and erase voltage V _P to the gate line GL for selecting, each of the write and erase voltage V _P to the source line SL and the drain line DL to select applying a negative voltage -1 / 2V _P corresponding to 1/2. The potentials of the unselected gate line GL and the source and drain lines SL and DL are set to 0. When such a voltage is applied, the gate electrode G of the selected memory element M at the intersection of the selected gate line GL and the selected source / drain lines SL, DL and the source / drain electrodes S, D potential difference corresponding to the write erase voltage V _P is the selected memory device M becomes the write state occurs on.

At the time of erasing, -1 / 2V _P
Source line SL and drain line DL
+ 1 / 2V _P is applied to each. Also in this case, the potentials of the unselected gate line GL and the source and drain lines SL and DL are set to 0. When such a voltage is applied, the gate electrode G and the source and drain electrodes S and D of the selected memory element M at the intersection of the selected gate line G and the selected source and drain lines SL and DL data the potential difference of the reverse potential corresponding to the write erase voltage V _P is held in the selected memory device M occurs is erased.

On the other hand, the read time is to apply a more adequate small ON voltage V _ON the write erase voltage V _P to the gate lines GL for selecting the source for selecting, drain line SL, the read voltage (write erase the drain line DL of DL applying a sufficiently small voltage) V _D than the voltage V _P, the potential of the source line SL is set to 0. An off voltage V _OFF is applied to unselected gate lines GL, and unselected source and drain lines SL, D
The potential of L is set to 0. When such a voltage is applied, selection is made from the selected drain line DL in accordance with the data held in the selected memory element M at the intersection of the selected gate line GL and the selected source and drain lines SL, DL. A current flows through the source line SL, which is output as read data.

[Problems to be solved by the invention]

However, in the above-described conventional TFT memory array, since each memory element M is configured by an inverted staggered TFT, the vertical and horizontal plane dimensions of each memory element M are equal to the width of the gate electrode G portion of the gate line GL. , Width of source and drain electrodes S and D of source and drain lines SL and DL and their spacing (channel length between source and drain electrodes S and D)
And therefore one memory element M
Occupies a large area, making it difficult to achieve high integration.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to significantly reduce the plane area occupied by one memory element and to form a plurality of memory elements in the same place. And to provide a semiconductor memory with high integration.

[Means for solving the problem]

The semiconductor memory of the present invention, on an insulating substrate, a laminated film formed by laminating a source electrode and a drain electrode with a semiconductor layer interposed, laminated with an insulating film interposed between a plurality of laminated films,
A charge storage layer and a gate electrode are provided on side surfaces of the plurality of stacked films.

As described above, since the source electrode and the drain electrode are stacked, the area occupied by the memory element can be significantly reduced. In addition, the area occupied by one memory element can be reduced because a plurality of stacked films are stacked. A plurality of memory elements can be formed therein, and higher integration can be achieved as compared with a conventional semiconductor memory.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to FIGS.

1 and 2 are sectional views of one memory element portion of the TFT memory array of the present embodiment, FIG. 3 is a sectional view of a portion between memory elements, and FIG. 4 is a plan view of the TFT memory array.

1 to 4, reference numeral 11 denotes an insulating substrate made of glass or the like, on which a source line (data line) SL and a drain line (data line) DL are formed. , DL along the semiconductor layer (i-
A laminated film polymerization layer in which three laminated films A1, A2, and A3 are vertically stacked with an i-type semiconductor layer (a-Si semiconductor layer) 13 interposed therebetween is formed in parallel with each other for a plurality of lines. In each of the laminated films A1, A2, A3 of the laminated film polymerized layer, a drain line DL is formed in a lower layer, and a semiconductor layer 13 and a source line SL are formed thereon.
Are sequentially laminated, and the lower laminated film A1 is
The intermediate film A2 and the upper insulating film A3 are formed on the underlying insulating film 12a formed in a pattern along the source and drain lines SL and DL on the substrate 11, respectively. It is formed on the interlayer insulating film 12b formed on A2. In addition, the drain lines DL of the respective laminated films A1, A2, A3
And the semiconductor layer 13 and the source line SL and the base insulating film 12
a and the interlayer insulating film 12b are all formed in the same pattern. The base insulating film 12a and the interlayer insulating film 12b are both insulating films having no charge storage function, for example, the stoichiometric ratio (Si / N = Si / N = Si / N = Si / N).
It is made of silicon nitride (SiN), which is about the same as 0.75).

On the other hand, GL is on the substrate 11 and the respective laminated films A1, A2, A3.
The gate line GL is a plurality of gate lines provided on the stacked film polymerized layer in which the source line SL and the drain line DL of each of the stacked films A1, A2, A3 are crossed in a plane. Rises along both sides of the laminated film polymerized layer, that is, both sides of each laminated film A1, A2, A3, and at the rising portion, the source line SL and the drain line DL of each laminated film A1, A2, A3 and the semiconductor layer It faces 13 sides. Reference numeral 14 denotes a memory insulating film interposed between the gate line GL and a side surface of each of the stacked films A1, A2, and A3, and the memory insulating film 14 is formed in the same pattern as the gate line GL. . The memory insulating film 14 has a composition ratio Si / N of silicon atom Si and nitrogen atom N larger than the stoichiometric ratio (Si
/N=0.85 to 1.15) and is made of silicon nitride having a charge storage function.

The intersections of the gate line GL and the source line SL and the drain line DL of each of the laminated films A1, A2, A3 are memory elements M1, M2, M3, respectively, and these memory elements M1, M2, M3 Are the source and drain electrodes S and D of the source and drain lines SL and DL (portion intersecting with the gate line GL) and the semiconductor layer 13 between them as side surfaces, and the gate electrode of the gate line GL via the memory insulating film 14. The configuration is such that G portions (rising portions along both side surfaces of each of the laminated films A1, A2, A3) face each other. Note that the base insulating film 12a is provided to ensure that the gate electrode G faces the side surface of the drain electrode D below the lower stacked film A1. The insulating film 14 is formed thicker than the film thickness.

Reference numeral 15 denotes a substrate 11 on which the memory elements M1, M2, and M3 are formed.
Tantalum oxide (Ta
O _X ) and the like.
Is provided to prevent an unstable current from flowing through the laminated films A1, A2, and A3 in a portion where the gate line GL does not pass (a portion shown in FIG. 3).

FIG. 5 shows an equivalent circuit of the above-mentioned TFT memory array. Writing, erasing and reading of this TFT memory array are performed as follows.

When writing is performed by applying a positive voltage + 1 / 2V _P corresponding to 1/2 of the write and erase voltage V _P to the gate line GL for selecting, each laminated film
A1, A2, A3 source, drain line SL, of the DL, a negative voltage corresponding to 1/2 of each source line SL and the drain line DL the write erase voltage V _P of the laminate film to choose -1/2
Apply _VP . Note that the potentials of the unselected gate line GL and the source / drain lines SL and DL of the unselected stacked film are 0
And When such a voltage is applied, the selected gate line GL and the selected source / drain lines SL, DL
The selected memory potential difference is produced corresponding to the write erase voltage V _P between the gate electrode G and the source, drain electrodes S, D of selected memory elements in the intersection (M1.M2, M3 either) with The element enters a write state.

At the time of erasing, -1 / 2V _P
It was applied, applying a source line SL and to the drain line DL + 1 / 2V _P stacked film to be selected. Again,
Unselected gate line GL and unselected stacked film source,
The potentials of the drain lines SL and DL are set to 0. When such a voltage is applied, the gate electrode G and the source / drain electrodes S, D of the selected memory element at the intersection of the selected gate line G and the selected source / drain lines SL, DL
Data the potential difference of the reverse potential corresponding to the write erase voltage V _P is held in the selected memory device M occurs is deleted between.

On the other hand, during reading, it applies a sufficiently low ON voltage V _ON from the write erase voltage V _P to the gate lines GL for selecting the source of the laminated film to be selected, the drain lines S
L, and (sufficiently small voltage than the write erase voltage V _P) V _D drain line DL to the read voltage of the DL is applied, a source line
The potential of SL is set to 0. Note that the off voltage V _OFF is applied to the unselected gate line GL, and the potentials of the source and drain lines SL and DL of the unselected stacked film are set to 0. When such a voltage is applied, selection is made from the selected drain line DL in accordance with the data held in the selected memory element M at the intersection of the selected gate line GL and the selected source and drain lines SL, DL. A current flows through the source line SL, which is output as read data.

FIGS. 6 to 8 show a method of manufacturing the above-mentioned TFT memory array. This TFT memory array can be manufactured by the following steps.

First, as shown in FIG. 6A, a base insulating film 12a and a metal film 1 made of chromium or the like to be a drain line DL are formed on a substrate 11.
6, a semiconductor layer 13, a metal film 17 such as chromium serving as a source line SL is sequentially deposited to form a lower layered film A1, followed by an interlayer insulating film 12b and a metal such as chromium serving as a drain line DL. The film 16, the semiconductor layer 13, and the metal film 17 of chromium or the like to be the source line SL are repeatedly deposited to form an intermediate layer laminated film A2.
Then, an upper layered film A3 is formed.

Next, the metal film 17 of each of the laminated films A1, A2, A3, the semiconductor layer 1
3. The metal film 16, the interlayer insulating film 12b and the base insulating film 12 are patterned into the shapes of the source and drain lines SL and DL as shown in FIGS. 6 (b) and 7.

Next, a memory insulating film 14 is formed over the entire surface of the substrate 11.
And a metal film of chromium or the like to be the gate line GL are sequentially deposited, and the metal film and the memory insulating film 14 are patterned into the shape of the gate line GL as shown in FIGS. 6 (c) and 8.

Thereafter, a protective insulating film 15 is formed on the entire surface of the substrate 11 as shown in FIG. 6 (d), and the TFT memory array shown in FIGS. 1 to 4 is completed.

That is, in the TFT memory array of the above embodiment, the stacked films A1, A2, and A3 in which the source line SL and the drain line DL are vertically stacked with the semiconductor layer 13 interposed therebetween are formed by a plurality of layers (intervening layers) via the interlayer insulating film 12b. By stacking three layers in the example, the memory element is formed in a plurality of layers (three layers) at the intersection of the source line SL and the drain line DL of each of the laminated films A1, A2, and A3 and the gate line GL intersecting the source line SL and the drain line DL. M1, M2, M3. In this TFT memory array, the source line SL and the drain line DL are vertically stacked with the semiconductor layer 13 interposed therebetween, as described above, so that the source line SL Since the drain line DL is provided within the plane area of one line, the vertical and horizontal plane dimensions of the memory elements M1, M2, and M3 are determined by the width of the gate electrode G portion of the gate line GL and the source and drain lines. Electrode part of one of SL and DL (The portion corresponding to the source electrode S portion or the drain electrode D portion), so that the plane area occupied by one memory element can be significantly reduced, and the source line SL and the drain line DL are connected to a semiconductor. Since the laminated films A1, A2, and A3, which are laminated with the layer 13 interposed therebetween, are laminated in a plurality of layers with an interlayer insulating film 12b interposed therebetween, the laminated film
Since a plurality of memory elements M1, M2, and M3 having the same number as the number of stacked layers A1, A2, and A3 can be formed, it is possible to achieve much higher integration than a conventional TFT memory array.

Moreover, in the above embodiment, the source line SL and the drain line DL of each of the laminated films A1, A2, A3 and the semiconductor layer 13,
The interlayer insulating film 12b between the laminated films A1, A2, A3 and the lower laminated film A1
The source and drain lines SL, DL of each of the laminated films A1, A2, A3 at the time of manufacturing a TFT memory array, since all the underlying insulating films 12a under
And the semiconductor layer 13 and the interlayer insulating film 12b and the base insulating film 12 can be patterned at once, and the gate line
Since the GL and the memory insulating film 14 thereunder have the same pattern, the gate line GL and the memory insulating film 14 can also be patterned at a time, so that the manufacture of the TFT memory array is easy.

In the above embodiment, the drain line DL of each of the laminated films A1, A2, A3 is formed on the lower side, and the drain line DL is formed on the upper side. Conversely, the source line SL is formed on the lower side, and the drain line DL is formed on the lower side. The line DL may be formed on the upper side, or if the thickness of the lower line of the source and drain lines SL and DL of the lower layered film A1 is sufficiently larger than the thickness of the memory insulating film 14, Even without the base insulating film 12a in the embodiment,
The rising portion (gate electrode G portion) of the gate line GL can be opposed to the side surface of the line below the lower layered film A1. Further, in the above embodiment, the gate line GL of each of the laminated films A1, A2, A3 has the same width as the gate electrode G portion, and the source line SL and the drain line DL have the same width as the source and drain electrodes S, D portion. However, the width of the line portion of the gate line GL and the source and drain lines SL and DL may be different from the width of the electrodes G, S and D.

Further, in the above embodiment, the source line SL, the drain line DL, and the semiconductor layer 13 of each of the laminated films A1, A2, A3 are all in the same pattern, but these are not necessarily the same pattern. The source / drain electrodes S and D of the source / drain lines SL and DL of the laminated films A1, A2 and A3 and the side surfaces of the semiconductor layer 13 are connected to the gate lines GL.
It is sufficient that the gate electrode G has a shape that can be opposed to the gate electrode G via the memory insulating film 14, and the memory insulating film 14 does not necessarily have to have the same pattern as the gate line GL.

Further, in the above embodiment, the stacked films A1, A2, and A3 in which the source line SL and the drain line DL are stacked vertically with the semiconductor layer 13 interposed therebetween are stacked in three layers. May be arbitrarily determined. If the number of stacked layers is increased, a greater number of memory elements can be formed at the same location to further increase the degree of integration.

〔The invention's effect〕

The semiconductor memory according to the present invention is characterized in that a plurality of stacked films formed by stacking a source electrode and a drain electrode with a semiconductor layer interposed therebetween are stacked on an insulating substrate with an insulating film interposed between the stacked films. The charge storage layer and the gate electrode are provided on the side surfaces of the laminated film of the above. In this way, since the source electrode and the drain electrode are laminated, the area occupied by the memory element can be significantly reduced. Since a plurality of stacked films are stacked, a plurality of memory elements can be formed in an area occupied by one memory element, and higher integration can be achieved as compared with a conventional semiconductor memory.

[Brief description of the drawings]

1 to 8 show an embodiment of the present invention. FIG. 1 is an enlarged sectional view taken along line II of FIG. 4, and FIG. 2 is a line II-II of FIG. FIG. 3 is an enlarged sectional view taken along the line II in FIG.
FIG. 4 is a plan view of the TFT memory array, FIG. 5 is an equivalent circuit diagram of the TFT memory array, FIG. 6 is a manufacturing process diagram of the TFT memory array, and FIG. FIG. 6 (b) is a plan view, and FIG. 8 is a plan view of FIG. 6 (c). FIG. 9 and FIG. 10 are a plan view of a conventional TFT memory array and an enlarged sectional view of one memory element portion thereof.
FIG. 11 is an equivalent circuit diagram of a conventional TFT memory array. 11 ... substrate, A1, A2, A3 ... laminated film, DL ... drain drain, D ... drain electrode, 13 ... semiconductor layer, SL ... source line, S ... source electrode, 12a ... base insulation Membrane, 12b
... interlayer insulating film, 14 ... memory insulating film, GL ... gate line, G ... gate electrode, M1, M2, M3 ... memory element, 15
.... Protective insulating film.

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁶ identification code FI H01L 29/792 (58) Investigated field (Int.Cl. ⁶ , DB name) H01L 29/788 H01L 29/792 H01L 27/115 H01L 21/8247 H01L 29/786

Claims (1)

(57) [Claims] A plurality of laminated films formed by laminating a source electrode and a drain electrode with a semiconductor layer interposed therebetween with an insulating film interposed between the plurality of laminated films; A semiconductor memory, wherein a charge storage layer and a gate electrode are provided on a side surface of the semiconductor memory.