JP2893350B2 - Data processing device, image processing device, shift register circuit, lookup table circuit, arithmetic circuit, image processing system - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a data processing apparatus that processes time-series data that is sequentially input in a pipeline by hardware processing means and sequentially outputs the processing results. More particularly, the present invention relates to a one-chip type data processing device suitable for local area processing of an image.

[Conventional technology]

Data processing for performing the same arithmetic processing on a large amount of data includes data processing in simulation,
There are two-dimensional data map or two-dimensional image data processing, and these processing can be executed by a general sequential computer. However, in order to perform those processing at high speed, a dedicated data processing device is desirable. For example, in the field of image processing, 3 ×
It is necessary to perform processing (local image processing) using local pixel data such as three pixels at a rate of 3,932,160 times / second. In order to perform such high-speed data processing, a dedicated data processing device as disclosed in Japanese Patent Application Laid-Open No. 59-146366 or Japanese Patent Application Laid-Open No. 62-140183 has been developed.

[Problems to be solved by the invention]

However, in the above-described conventional technology, an addition / subtraction circuit, a multiplication / division circuit, and the like are combined in order to perform a general-purpose local image processing, and in some cases, an arithmetic operation is performed by using those circuits several times in a time-division manner. I have. Therefore, there is a problem that management of the circuit configuration or the timing of data flowing through the data processing device is complicated, and that the design and operation test of the device are also difficult.

Further, there is a problem in that the data processing device must be configured using a plurality of LSIs and external circuits because the circuit becomes complicated and cannot be accommodated in a one-chip LSI circuit. These problems further require a user who uses the data processing apparatus and a high degree of knowledge in configuring a system using the data processing apparatus, making the system configuration difficult.

An object of the present invention is to input a plurality of data in time series,
A data processing device that performs predetermined arithmetic processing on one data of the plurality of data using a certain number of data having a fixed relative relationship with respect to the one data and outputs the data, It is an object of the present invention to realize a one-chip LSI circuit that can be realized by a simple configuration using a circuit and that can easily manage data processing timing.

Another object of the present invention is to provide an image processing device suitable for local image processing in addition to the above object.

Another object of the present invention is to provide a circuit element having a configuration suitable for realizing the image processing apparatus.

[Means for solving the problem]

In order to achieve the above object, the data processing device of the present invention inputs a plurality of data in a time-series manner, and one data in the plurality of data is temporally relative to the one data. Using a certain number of data, a data processing for performing a predetermined arithmetic process and outputting the data, the data including the one input data is respectively delayed according to the relative relationship, and is finally input. A delay circuit that outputs the same data as the same data, and an arithmetic processing circuit that inputs each data output from the delay circuit and performs the predetermined arithmetic processing.

Further, an image processing device of the present invention is an image processing device including a pixel data delay circuit, a look-up table circuit, and an arithmetic processing circuit, wherein the pixel data delay circuit has a two-dimensional array of pixel data. Are input in time series, the input one pixel data and the adjacent pixel data of the pixels adjacent to the pixel corresponding to the one pixel data are delayed according to the time series relative relationship, and finally, The look-up table circuit includes a memory provided in correspondence with each pixel data input from the pixel data delay circuit, and a drive of the memory. And each memory is configured to process each pixel data in an area corresponding to the address with the pixel data as an address by a predetermined function. And the driving circuit of the memory reads out the processing data corresponding to the input pixel data from the memory and outputs the read processing data. The output data of the up-table circuit is input, processed by predetermined addition and subtraction, and output.

An image control signal delay circuit is provided in the image processing apparatus, and the control signal delay circuit inputs an image control signal, and converts the image control signal into the pixel data delay circuit, the look-up table circuit, and the arithmetic processing. The pixel data is output in a delayed manner in accordance with a delay time of the one pixel data by the circuit, and the input of the pixel data is held in synchronization with a blanking period of the image control signal. It can be.

Further, the pixel data delay circuit includes two memories;
And a shift register circuit for delaying the input n-bit time-series pixel data by n bits and outputting the same, and the memory has a memory area of at least n / 2 words. The memory drive circuit may alternately write sequentially input pixel data to the two memories and alternately read the written pixel data with an n-bit delay.

Further, the lookup table circuit includes a memory,
A constant register, and first and second multiplexers, wherein the first multiplexer inputs an address in a normal mode and an address in a setting mode, and selects one of the two addresses by a selection signal input separately The second multiplexer receives the output of the memory and the constant register, selects one of the two outputs according to a mode switching signal input separately, and outputs the selected output. The memory stores setting data separately input by an input write control signal in a memory area corresponding to the address input, and the constant register is separately input by the mode switching signal. Setting data may be stored.

An arithmetic processing circuit for adding or subtracting two input data in accordance with a separately input select signal; an upper / lower limit generating circuit for generating a predetermined upper limit or lower limit; A multiplexer for inputting the operation output of the addition / subtraction circuit and the upper limit value or lower limit value of the upper / lower limit value generating circuit, and selecting and outputting one of them;
The multiplexer may select and output the upper limit value or the lower limit value when an overflow signal or an underflow signal is output from the addition / subtraction circuit.

Further, the arithmetic processing circuit is provided with a second multiplexer for inputting the output of the addition / subtraction circuit and the two input data, selecting and outputting one of the two, and outputting the overflow signal at the time of subtraction. When the said 2
The input data on the subtraction side of the two input data may be output as the maximum value, and the output of the multiplexer may be output when the select signal is an addition.

Further, the lookup table circuit is provided with first and second 3-stated buffers, and the first 3-stated buffer outputs the normal address to the outside by a control signal input separately. The second 3-stated buffer may output the output of the second multiplexer to the outside in response to a separately input control signal.

Further, a configuration circuit suitable for realizing the image processing apparatus of the present invention is as follows.

The image data delay circuit includes two memories and a drive circuit for the memory, and includes a shift register circuit that delays n-bit time-series input data by n bits and outputs the delayed data. At least n / 2 words of memory area, the memory drive circuit,
It is desirable that sequentially input data is alternately written to the two memories, and that the written data is alternately read with a delay of n bits.

The look-up table circuit has a memory, a constant register, and first and second multiplexers, and the first multiplexer inputs an address in the normal mode and an address in the setting mode, and inputs the addresses in the two modes. One of them is selected by a selection signal input separately to be an address input of the memory, and the second multiplexer inputs the outputs of the memory and the constant register, and inputs one of the two outputs separately. The memory is configured to store the setting data separately input by the input write control signal in a memory area corresponding to the address input. Preferably stores the setting data separately input by the mode switching signal. .

An arithmetic processing circuit for adding or subtracting two input data in accordance with a separately input select signal;
An upper / lower limit value generating circuit that generates a predetermined upper or lower limit value, an arithmetic output of the addition / subtraction circuit and an upper or lower limit value of the upper / lower limit value generating circuit are input, and either one is selected. And a multiplexer for outputting.
Preferably, the multiplexer selects and outputs the upper limit value or the lower limit value when an overflow signal or an underflow signal is output from the addition / subtraction circuit. Also, a second circuit which receives the output of the addition / subtraction circuit and the two input data and selects and outputs one of them.
And the second multiplexer outputs, when the overflow signal is output when the select signal is subtracted, the input data on the subtraction side of the two input data as a maximum value, the second multiplexer outputs When the signals are added, the output of the multiplexer can be output.

[Action]

With such a configuration, according to the present invention, the above object is achieved by the following operations.

According to the data processing device of the present invention, each data including one data input in time series is delayed by the delay circuit according to the relative relationship of the time series, and the same timing as the data input last is used. Is output. Therefore, management of data processing timing becomes unnecessary. Further, such a delay circuit can be easily formed by hardware. An arithmetic processing circuit that inputs each data output from the delay circuit and performs predetermined arithmetic processing can be realized with a simple configuration using hardware.

According to the image processing apparatus of the present invention, the pixel data delay circuit outputs one pixel data to be processed and adjacent pixel data of a pixel adjacent thereto at the same timing. And by the look-up table circuit,
Processing data obtained by processing the pixel data as an address using a predetermined function is read. The read processing pixel data is subjected to predetermined addition / subtraction processing by an arithmetic processing circuit, and the pixel data subjected to local area processing is output as time-series pixel data similar to the input pixel data.

Generally, two-dimensional image data includes an image control signal including a blanking signal (an invalid signal as pixel data) for each horizontal line or for each screen. In response to this, an image control signal delay circuit is provided, whereby the image control signal is transmitted according to the delay time of the one pixel data by the pixel data delay circuit, the look-up table circuit, and the arithmetic processing circuit. By outputting with a delay, it is possible to output while maintaining the synchronous relationship between the pixel data and the image control signal. As a result, the flow of data becomes simple, and the design and operation test of the device become easy. In this case, if the pixel data delay circuit holds the input of the pixel data in synchronization with the blanking period of the image control signal, the number of stages of the delay circuit can be reduced accordingly.

Further, according to the shift register of the pixel data delay circuit having the two memories and the drive circuit for the memory, the shift register is smaller than the case where the unit delay circuits are connected in series according to the delay time. Become.

In addition, the counter is driven in accordance with the input of each pixel data, and the count value is used as a memory address, thereby acting as a variable length shift register for performing a necessary delay according to the number of pixel data.

Further, since the constant multiplication operation for the operation processing of the local area pixels is performed by a look-up table circuit using a memory, the size of the operation circuit can be reduced, and in addition to the downsizing of the shift register, The image processing device can be mounted on a one-chip LSI. In addition, since the lookup table circuit is used, it is possible to perform not only a constant multiplication operation but also an operation process using an arbitrary function, and it is possible to provide the operation content with considerable versatility. In addition, according to the lookup table circuit provided with a constant register, a circuit operation test can be easily performed. In addition, the arithmetic processing of the image data can have an additional function that a constant output can be temporarily obtained without rewriting the data in the lookup table.

Further, according to the arithmetic circuit for performing the addition / subtraction with the upper / lower limiter, even if the operation result overflows or underflows, the output data does not fly discontinuously. As a result, meaningful calculation results can be obtained as image data close to the original smooth change. In addition,
A circuit for selecting the maximum value can be easily configured by utilizing the subtraction of the operation with the limiter.

In addition, since the setting state of the control register and the look-up table circuit in the circuit can all be read from the outside via the control circuit, the setting state of the setting state is controlled by software of a higher-level device that controls the image processing apparatus. Even if the information is not stored, the state of the image processing apparatus can be known at any time. As a result, it can be used for function diagnosis in relation to the entire image processing system. Further, it is possible to prevent a bug caused by a mismatch between a state stored by software and an actual state of the image processing apparatus. Further, according to the one provided with the monitor terminal for directly outputting the input address data of the lookup table circuit to the outside, the operation test of the image processing apparatus can be systematically performed.

It is obtained by scanning two-dimensional original pixel data. Since an image control signal for identifying a break of time-series data of each line is input and output in synchronization with the image data, an image processing system is configured using the image processing apparatus according to the present invention. In this case, the handling of the data signal lines becomes simple, and the system configuration can be systematically performed.

〔Example〕

 Hereinafter, a description will be given based on examples of the present invention.

FIG. 1 shows an overall configuration diagram of an image processing apparatus to which the present invention is applied. The device of this embodiment is mounted on a one-chip LSI. The image processing function of the present embodiment is to perform a local area operation on four adjacent pixels on two-dimensional image data. That is, for each pixel constituting an image, an operation is performed using the data of the pixel and the four adjacent pixels vertically and horizontally, and the result is output as two-dimensional pixel data. This local area operation can be defined by the following equation (1). First, two-dimensional image data is set as a set of m × n pixel data as shown in FIG. 2, and each pixel data is numbered sequentially from the upper left corner, and Pij (i = 1... M, j = 1) .. N). The local area operation on the image data means that, for arbitrary pixel data Pij constituting the image, four adjacent pixel data P _{i−1 · j} , P _{i + 1 · j} , P _{i · j−1} , P _{Using i · j + 1} , q _ij = k (a ₀ P _ij + a ₁ P _{i−1 · j} + _az P _{i + 1 · j} + a ₃ P _{i · j-1} + a ₄ P
_{i · j + 1} ) (1). As a specific use of the local region calculation, the local region calculation is used for smoothing processing for smoothing the gray scale change of an image and processing for increasing edge detection for detecting a sharp change point of the gray scale.

The local region calculation for the four adjacent pixels is the most essential in image processing, and the present embodiment relates to an image processing device that performs this local region calculation. However,
An image processing apparatus that performs a local area operation of an arbitrary size can also be configured by a method similar to the circuit configuration of the present embodiment.

(Overall Configuration of Apparatus) As shown in FIG. 1, the main circuit of the present embodiment is composed of n-stage shift register circuits 1, 2, and 3 and a look-up table circuit.
4,5,6,7,8,9, arithmetic circuits 10,11,12,13 and control circuit 14
And signal delay circuits 15 to 38. Also, a data input terminal 50 for pixel data, a control signal input terminal
51a, b, data output terminal 52, control signal output terminals 53a, b, monitor output terminal 54, address input terminal 55 to the control circuit, control data input terminal 56, input output control terminals 57a-c, control data output terminal 58 , And a clock signal input terminal 59 are provided. In the drawing, the thick signal lines represent data signal lines having a data width of s bits, and the thin signal lines represent control signal lines. White lines represent bus-type signal lines including data lines, address lines, and control lines.
The clock signal input from the clock signal input terminal 59 is supplied to all the circuits in the figure, and all the circuits operate in synchronization with the clock signal. That is, the n-stage shift register circuits 1, 2, and 3 output the received data with a delay of n clock cycles by this clock signal, and the signal delay circuits 15 to 38 output the data with a delay of one clock cycle. The arithmetic circuits 10, 11, 12, 13 and the look-up table circuits 4, 5, 6, 7, 8, 9 also output processing results for input data after one clock cycle in synchronization with the clock signal. Designed for

The look-up table circuits 4, 5, 6, 7, 8, 9 assign numbers of k = 0, 1, 2, 3, 4, 5 in this order, and the k-th look-up table Sometimes called a circuit.

(Configuration and Operation of Each Part of the Device) Here, the configuration of each circuit in the embodiment of FIG. 1 will be described together with the operation.

The pixel data is input from the data input terminal 50 as data having a data width of s bits at a rate of one data per clock cycle. Data is P from the pixel in the upper left corner of the image
_{1 · 1, P 1 · 2} , ......, P 1 · n, P 2 · 1, ......, P 2 · n, ......, P
They are input in chronological order in the order of _{m · n} . The input data is stored in shift register circuits 2 and 3 and signal delay circuits 31, 32, 33, 34, and 3
The data are delayed by 3,2 + n, 4 + n, 3 + n, and 3 + 2n cycles, respectively, and input to the look-up table circuits 4, 5, 6, 7, and 8, respectively. At this time, considering the timing of the data P _ij input to the look-up table circuit 7, the timings of the data input to the other look-up table circuits 4, 5, 6, 8 are -n, -1 respectively. , +1 and + n cycles. Since the pixel data is sequentially input from the upper left corner of the image, just when the pixel data P _ij is input to the look-up table circuit 7, P _{i−1 · j} , P _{i · j−1} , P
Pixel data corresponding to _{i · j + 1} and _{Pi + 1 · j} are input to the look-up table circuits 4, 5, 6, and 8 at the same timing. The look-up table circuit is a kind of memory, and uses inputted pixel data as an address and outputs data written at the address. By storing the data of the value ax at the address x of the look-up table, it is possible to perform an operation to multiply the input data by a. In this way, each pixel data multiplied by a ₀ , a ₁ , a ₂ , a ₃ by the look-up table is calculated by the arithmetic circuits 10, 11, and
Lookup table circuit 9
To output k times more. Here, the arithmetic circuits 10, 11,
12 and 13 are 1 from input of data to obtaining operation result.
Since a clock cycle delay occurs, the data input timing of the arithmetic circuit 13 can be adjusted by placing the signal delay circuits 37 and 38 between the lookup table circuit 7 and the arithmetic circuit 13.

When image data to be input to the apparatus of the present embodiment is obtained from a video signal such as a video signal, the image data is generally time-series data as shown in FIG. That is, one image is mx
When decomposed into data of n pixels, after n pieces of image data for one line continue, N is provided only during horizontal blanking of scanning lines and horizontal blanking (hereinafter abbreviated as HB) for an area outside the horizontal image. _h invalid data continues, followed by data corresponding to the next line again. _{Then, N V × (n + N} h) pieces of invalid data only during vertical blanking for the vertical feedback and vertical image area outside of the scanning lines (hereinafter VB hereinafter) is followed by image data of m lines . Therefore, an HB signal and a VB signal as shown in FIG. 1 are required for identifying these invalid data and the first data of one screen. FIG. 3 shows that the image data where the HB signal and the VB signal are both 1 is valid, and that the VB signal changes from 0 to 1 is the beginning of one screen.

On the other hand, the data signal input from the data input terminal 50 and the data output terminal 52
Causes a delay between the data signals output from. Therefore, in order to output the HB signal and VB signal input at the same timing as the data signal from the control signal input terminals 51a and 51b from the control signal output terminals 53a and 53b at the same timing as the processing result data signal, a signal delay is performed. It is necessary to provide a circuit.
Signal delay circuits 15 to 30 and shift register circuit 1 in FIG.
Is for this.

By the pixel data P _ij in FIG. 1 arrives from the input from the data input terminal 50 to the look-up table circuit 7, passes through the three signal delay circuit 31, 32, 34 and one of the shift register circuit 2 I do. The output data from the lookup table circuit 7 includes two signal delay circuits 37, 3
The data is output as q _ij from the data output terminal 52 through the circuit 8, the arithmetic circuit 13, and the look-up table circuit 9. Therefore, the delay time from the input of P _ij to the output of q _ij is a total of n + 8 clock cycles. Therefore, HB
A delay circuit for n + 8 clock cycles may be prepared for the signal and the VB signal. However, since the HB signal is a signal that repeats for each line, a delay of one line (n clock cycles)
Can be omitted.

The actual time for one line is (n + N _h ) clock cycles, which is the sum of n clock cycles for image data and N _h clock cycles for HB, but shifts during invalid data for N _h clock cycles. Register circuits 1, 2, 3
And the signal delay circuits 33, 34, 35, 36, and 25 are set in the hold state so that invalid data is not read, so that the n-stage shift register circuit 1 can create a delay time for one line. The control signals 60a and 60b in FIG. 1 are for this purpose, and the shift register circuits 1, 2, and 3 and the signal delay circuits 25, 33, while the HB signal is "0" (that is, during the HB timing). Three
Put 4,35,36 in hold status.

The control circuit 14 has an address input terminal 55,
Control data input terminal 56, input / output control terminals 57a, 57b, 57c,
A circuit for switching the functions of the arithmetic circuit and the look-up table circuit by rewriting the table data of the look-up table circuits 4, 5, 6, 7, 8, and 9 and the contents of the control register using the control data output terminal 58. It is. Normal,
These element control terminals 55, 56, 57a, 57b, 57c, 58
It is connected to the U bus signal line, etc., and the CPU controls the image processing apparatus.

As described above, according to the embodiment of FIG. 1, the pixel data delay circuit composed of the shift register circuits 2 and 3 and the signal delay circuits 31, 32, 33, 34, 35, and 36 causes one pixel data to be input in time series. Pixel data P _ij and pixel data P _{i−1 · j} P _{i · j−1} P _{i · j + 1} P _{i + 1 · j} for four pixels adjacent to the pixel data P _ij , And is output at the same timing as the last input adjacent pixel data _{Pi + 1.j.}
When these five pixel data are input to the look-up table circuits 4, 5, 6, 7, 8 respectively, processing data obtained by multiplying the address previously stored in a memory area having each pixel data as an address by a constant is used. Is read out and output. The read processing data is subjected to predetermined addition processing by an arithmetic processing circuit including arithmetic circuits 10 to 13 and signal delay circuits 37 and 38, multiplied by a gain k by a look-up table circuit 9, and output. It is output from the terminal 52 as processing pixel data.

That is, according to the present embodiment, adjacent pixel data used in the arithmetic processing of one pixel data is adjusted to the same timing by the pixel data delay circuit, and the constant multiplication processing of the local area operation of the pixel data is performed by the lookup table circuit. And the addition processing of the outputs is performed by an arithmetic processing circuit including an addition circuit element, so that the signal flow in the image processing apparatus is simplified,
Circuit design and operation tests become easier.

Further, since the look-up table circuits 4 to 9 are configured using memories, the circuit size can be made smaller than in the case where the lookup table circuits 4 to 9 are configured using arithmetic circuits. Furthermore, if the shift register circuits 1 to 3 are configured by using memories as described later, the circuit size can be reduced as compared with the case where n stages of 1-bit delay circuits are provided, and the image processing apparatus of FIG. It can be implemented in

In the embodiment shown in FIG. 1, the lookup table circuits 4 to 9 are described as multiplying the input pixel data by a constant. However, an arbitrary function can be applied depending on the contents of the data processing. That is, if the pixel data is an address X, storing f (x) in an area corresponding to the address X allows the pixel data to be processed by an arbitrary function f, and allows the type of operation to have versatility. it can.

Further, together with the time-series data of the two-dimensional pixel data, an image control signal for identifying a head and a break of each line related to the horizontal scanning and the vertical scanning is input, and the image data delay circuit is held in synchronization with the input, and Since the image control signal is delayed and output by the delay of each circuit relating to the processing of the image data, the handling of the data signal lines can be understood when configuring the image processing system using the apparatus of the present embodiment. It will be easy.

Next, a specific embodiment of the main circuit of FIG. 1 will be described in detail. In the following description, it is assumed that pixel data handled by the image processing apparatus is s-bit signed data. When data is described for each bit, numbers 1, 2, 3,... Are assigned in order from the least significant bit.

(Shift Register Circuit) FIG. 4 shows a detailed structure of the shift register circuit 1, 2, or 3. As shown, a memory 102, a counter 103, D flip-flops (hereinafter abbreviated as DFF) 104 to 106, a latch 107,
Strobe signal generation circuits 108 and 109, negation (NOT) circuit 110,
Comprising 111. Further, a data input terminal 120, a data output terminal 121, and a control input terminal 122 are provided.

When the WRITE ENABLE signal is 1, the memories 101 and 102
Write the data given by the DATA IN signal to the address given by the DDRESS signal. And the OUTPUT ENABLE signal is 1
In the case of, the data at the address given by the ADDRESS signal is
Output as A OUT signal.

When the COUNT signal is 0 and the LOAD signal is 1, the counter 103 takes in the data of the IN signal internally and
When the LOAD signal is 0, the data taken in is incremented by 1. Then, the internal data is always output as an OUT signal.

The DFF 105 and the latch 107 are for temporarily holding input data and output data, respectively. When the LOAD signal is 1, the input data is taken in, and when the LOAD signal is 0, the current value is held. The current value is always output to the output side.

The strobe signal generation circuits 108 and 109 generate read strobe signals for reading the contents of the memory.

The shift register circuit can be configured by connecting DFFs in a required number of stages in series. However, in order to reduce the size of the circuit, the present embodiment uses two blocks of memory. That is, the n-stage shift register circuit outputs the data n clock cycles earlier at the same time as when new data is input. However, since a normal memory cannot perform a read operation and a write operation at the same time, this is realized by preparing two memories and accessing them alternately.

FIG. 5 is a diagram for explaining the operation of the shift register circuit of FIG. The figure shows an example of an eight-stage shift register. The first data “0” is stored in the memory 101 at address 0
At that time, and the data at address 0 of the memory 102 is read (FIG. 5 (a)). The second data "1" is memory
The data is written to the address 0 of the memory 102, and at that time, the data at the address 1 of the memory 101 is read (FIG. 5B). In this way, reading and writing are repeated alternately, and when the read or write address becomes 3 (corresponding to the number of shift stages / 2−1), it returns to 0 again, and the same operation is repeated. Thereby, the ninth of FIG.
As shown in the state of the step (FIG. 5 (i)), when the ninth data "8" is input, the data "0" eight steps before is output.

The procedure for accessing the memory to realize such an operation is as follows.
It can be made by the method shown in FIG. First, a sequence 123a that is increased by one step is generated. This sequence
123a can be realized by the counter 103 in FIG. However,
Count 103 when the number reaches 8 (equivalent to the number of shift steps)
Is reset to return to 0. Next, this sequence 12
A sequence 124a is generated by dividing 3a by 2. The sequence 124a is obtained by a bit signal excluding the least significant bit of the output of the counter 103. A step whose remainder after division by 2 is 0 is set as a read timing, and a step of 1 is set as a write timing. The remainder divided by 2 is the counter 10
Given by the least significant bit of the output of 3. Thereby, the access procedure of the memory 101 is completed. Meanwhile, memory 101
Sequence that delays the access procedure by one step with OFF104
125a is an access procedure of the memory 102. In FIG.
The second and subsequent numbers in the sequence correspond to the operations (a) to (1) in FIG.

In general, such a shift register circuit including two memories can be configured in a similar manner for an n-stage (where n is an even number) shift register circuit. That is, a memory of n / 2 words may be prepared, and the sequence 123a may be increased to n-1 in the generation of the memory access procedure.

In FIG. 4, a counter 103 is for generating a sequence 123a, and a signal 124 of the output 123 excluding the least significant bit corresponds to the sequence 124a. Also, the signal 126 of the least significant bit of 123 corresponds to the remainder obtained by dividing the sequence 123a, so that an access control signal for the memory 101 is generated. On the other hand, the access control signal of the memory 102 is signal 1
A signal 125, which is obtained by delaying 24,126 by one clock cycle by DFF104,
Generated by 127.

The control input terminal 122 is connected to the HB signal, and puts the shift register circuit into an operation state while input data is valid, and puts the shift register circuit into a hold state when input data is invalid. At first, the input data is invalid, the control input terminal 122 becomes 0,
The counter 103 is loaded with 0. When the input data becomes valid, the control input terminal 122 becomes 1, and the counter 103 starts counting up. When image data for one line is input and the input data becomes invalid again, 0 is loaded to the counter 103.

If the period during which the input data is valid is n clock cycles, the counter 103 repeats counting up from 0 to n-1. Therefore, the entire shift register circuit functions as an n-stage shift register.
Also, during the HB timing period when the input data is invalid,
Since the counter remains at 0 and the load signal of the DFF 105 becomes 0, the input data is not read into the shift register circuit. Further, since the load signal of the DFF 104 also becomes 0, the access signal to the memory 102 is retained when the input data was last valid, and is inherited without inconsistency when the next input data is valid. be able to.

As described above, the number of shift stages in the shift register circuit of the present embodiment is variable and can be determined by the HB signal input from the control input terminal. That is, no matter what the number of pixels in one line or the length of the HB timing, if the HB signal corresponding to the pixel data is input, correct operation is possible. Therefore, the implemented memory 101,
As long as the number of words of 1-2 permits, it is possible to deal with image data of any size.

In FIG. 1, since the operation / hold states of the shift register circuits 1, 2, and 3 are controlled by the same control signal line 60a, they are collectively referred to as (s + s + 1).
It can be a bit shift register. Thus, except for the memories 101 and 102 and the OFFs 105 and 107 in FIG. 4, two sets of control units including the counter 103 and the DFFs 104 and 106 can be omitted.

(Look-up table circuit) FIG. 7 shows the look-up table circuit 4, 5, 6, 7, 8 or 9.
Shows the detailed structure of. As shown, a memory 401, multiplexers (MUX) 402 and 403 are a constant register (REG) 404, latches (LAT) 405 and 406, and tri-state buffers 407 and 40.
8. A mode switching logic circuit 409 is provided. Also,
Address input terminals 410, 411, data input terminals 412, data output terminals 413, 414, port select signal input terminal 415, mode switching signal input terminal 416, write control signal input terminal 417, read control signal input terminal 418, monitor output control signal terminal 419 , A monitor output signal terminal 420 is provided. Each of the multiplexers 402 and 403 has two input terminals and one output terminal, and outputs a 0-side input when the A signal is 0, and outputs a 1-side input when the A signal is 1. When the ENABLE signal is 0, the tri-state buffers 407 and 408 are in a disconnected state between the input and the output, and when the ENABLE signal is 1, they are in the connected state. The constant register 404 captures input data when the LOAD signal is 1,
When it is 0, the current value is held. The current value is always output. Functionally similar to DFF.

The look-up table circuit has two operations, a normal operation as a look-up table for outputting the contents of the address using the input data as an address, and a setting operation for setting the contents of the table and confirming the set contents. Need to do. For this reason, a memory having two address input terminals and two data output terminals is required. As a memory having such terminals, there is a dual-port memory, which is a circuit occupying a larger area than a normal memory. On the other hand, a normal memory is compact, but has only one address input terminal and one data output terminal. The lookup table circuit shown here realizes a compact circuit by adding a control circuit to a normal memory.

Next, the operation of the lookup table circuit will be described. The function of this circuit is controlled by a port select signal 415, a mode switching signal 416, a write control signal 417, and a read control signal 418. Table 1 shows the operation of the circuit depending on the state of each signal.

The address input terminal 410 and the data output terminal 413 are terminals for performing address input and data output during normal operation of the lookup table. On the other hand, address input terminal 41
1 and the data output terminal 414 and the data input terminal 412 are terminals for setting and confirming the contents of the lookup table during the setting operation. The port select signal 415 switches the connection between the address input terminals 410 and 411 and the memory for normal operation and setting operation of the lookup table.

The mode switching signal 416 is a control signal for selecting whether to perform reading / writing of data from / to the look-up table circuit to the memory 401 or to the constant register 404. In the former case, this circuit functions as an original look-up table. This is called a lookup table mode. In the latter case, during normal operation, the contents of the constant register 404 are always written to the data output terminal 413, regardless of the contents of the address data input from the address input terminal 410.
In the setting operation, data reading and writing are performed on the constant register 404. This is called a constant table mode. This function is used for an operation test of an arithmetic element described later.

When the monitor output control signal 419 is 1, the monitor output signal 420 always outputs the contents of the address input terminal 410 as it is. This is also used for an operation test of an arithmetic element described later.

(Arithmetic Circuit) FIG. 8 shows a detailed structure of the arithmetic circuit 10, 11, 12, or 13.
Addition / subtraction circuit 1001, multiplexer (MUX) 1 as shown
002,1003, Exclusive OR circuit (hereinafter abbreviated as EOR) 1004, Negation circuit (hereinafter abbreviated as NOT) 1005,1006, DFF1
007 is included. Addition / subtraction circuit 101 with limiter by addition / subtraction circuit 1001, multiplexer 1002, EOR1004
0 is configured. Also, data input terminals 1020, 1021,
An operation result output terminal 1022 is provided with an operation function selection terminal 1023 to which a select (SELECT) signal is input. Addition / subtraction circuit 10
01: Addition A + B of input when SELECT signal is 1,
When 0, subtraction AB is performed. Operation result overflows,
Or, when an underflow occurs, 1 is output to the OVERFLOW signal. The EOR 1004 is a circuit that takes an exclusive OR of s bits to 1 bit, and has an input a _i (i = 1
... S) and the output of b is a _i EOR b (i = 1... S)
Becomes In FIG. 8, EOR is performed between the s-bit constant data 2 ^S−1 output from the constant data generation circuit 1008 and the most significant bit of the output of the addition / subtraction circuit 1001. That is, the EOR 1004 and the constant data generation circuit 1008 form an upper and lower limit value generation circuit.

Next, the operation of the present arithmetic circuit will be described. When the select signal 1023 is 1, the arithmetic circuit uses the data input terminal 1020
The sum A + B of the value A and the value B of the data input terminal 1021 is output from the operation result output terminal 1022. When the SELECT signal 1023 is 0, the maximum value of A and B, that is, max (A, B) is output. . However, the numerical value is expressed as signed data of s bits, and when the operation result exceeds the range that can be expressed by s bits, a value truncated within the expressible range is output.
In other words, when it exceeds in the positive direction, 2 ^s-1 -1 is output as the calculation result, and when it exceeds in the negative direction, 2 ^S-1 is output. For example, when s = 8, data that can be represented is from −128 to +127.
If the calculation result exceeds this, the calculation is terminated at +127 for a positive number and at -128 for a negative number.

First, the part of the addition / subtraction circuit with limiter 1010 will be described. When the operation result of the addition / subtraction circuit 1001 causes an overflow or an underflow, the OVERFLOW signal becomes 1, and the multiplexer 1002 outputs data on the 1 side. At this time, if the operation result overflows, the most significant bit of the operation result becomes ¹ , and the value obtained by inverting the constant 2 ^s-1
2 ^s−1 −1 is output to the subsequent circuits via the multiplexer 1002. If the operation result is an interflow,
The most significant bit of the operation result becomes 0, and the constant 2 ^s-1 is output as it is. This will be described in detail in the case where s = 8. The constant 2 ^s-1 is expressed as “1000000” in binary bit representation.
(2). In the case of overflow, since the operation result exceeds the positive maximum value “0111111” (2) = 127, the maximum value bit becomes 1, the constant “1000000” (2) is inverted by EOR, and “0111111” (2), That is, 127 which is the positive maximum value is output. On the other hand, in the case of an underflow, the operation result is smaller than the negative minimum value “10000000” (2) = − 128, so that the most significant bit is 0, and the constant “10000000” (2), that is, the negative minimum value −128 is output. Is done. Thus, the addition / subtraction circuit 1
An adder / subtractor circuit 1010 with a limiter can be configured by the 001, the EOR 1004, and the multiplexer 1002.

In the operation on image data, inconvenience often occurs when the operation result overflows or underflows and the output data jumps out of sequence. For example, in the case of an image smoothing operation, a certain pixel
7 is output, overflow occurs in the pixel next to it, and if it is supposed to be 128, but is output as -128, if this data is input as it is to the differentiation processing circuit, the pixel of this pixel which is originally changing smoothly A large peak appears in the vicinity. By providing a limiter in the addition / subtraction circuit, such inconvenience can be prevented.

Next, the remaining part of the arithmetic circuit will be described. SELE
Addition / subtraction circuit with limiter when CT signal terminal 1023 is 1
1010 outputs the sum (A + B) of the data A and B provided from the data input terminals 1020 and 1021 to the multiplexer 1003. At this time, since the B signal of the multiplexer 1003 becomes 0, the 00 of the multiplexer is input to the 10 side, that is, the sum A + B is output in any case. On the other hand, when the select signal terminal 1023 is 0, the addition / subtraction circuit with limiter 1010 outputs the difference between A and B (AB). At this time, B of multiplexer 1003
The signal becomes 1 and the A signal is connected to the inversion of the most significant bit of (AB), so that if (AB) is positive,
Data A, which is an 11-side input, is output, and if negative, data B, which is an 01-side input, is output. That is, this is max (A, B)
It is. Even if AB exceeds the numerical range that can be temporarily represented by the calculation result limit function, if AB is positive, it is output as a positive number if it is positive, and it is output as a negative number if it is negative. Can determine the maximum value.

(Control Circuit) FIG. 9 shows a detailed structure of the control circuit 14. As shown, control registers 1401 and 1402, decoder circuits 1403 and 1404,
Tri-state buffers 1405, 1406, AND1407, OR1408,
It is formed with NOR1409 and NOT1410. Further, an address input terminal 55, a control data input terminal 56, a read / write control terminal 55b, an output control terminal 55a, an element selection signal terminal 55c, and a data output terminal 1426 are provided. In addition, terminal 142
0,1421,1422,1423,1424 are lookup table circuits 4,
5, 6, 7, 8, 9 port select signal 415, mode switching signal 416, write control signal 417, read control signal 418,
The terminal 1425 is a signal terminal connected to the monitor output control signal 419, and the terminal 1425 is a signal terminal connected to the SELECT signal terminal 1023 of the arithmetic circuits 10, 11, 12, and 13. The data output terminal 1426 is connected to the control data output terminal 58 together with the data output terminals 414 of the lookup table circuits 4, 5, 6, 7, 8, and 9.

Next, the operation of the control circuit thus configured will be described.

The address, control data, read / write control signal, and output control signal given from the outside of the element (the image processing apparatus in FIG. 1) are obtained by a logic circuit including OR1408, NOR1409, and NOT1410 when the element selection signal 55c is 0. Is taken into the device. Therefore, normally, the element selection signal 55c is set to 1
By setting the element selection signal 55c to 0 after the state of the other signals is determined, a correct signal can be input. When the read / write control signal 55b is 1, the read operation is performed on the element, and when it is 0, the write operation is performed. When the output control signal 55a is 0, data can be output from the control data output terminal 1426 (58). When the output control signal 55a is 1, the terminal 1426 is disconnected and no data is output.

The address data applied to the control circuit 14 is s + 3
Consists of bits. The upper 3 bits are the decoder
An input signal is input to 1403, and an output signal of the decoder 1403 outputs an access signal to one of the six look-up table circuits and the control registers 1401 and 1402. That is, in the case of writing data to the lookup table circuit, 1 is output to one of the six write control signals 1422, and in the case of reading, 1 is output to one of the six read control signals 1423. Is output. At this time, the lower s bits of the address data are connected to the address input terminals 411 of the six lookup table circuits, and are used as address data of the lookup table circuit selected by the upper three bits. In the case of writing to the control registers 1401 and 1402, the LOAD signal of the selected control register 1401 or 1402 is set to 1, and in the case of reading, the ENABLE signal of the tri-state buffer circuits 1405 and 1406 connected to the output of the selected control register is set. Set to 1 to enable output from the data output terminal 1426. Switching between reading and writing is performed by an AND circuit 1407. The lower 3 bits of the output of the control register 1401 are connected to a decoder 1404, and the output of this decoder
One of the monitor outputs of the look-up table circuits is output from a monitor output terminal 54 (FIG. 1). The other output of the control register 1401 and the output of the control register 1402 are respectively the port select signal 415 of the lookup table circuit, the mode switching signal 416, and the output of the arithmetic circuit.
SELECT signal terminal 1023
By changing the data of 1,1402 as described above, the functions of the lookup table circuit and the arithmetic circuit are switched.

(How to Use the Image Processing Apparatus) Here, how to use the image processing apparatus in FIG. 1 in actual use will be described with reference to FIG.

First, the upper 3 bits of the address data are set to “110” (2)
Then, the fourth and fifth bits of the control register 1401 are set to 1 (S101). As a result, each look-up table circuit enters a setting operation state, and the function of the arithmetic circuit is added.
Next, the upper 3 bits of the address data are set to "111" (2).
The lower 6 bits of the control register 1402 are set to 0 (S102). As a result, all the look-up table circuits are in the look-up table mode. In this state, while changing the upper 3 bits of the address data from 0 to 5, the address in the lookup table is specified by the lower s bits, and the table data of the 0th to 5th lookup tables is set.) S103 to S109). When all the data settings are completed, the fourth bit of the control register 1401 is set to 0, and the lookup table is set to the normal operation state (S110). Thus, the image processing apparatus shown in FIG. 1 performs an arithmetic operation on the set table data for the image data input from the data input terminal 50.

On the other hand, when the fifth bit of the control register 1401 is set to 0,
The function of the arithmetic circuit is to calculate the maximum value, and for each pixel of the input image data, the pixel data having the largest value among the four adjacent pixels including the center is output. By setting the lower 3 bits of the control register 1401 to any one of 0 to 5, the input data to the 0th to 5th corresponding look-up table circuits is output from the monitor output terminal. The lower 6 bits of the control register 1402 are 0
And the fifth look-up table circuit is associated with the first look-up table circuit. When "1" is set, the corresponding look-up table circuit enters the constant table mode.

The setting state of the control registers 1401 and 1402 can be read from the control data output terminal (1426) 58 by performing a read operation by designating addresses corresponding to these registers. The table data of the look-up table circuit is read out by setting the fourth bit of the control register 1401 to 1 and then specifying the look-up table circuit by the upper 3 bits of the address and the table address by the lower s bits. , The data can be read from the control data output terminal 58.

(Test method of the present image processing apparatus) When the present image processing apparatus is configured by an LSI, the manufactured L
Unless all SI circuits operate normally, the function as an image processing device cannot be obtained. Therefore, it is necessary to perform an operation test of each circuit of the LSI. However, since it is impossible to measure a signal by applying a probe to an arbitrary signal line on an LSI chip, this test must be performed using only signal terminals that are externally drawn from the chip. The arithmetic element has a signal terminal and a special function for systematically performing an operation test of such a circuit.

This image processing apparatus includes a shift register circuit, a look-up table circuit, an arithmetic circuit, a control circuit, and a control signal delay circuit as shown in FIG. The operation test of the circuit is performed for each of these constituent circuits in accordance with the procedure shown in FIGS.

First, a test of the control circuit 14 is started. As shown in FIG. 11, the control circuit 14 tests the control registers 1401 and 140
Then, arbitrary data is written in 2 (S201), and when the data is read, it is confirmed that the data is as written (S202, S203). If the written data differs from the read data, the control register or the write / read function is not functioning normally, and the test ends here (S221).

Next, the fourth bit of the control register 1401 is set to 1 and the lower 6 bits of the control register 1402 are set to 0, and the lookup table circuit is set to the lookup table mode and the setting operation state (S204, S205). Then, writing and reading of table data are sequentially performed for the six lookup table circuits (S206 to S214). Here, if the written data and the read data are different (S210), the test ends because the memory of the look-up table circuit or the write / read function is not working properly (S222).

Next, although not shown, each of the look-up table circuits has the lower 6
The bit is set to 1, each lookup table circuit is set to the constant table mode, and the same test is performed on the constant register.

Next, a test of the shift register circuit and the signal delay circuit is performed according to the procedure shown in FIG. The lower 3 bits of the control register 1401 are appropriately switched from 0 to 5 (S241, S244, S247), and an appropriate data sequence is input from the data input terminal 50 and the control signal input terminals 51a, b (S242, S245, S248). Then, the data input to each look-up table circuit is output to the monitor output terminal 54. It is confirmed that the data output from the monitor output terminal 54 is the same as the data sequence input from the data input terminal and is delayed by a predetermined cycle time (S243, S246, S249). Also, it is confirmed that the data input from the control signal input terminal is output from the control signal output terminal with a delay of a predetermined cycle time (S243, S246, S249).

Finally, the operation circuit is tested according to the procedure shown in FIG.

First, the function of the arithmetic circuit is added by setting the fifth bit of the control register 1401 to 1, the fourth bit of the control register 1401 is set to 1 (S2521), and the lower 6 bits of the control register 1402 are set to 1
To set the lookup table circuit in the constant table mode and the setting operation state (S253). Also, the control register
The input data of the look-up table circuit 9 is connected to the monitor output terminal with the lower 3 bits of 1401 as 101 (2) (S252). Here, appropriate data is written into each constant register (lookup table circuit) (S254), and it is confirmed that the operation result output from the monitor output terminal at that time corresponds to the written data (S255). The same test is performed for the maximum value calculation with the fifth bit of the control register 1401 set to 0 (S256 to S258).

According to the above procedure, the operation test of each constituent circuit can be individually performed, and the test of all the circuits can be performed without omission. In addition, in addition to these tests, inputting appropriate sample image data and confirming that the image processing apparatus as a whole performs calculations as expected,
A complete test can be performed.

(System Configuration Example Using the Present Image Processing Apparatus) FIGS. 15 and 16 show an embodiment of an image processing system configured using the present image processing apparatus.

In FIG. 15, the image processing devices 10001, 10002,
10003 are connected in parallel, different look-up tables are provided to each image processing apparatus, and different mask calculations are performed. These calculation results are added by a three-input addition circuit 10004 and output. This makes it possible to obtain an image in which a plurality of feature amounts of the image are superimposed. Since the same control signal is input to the three image processing apparatuses, image processing is performed at the same timing. Therefore, the addition circuit
The timings of the input image data of the three systems 10004 are the same and can be connected without providing a special timing adjustment circuit. If a delay circuit for control signals similar to that of the image processing apparatus shown in FIG. 1 is provided in the adder circuit 10004, the timing of the image data and the control data can be aligned on the output side of the adder circuit 10004. The result can be easily restored as a video signal.

FIG. 16 shows a configuration example of a system including a loop in a data flow. Reference numerals 20001, 20002, and 20003 denote image processing apparatuses according to the present invention, 20004 denotes a two-input addition circuit, and 20005 denotes a dual-port memory. In this system, a dual port memory 20005 is used as a unit for timing matching. That is, when a loop is included in the data flow, a part where the timing is always different is generated somewhere. To make up for this, dual port memory 20
Use 005. This memory synthesizes an address based on a control signal, and writes and reads image data at that address. The writing portion 20005a and the reading portion 20005b operate independently by different control signals.

Thus, using the image processing device according to the present invention,
The system configuration is such that the image data signal and the control signal are always arranged in synchronization. If an image processing device with various functions that synchronizes the image data signal and the control signal at the input / output terminals is prepared, a system that performs complicated processing easily by simply connecting those image processing devices is provided. Can be configured. Further, in such a system, a video signal can be restored from image data of an arbitrary connection portion of each image processing apparatus, so that it is easy to visually confirm the state of processing of image data.

〔The invention's effect〕

As described above, the present invention has the following effects.

According to the data processing device of the present invention, each data including one data input in time series is delayed by the delay circuit according to the relative relationship of the time series, and the same timing as the data input last is used. Is output. Such a delay circuit can be easily formed by hardware.
An arithmetic processing circuit for inputting each data output from the delay circuit and performing predetermined arithmetic processing can be realized with a simple configuration using hardware. In addition, the flow of signals in the data processing device is simplified, and in addition, if the circuits are driven in synchronization with a common clock panel, circuit design and operation tests become easier.

Further, according to the image processing apparatus of the present invention, adjacent pixel data used in the arithmetic processing of one pixel data is adjusted to the same timing by the pixel data delay circuit, and the constant multiplication processing of the local area operation of the pixel data is looked up. Since the output processing is performed using the up-table circuit and the addition processing of the outputs is performed by the arithmetic processing circuit including the addition circuit element, the signal flow in the image processing apparatus is simplified. In addition, if these circuits are configured to be driven in synchronization with a common clock pulse, circuit design and operation tests are facilitated.

Further, a shift register circuit constituting an image data delay circuit is constituted by two memories and a memory drive circuit, and pixel data input in a time series is divided by the memory drive circuit into two.
Since the pixel data is read from the two memories while writing to the two memories alternately with a delay of the delay time, the unit delay circuit can be made smaller than in the case of serial connection according to the delay time. . In addition, the counter is driven according to the input of each pixel data, and reset by the HB signal, and the count value is used as a memory address, so that the necessary delay is performed according to the number of pixel data. A long shift register can be realized. In addition, since the counter is reset by the HB signal and the shift register is held, unnecessary shift stages for blanking timing can be saved.

In addition, since the constant multiplication operation for the operation processing of the local area pixels is performed by a look-up table circuit using a memory, the size of the operation circuit can be reduced. The processing device can be mounted on a one-chip LSI. Moreover,
Since the look-up table circuit is used, it is possible to perform not only a constant multiplication operation but also an operation process using an arbitrary function, and it is possible to provide the operation contents with considerable versatility. In addition, the circuit operation test can be easily performed according to the lookup table provided with the constant register. In addition, it is possible to provide an additional function that a constant output can be temporarily obtained without rewriting the lookup data during the arithmetic processing of the image data.

Further, according to the arithmetic circuit for performing the addition / subtraction with the upper / lower limiters, even if the operation result overflows or underflows, the output data does not fly discontinuously. As a result, meaningful calculation results can be obtained as image data close to the original smooth change. In addition,
A circuit for selecting the maximum value can be easily configured by utilizing the subtraction of the arithmetic circuit with the limiter.

In addition, since the setting state of the control register and the look-up table circuit in the circuit can all be read from the outside via the control circuit, the setting state of the setting state is controlled by software of a higher-level device that controls the image processing apparatus. Even if the information is not stored, the state of the image processing apparatus can be known at any time. As a result, it can be used for function diagnosis in relation to the entire image processing system. Further, it is possible to prevent a bug caused by a mismatch between a state stored by software and an actual state of the image processing apparatus. Further, according to the one provided with the monitor terminal for directly outputting the input address data of the lookup table circuit to the outside, the operation test of the image processing apparatus can be systematically performed.

According to the present invention, an image control signal for recognizing a delimiter of time-series data of each line, which is obtained by scanning two-dimensional pixel data, is input and output in synchronization with the pixel data. In configuring the image processing system using the image processing device, the handling of the data signal lines is simplified, and the system configuration can be systematically performed.

[Brief description of the drawings]

FIG. 1 is a diagram showing the overall configuration of an embodiment of the present invention, FIG. 2 is a diagram for explaining the positional relationship between four adjacent pixels, FIG. 3 is a diagram for explaining the structure of time-series image data, and FIG. Is a diagram showing a detailed structure of the shift register circuit, FIG. 5 is a diagram for explaining the operation of the shift register, FIG. 6 is a diagram for explaining a memory access procedure of the shift register, and FIG. 7 is a detailed structure of the lookup table circuit FIG. 8 is a diagram showing a detailed structure of an arithmetic circuit, FIG. 9 is a diagram showing a detailed structure of a control circuit, FIG.
FIG. 10 is a diagram for explaining how to use the image processing apparatus of the present invention,
11 and 14 are diagrams for explaining the procedure of an operation test of the image processing apparatus according to the present invention, and FIGS. 1, 2, 3, ... shift register circuit, 4, 5, 6, 7, 8, 9, ... look-up table circuit, 10, 11, 12, 13, ... arithmetic circuit, 14
... Control circuit, 15 to 38 ... Signal delay circuit, 50 ... Data input terminal, 51a, 51b ... Control signal input terminal, 52 ... Data output terminal, 53a, 53b ... Control signal output terminal, 54 ... ... Monitor output terminal, 55 ... Address input terminal, 56 ... Control data input terminal, 57a, 57b, 57c ... I / O control terminal, 58 ...
... Control data output terminal, 59 ... Clock signal input terminal.

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-62-221076 (JP, A) JP-A-60-231998 (JP, A) JP-A-61-131909 (JP, A) JP-A 63-221 26778 (JP, A) JP-A-62-219081 (JP, A) JP-A-53-148232 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06T 1/20

Claims (15)

(57) [Claims] 1. A plurality of data are input in a time series, and for one of the plurality of data, a certain number of data having a certain temporal relative relationship with the one data is used. A data processing device that performs predetermined arithmetic processing and outputs the data,
A data delay circuit that delays each data including the one input data according to the relative relationship, and outputs the data at the same timing as the last input data;
An arithmetic processing circuit for inputting each data output from the data delay circuit and performing the predetermined arithmetic processing, the data being provided in synchronization with the data input in time series. A data processing device, comprising: a control signal delay circuit for delaying a control signal for identifying a data partition or the like and outputting the control signal in synchronization with an output timing of data output from the arithmetic processing circuit. 2. A pixel data delay circuit, a look-up table circuit, and an arithmetic processing circuit, wherein the pixel data delay circuit inputs pixel data in a two-dimensional array in a time-series manner. One pixel data and adjacent pixel data of a pixel adjacent to a pixel corresponding to the one pixel data are respectively delayed according to the time-series relative relationship, and the same as the last input neighboring pixel data. The look-up table circuit has a memory provided in correspondence with each pixel data input from the pixel data delay circuit and a drive circuit for the memory. Processing data obtained by processing each pixel data by a predetermined function in an area corresponding to each pixel data as an address is stored. The driving circuit reads the processing data corresponding to the input pixel data from the memory and outputs the processing data.The arithmetic processing circuit inputs the output data of each of the lookup table circuits. And an image processing apparatus configured to perform processing by predetermined addition and subtraction, and to output an image control signal for identifying a blanking period included in the pixel data, and to delay the image control signal. An image control signal delay circuit is provided, and the image control signal delay circuit delays the image control signal by the pixel data delay circuit, the look-up table circuit, and the arithmetic processing circuit. The pixel data delay circuit is synchronized with a blanking period of the image control signal. The image processing apparatus input of the pixel data is assumed to be held by. 3. The pixel data delay circuit includes a shift register circuit having two memories and a drive circuit for the memories, and delaying the input n-bit time-series pixel data by n bits and outputting the data. Wherein each of the memories has a memory area of at least n / 2 words, and the memory drive circuit alternately writes sequentially inputted pixel data to the two memories, and 3. The method according to claim 2, wherein the data is alternately read with a delay of n bits.
An image processing apparatus according to claim 1. 4. The look-up table circuit includes a memory, a constant register, and first and second multiplexers, wherein the first multiplexer inputs an address in a normal mode and an address in a setting mode, One of the second addresses is selected by a separately input selection signal and used as an address input of the memory. The second multiplexer inputs the output of the memory and the constant register, and One of the two outputs is selected and output by a mode switching signal input separately, and the memory stores setting data input separately according to an input write control signal in a memory area corresponding to the address input. Wherein the constant register accumulates setting data separately input by the mode switching signal. Claim 2
An image processing apparatus according to claim 1. 5. An addition / subtraction circuit in which the arithmetic processing circuit adds or subtracts two input data in accordance with a separately input select signal, and an upper / lower limit value generating circuit for generating a predetermined upper limit or lower limit. A multiplexer for inputting the operation output of the addition / subtraction circuit and the upper limit value or the lower limit value of the upper / lower limit value generation circuit, and selecting and outputting one of them. The multiplexer outputs an overflow signal or The image processing apparatus according to claim 2, wherein the upper limit value or the lower limit value is selected and output when an underflow signal is output. 6. The arithmetic processing circuit is provided with a second multiplexer that inputs the output of the addition / subtraction circuit and the two input data and selects and outputs one of them. When the overflow signal is output when the select signal is subtracted, the input data on the subtraction side of the two input data is output as the maximum value, and when the select signal is added, the output of the multiplexer is output. The image processing apparatus according to claim 5, wherein the image processing is performed. 7. A means for outputting the select signal to the arithmetic circuit, setting data to the look-up table circuit, an address of a setting mode, an address selection signal, the write control signal, and a mode switching signal. 7. The image processing device according to claim 4, further comprising: a control circuit including means for outputting the following. 8. The look-up table circuit includes a memory, a constant register, first and second multiplexers,
A first multiplexer that inputs a normal mode address and a setting mode address, and selects one of the second addresses by a separately input selection signal; The second multiplexer inputs the output of the memory and the constant register, selects one of the two outputs by a mode switching signal input separately, and outputs the selected output. The memory stores setting data separately input by an input write control signal in a memory area corresponding to the address input, and the constant register is input separately by the mode switching signal. The first 3-stated buffer is configured to accumulate setting data by a control signal input separately. 4. The method according to claim 1, wherein a normal address is output to the outside, and the output of the second multiplexer is output to the outside by a control signal input separately from the second 3-stated buffer. 3. The image processing device according to 2. 9. A means for outputting the select signal to the arithmetic circuit, setting data to the look-up table circuit, an address of a setting mode, an address selection signal, the write control signal, and a mode switching signal. 9. The image processing apparatus according to claim 8, further comprising: a control circuit including: means for outputting the control signal; and means for outputting the control signal to the first and second 3-steady buffers. 10. A plurality of image processing apparatuses according to any one of claims 2, 3, 4, 5, 6, 7, 8, and 9, wherein the plurality of image processing apparatuses are connected in series and / or in parallel. An image processing system configured as follows. 11. A shift register circuit comprising two memories and a drive circuit for the memories, wherein the shift register circuit outputs input time-series data delayed by n steps, wherein the memories cannot be read and written at the same timing. , Each having a memory area of at least n / 2 words, wherein the memory driving circuit
When writing to one of the two memories, the data written n steps before is read from the other memory at the same time, and this is alternately performed for the two memories. Wherein the read operation of the output data is performed at the same timing. 12. A look-up table circuit having a memory, a constant register, and a multiplexer, wherein the multiplexer inputs the outputs of the memory and the constant register, and receives one of the two outputs separately. The multiplexer is connected to a terminal for directly outputting to the outside at the same time as being supplied as an input to a subsequent data processing circuit. Look-up table circuit. 13. A look-up table circuit having a memory and a multiplexer, wherein the multiplexer inputs an address in a normal mode and an address in a setting mode, and selects one of the second addresses by a separately input selection signal. The memory is configured to store setting data separately input according to an input write control signal in a memory area corresponding to the address input. At the same time as being supplied as an input to the subsequent data processing circuit, it is connected to a terminal that directly outputs to the outside through a gate circuit controlled by the write control signal, and when the write control signal is false in the setting mode, The data in the memory area corresponding to the address in the setting mode is Look-up table circuit, characterized in that to be output to the terminal via. 14. An addition / subtraction circuit for adding or subtracting two input data in accordance with a separately input select signal, an upper / lower limit value generating circuit for generating a predetermined upper limit or lower limit, and an upper / lower limit value generator. A multiplexer for inputting an operation output and an upper limit value or a lower limit value of the upper / lower limit value generating circuit, and selecting and outputting one of them; the multiplexer outputs an overflow signal or an underflow signal from the addition / subtraction circuit; An arithmetic circuit configured to select and output the upper limit value or the lower limit value. 15. A second multiplexer for inputting an output of said addition / subtraction circuit and said two input data and selecting and outputting one of said two data, said second multiplexer being provided when said select signal is subtraction. When the overflow signal is output to
15. The image processing device according to claim 14, wherein the input data on the subtraction side of the two input data is output as a maximum value, and the output of the multiplexer is output when the select signal is addition. .