JP2877381B2 - Display device and display method - Google Patents

Abstract

There is provided a display apparatus which uses a display panel using a liquid crystal having a bistability or a memory performance such as a ferroelectric liquid crystal and can display image data in various display modes in which the number of pixels (resolution), display color, minimum pixel unit, and the like respectively differ. The display apparatus comprises: a memory to store the image data; a pixel data output circuit to output the image data stored in the memory every pixel data; a converter to convert the pixel data which was output from the pixel data output circuit into binary data which is displayed on the display panel; a display data output circuit for converting the binary data converted by the converter into the display data corresponding to the display modc and outputting; and a display controller for allowing the image data which was output by the display data output circuit to be displayed on the display panel. A multiplexer is used as a pixel data output circuit. An RAM in which binary data has been stored is used as a converter.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display device such as a ferroelectric liquid crystal display device, which is bistable (memory) to an electric field.
The present invention relates to an image information output circuit suitable for being applied to a display device using a binarized display element having the following.

[Conventional technology]

In recent years, displays such as personal computers and workstations have rapidly increased in size and resolution, and there are many display modes including conventional ones. Taking the graphics environment of a commonly used personal computer of IBM (registered trademark) as an example, CGA (Color Graphic Adapter), RGA (Enhanc
ed Graphic Adapter), VGA (Video Graphic Adapter)
There are over ten different display modes, each with different resolutions and different numbers of colors that can be displayed.

 FIG. 10 is a list thereof.

(1) Display Color As can be seen from FIG. 10, the number of bits per pixel (bits / pixel) differs depending on each display mode, and the storage format in the image memory (VRAM) also differs. Naturally, a mode in which the number of configuration bits per pixel is large enables multi-color display.

Here, as an example, a display mode 13 (h) (VGA) capable of performing multicolor display in a graphics environment of a personal computer of IBM Corporation will be described below. First, when a certain address of the VRAM is accessed, the image data (bit / pixel: mode 13 (h)) in the VRAM is used as an address for selecting a color register in a color palette in which color information is stored in advance. work. In the case of VGA, the color pallet has 256 color registers of 18 bits (6 bits each for R, G, B), and color information is stored in these color registers. When one color register is selected from 256 lines by the image data from VRAM, R, G, B
Are read out and are led to a DA converter located in the same color palette.
The DA converter provided for each of R, G, and B is
The 6-bit color data is converted into an analog signal and sent to a display (CRT).

Such a color information output method (color pallet + analog output) is capable of realizing multi-color display for the amount of data in VRAM, and by rewriting the data in the color register without having to rewrite the data in VRAM. It has the advantages of being able to change the color on the display screen and of reducing the number of connections to the display, and is a standard method mainly for personal computers at present.

(2) Resolution In FIG. 10, the resolution also differs for each display mode. For example, in the case of mode D (h), 320 × 200 pixels (picture element) and in the case of mode 12 (h), 640 X 480 pixels. It has been relatively difficult to support all of these various display modes on a single display (CRT). Conventionally, display modes that can be displayed are defined (restricted). is there. Some auto-tracking CRTs called "multi-scan" or "multi-sync" switch the electron beam scanning frequency according to each display mode to support a relatively wide range of display modes. The method is taken. For this reason, when the display is performed in a display mode with a small amount of display information (low resolution), characters and numerals are often displayed with a missing edge.

[Problems to be solved by the invention]

As described above, when display is performed by applying various display modes having different display colors and resolutions to a display device using a liquid crystal having a memory property such as a ferroelectric liquid crystal, unlike the case of displaying on a CRT or the like, You have to consider things like that.

(1) Display color In the case of a display device using a binarized display element typified by a ferroelectric liquid crystal display device or the like, an analog (depth direction) within one pixel (picture element) like a CRT or the like ) It is difficult to express gradation, that is, to three-dimensionally display gradation.
When grayscale display is performed by a binarized display element, a process of developing grayscale (color) data in the depth direction in the horizontal direction (spreading direction) is performed, and two-dimensional display (area grayscale) is performed. Is common. Therefore, when displaying various display modes having different display colors on a ferroelectric liquid crystal display device or the like, the gradation (color) data in the depth direction for the CRT is originally determined according to the display mode. Must be converted into gray scale data in the horizontal direction (spreading direction) in accordance with the arrangement.

(2) Regarding resolution When displaying on a display device such as a ferroelectric liquid crystal display device with a high resolution (1000 × 1000 pixels or more) in various display modes conventionally used in a CRT or the like, Since the resolution of the CRT display mode is lower (less display information) than the effective picture element number (resolution) of the liquid crystal display device, extra picture elements (excess picture elements) are generated on the liquid crystal display device side. In such a case, a plurality of vertical and horizontal electrodes are bundled and simultaneously driven on the liquid crystal display device side to perform enlarged display. For example, in a ferroelectric liquid crystal display device of 1280 × 1024 picture elements, an enlarged display of (1) to 4 times can be realized, for example, when displaying a screen of mode D (h) (320 × 200 picture elements).
Even if such an enlarged display is adopted, extra pixels are generated outside the effective display area depending on the relationship between the number of effective picture elements (resolution) of the liquid crystal display device and the resolution of the display mode.

Therefore, it is necessary to perform an appropriate process on a portion (border portion) of the extra picture element outside the effective display area.

When displaying a low-resolution display mode on a CRT, the scanning frequency of the electron beam is reduced and the phosphor screen is decimated and scanned, so that the portion not irradiated with the beam is kept black (dark). However, in the case of a ferroelectric liquid crystal display device, the state of the picture element cannot be guaranteed (bright or dark, on or off) without inputting image data. For this reason, it is necessary to input data to the remaining picture elements and to control the drive.

The present invention has been made to eliminate the above-mentioned problems that cannot be realized by an image information output circuit used in a conventional CRT or the like, and has an object to solve various display modes used in a conventional CRT or the like. It is an object of the present invention to realize an image information output circuit for displaying the screen in the above-mentioned manner on a display device using a binarized display element such as a ferroelectric liquid crystal display device without breakdown.

[Means (and action) for solving the problem]

The display device according to the present invention is a display device capable of displaying image data of a plurality of display modes having different numbers of picture elements, display colors, and the like on a display panel, wherein the display device corresponds to a selected display mode displayed on the display panel. Storage means for storing image data in which one picture element is formed by the number of bits; reading means for reading image data stored in the storage means;
The data of one picture element constituting the image data read out from the storage means is n × by a magnification n (n is a positive number) determined based on the selected display mode picture element number and the picture element number of the display panel. The image processing apparatus includes: a scaling unit that scales data of n picture elements; and a display control unit that displays the scaled image data on the display panel.

The display method according to the present invention is a display method capable of displaying image data of a plurality of display modes having different numbers of picture elements, display colors, and the like on a display panel, wherein the selected display mode is displayed on the display panel. The image data that constitutes one picture element with the number of bits corresponding to the number of bits is stored in the storage means, the image data stored in the storage means is read, and the number of picture elements in the selected display mode and the display The scale factor n (n is a positive number) determined based on the number of picture elements is used to scale the data of one picture element constituting the image data read from the storage means to the data of n × n picture elements. The displayed image data is displayed on the display panel.

With the above configuration, it is possible to efficiently display screens of various display modes used in a conventional CRT or the like on a display screen of a liquid crystal display device.

〔Example〕

FIG. 2 is an overall configuration diagram of a graphics controller and a ferroelectric liquid crystal display device provided on a main device such as a personal computer which is a supply source of image information. The image information output circuit according to the present invention is provided in the graphics controller in FIG.

The display panel is composed of 1024 scanning electrodes and 2560 information electrodes arranged in a matrix, and two ferroelectric liquid crystals are sealed in two glass plates that have been subjected to alignment treatment. , And the information source are connected to the information electrode driving circuit. One pixel (pixel) has a 2-bit / pixel configuration divided into an area ratio of 3: 2 as shown in the circle in the display panel of FIG. Key display is possible.

The display controller receives display information from the image information output circuit according to the present invention, and controls the scan electrode drive circuit and the information electrode drive circuit.

The graphics controller is composed of a CPU (Central Processing Unit, hereinafter referred to as GCPU) and a VRAM (Memory for storing image information) which control the entire display function, and a display interface which is an image information output circuit according to the present invention. It controls the management of display information and overall communication between the CPU and the display device.

FIG. 1 is a configuration diagram of a display interface according to the present invention. The circuit includes a gradation conversion unit 1 for converting image data from a VRAM into area gradation data, a border register 2 for determining data outside an effective display area, a scanning line address generation unit 3, and image data to a liquid crystal display device. And a data selector 4 for converting the data into an output format for transfer. The operation will be described below with reference to the drawings.

(1) Gradation converter The image data stored in the VRAM5 is 4 bits / pixel in mode 3 (h) and mode 13 (h) in the case of the display mode under the graphics environment of IBM as an example. In this case, the number of constituent bits per pixel (picture element) differs for each display mode, such as 8 bits / pixel. In the present embodiment, the image data stored in the VRAM 5 is
It is configured such that 2 bytes (16 bits) are always output by one read operation (access) to the memory. For this reason, the number of picture elements output by one access to the VRAM 5 differs depending on the display mode, for example, mode 3 (h)
In the case of (1), four picture elements are output by one access in the case of mode 13 (h). Palette RAM12 described later
Performs gradation conversion on a pixel-by-pixel basis, so image data read from the VRAM 5 can be converted into a palette RAM 12 on a pixel-by-pixel basis.
Must be led to

The pixel multiplexer was provided for this purpose.
It is 11. FIG. 3 shows an image data conversion format of the pixel multiplexer 11, and these conversion modes are switched by an instruction from the GCPU 6 (see FIG.
Figure). For example, in the display mode 3 (h), the image data of four picture elements (4 bits / pixel) is output from the VRAM by one access.
11 operates in the conversion mode B. In the case of this conversion mode B, the pixel multiplexer 11 converts the data for two picture elements VSD0 to 3 and VSD4 to 7 in the first phase from the data VSD0 to 15 containing the data for four picture elements output from the VRAM5. Extract and store the pallet RAM1 as Q0-3 and Q8-11, respectively.
2, lead to the palette RAM13. Next, in the second phase, this time VS
The data for two picture elements D8 ~ 11 and VSD12 ~ 15 are
３3, Q8〜11 are led to the pallet RAM 12 and pallet RAM 13. As described above, the multiplexer 11 divides the image data into two phases and guides the image data to the pallet RAM units 12 and 13. In FIG. 3, conversion modes A and C are conversion modes when the image data format in the VRAM is 8 bits / pixel and 2 bits / pixel, respectively, as in the case of 4 bits / pixel. The image data is guided to the palette RAM 12 in units of one picture element.

The pallet RAMs 12 and 13 are units for converting picture element data (color information) from the VRAM 5 into ON / OFF data of picture elements of an actual display panel in units of one picture element. The conversion from <depth direction color information> to <horizontal direction gradation information> (area gradation) according to the present invention is realized here. In the embodiment of FIG. 1, two pallet RAMs are provided in parallel, which addresses the fact that the image data conversion speed in the pallet RAM is slower than the required transfer speed to the display device. If the processing speed of the pallet RAM is fast enough, there is no problem at all. Conversely, if the reading speed of the VRAM 5 and the operating speed of the multiplexers 11 and 14 are sufficiently high, the processing speed of the conversion system can be increased by increasing the number of pallet RAMs accordingly.

Each of the pallet RAMs 12 and 13 is composed of 256 8-bit registers, each called a pallet register. The GCPU 6 previously stores gradation information (picture element ON / OFF data) corresponding to picture element color information. Written. In this embodiment, the same gradation information is written in the palette RAMs 12 and 13. The write operation and the read operation to each pallet RAM can be performed at an arbitrary timing, but are usually performed as needed every one horizontal scanning period or every one vertical scanning period.

FIG. 4 shows the relationship between the gradation data (ON / OFF data of picture elements) of the palette register in the palette RAM and the actual picture element arrangement of the display panel. In FIG. 4, (c) is the minimum picture element unit of the display panel used in this embodiment. As described above, one picture element is divided by an area ratio of 3: 2, and is driven independently to realize four-level gradation display. (B) and (a) show handling of one picture element in the enlarged display mode. By collecting 4 picture elements and 16 picture elements and treating them as one picture element, the display can be enlarged twice or four times, and the number of displayable gradations can be increased to eight or sixteen levels. As shown in FIG. 4, the gradation data of the palette register corresponds to the ON / OFF data of each picture element on the display panel 1: 1 without any change.

As shown in FIG. 5, the picture element data (color information) from the VRAM 5 serves as an address for selecting a pallet register of the pallet RAM. For example, when the picture element data (color information) from the VRAM 5 is 4 bits / pixel, one of 16 palette registers is selected. When the picture element data is 8 bits / pixel and 2 bits / pixel, one is selected from 256 and 4 pallet registers, respectively. When a certain palette register is selected, the gradation data PL0-7, PH0-
7 is output and guided to the next-stage pixel multiplexer 14.

The pixel multiplexer 14 is used for ON / OFF data (up to 8 bits of data) of picture elements output from the pallet RAM.
Is converted into the number of bits that can be displayed according to the enlarged display mode (eX.1 ×, 2 ×, 4 ×) of the display panel. FIG. 6 shows the conversion mode of the pixel multiplexer 14. For example, when performing a 2 × (2 ×) enlarged display on the display panel, the conversion mode B is selected. At this time, since the number of gradation data that can be taken per picture element is 4 bits, the 8-bit data PL0 to PL0 output from the pallet RAMs 12 and 13 are output.
7, the lower 4 bits (PL0-3, PH0-7)
Only 0 to 3) are extracted and output as PIX0 to 7.
The conversion modes A and C are four times (4 ×), respectively.
The conversion format at the same magnification (1 ×) is shown.

As described above, the picture element data (color information) in the VRAM 5 is stored in the two multiplexers 11 and 14 and the palette RAM.
Is converted into gradation data on the display panel.

(2) Border register section As described above, when the number of effective picture elements of the liquid crystal display device> the resolution of the display mode, some pattern must be displayed on the remaining picture elements (border section) outside the effective display area. The border register 2 is provided for storing data to be output to the border section. FIG. 7 shows the configuration of the border register. In this embodiment, the border register basically consists of one 8-bit long register, and each bit corresponds to the border data BD.
0 to 7 (FIG. 7). The border register 2 has a so-called double buffer configuration, and can be rewritten from the GCPU 6 at an arbitrary timing. Actual border data is set in a border register output stage at the timing of a horizontal synchronizing signal or a vertical synchronizing signal. The timing of transmitting the data set in the border register 2 is controlled by horizontal and vertical blank signals (HBlank, VBlank). Basically, as shown in FIG. 8, when any one of the blank signals is at the Lo level (within the blank period), the border data is output, and in other periods, the image data in the effective display area is output. Is done. The details will be described later with the operation of the data selector.

(4) Scan line address data generator The scan line address generator 3 is provided to generate the scan line address data A0 to A15 of the display panel. The scanning line address generator 3 is provided with a horizontal synchronizing signal Hs input from a display controller of the liquid crystal display device.
This is a 12-bit binary counter using inc as a clock (selectable from 4096 scanning lines). This counter is GCPU6
, The count value (scanning line address data) can be preset at an arbitrary timing. Further, the width of the count-up (how many interlaced scans are performed) can also be set.

(4) Output unit to liquid crystal display device The image data transfer format to the ferroelectric liquid crystal display device has already been disclosed by the present applicants in Japanese Patent Application Nos. 61-212184 and 63-285141. In addition, a communication method is proposed for realizing high-resolution display on a display element having a memory property. According to these proposals, with respect to the transfer of image data, a method is adopted in which scanning line address information and image information for a scanning line requiring rewriting are serially time-divisionally transferred on the same transmission line.

The data selector 4 is provided to realize these transfer formats. The data selector 4 is
Based on the timing control signal from the GCPU 6, three types of data, that is, gradation-converted image data PD0 to PD7, border data BD0 to BD7, and scanning line address data A0 to A15, are switched in time division and sent to the display device. FIG. 9 shows an example of a transfer format from a display interface which is an image information output circuit according to the present invention in a form based on the above proposal. In FIG. 9, the horizontal blanking signal HBlank is
When the horizontal synchronizing signal Hsync is input during the period of the Lo level (within the blank period), the data selector 4 first controls the scanning line address data by the timing control from the GCPU 6.
A0 to A15 are output in two cycles (four clocks (CLK)). Next, until the HBlank becomes Hi level, the border data BD0 to 7 from the border register 2 are transferred to the communication lines PIX0 to PIX0.
Keep on 7. When HBlank becomes Hi level (the blank period ends), the image data PD0 to PD7 in the gradation-converted effective display area are placed on the communication lines PIX0 to PIX7. In FIG. 9,
When information of 1280 pixels (640 pixels) is transferred as image data in the effective display area, the GCPU 6 sets HBlank to the Lo level again. When HBlank goes to the Lo level, the data selector 14 again switches the border data BD0 to BD7 to the communication line PIX0.
And transfer of data for all picture elements (1280 picture elements) is completed.

Although FIG. 9 shows the transfer timing in the horizontal scanning direction, the data selector 4 similarly distinguishes the border area from the effective display area using the vertical blanking signal in the vertical scanning direction, and outputs the output data. Is switching.

Further, by controlling the timing of HBlank and VBlank, the effective display area can be displayed at an arbitrary position on the screen.

As described above, in a display device using a ferroelectric liquid crystal having bistability (memory property), a first multiplexer for guiding image data read from an image memory to the next stage for each pixel. A pallet RAM for outputting ON / OFF data of a predetermined pixel based on the data output from the first multiplexer, and a second RAM for converting the data from the pallet RAM into an output format for transferring the data to the display device. An image information output circuit having a multiplexer is provided, which performs image data conversion processing and processing outside the effective display area (frame section) in response to a display mode request from the main body CPU, so that it can be used in a conventional CRT or the like. It is possible to display the screens in the various display modes obtained on a display device using a binarized display element such as a ferroelectric liquid crystal display without failure.

[Effects of the Invention] As described above, according to the present invention, a conventional CRT
It is possible to display a screen in various display modes used in a display device with a size optimal for the display device even on a display device having a high resolution different from the resolution of the screen.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an image information output circuit according to the present invention. FIG. 2 is an overall configuration diagram of a graphics controller including an image information output circuit according to the present invention and a ferroelectric liquid crystal display panel unit. FIG. 3 is a diagram showing a data conversion format of the pixel multiplexer 11. FIG. 4 is a diagram showing a relationship between gradation data of a palette register in a palette RAM and actual pixel arrangement on a display panel. FIG. 5 is a diagram showing a relationship between image data from a VRAM and an address of a palette register. FIG. 6 is a diagram showing a data conversion format of the pixel selector 14. FIG. 7 is a diagram showing an example of the configuration of a border register, border data, and a display pattern. FIG. 8 is a diagram showing a relationship between a position of a border portion on a display screen and horizontal and vertical blanking signals. FIG. 9 is a diagram showing an example of a transfer format from an image information output circuit according to the present invention. FIG. 10 is a diagram showing a display mode on an IBM personal computer. 1: gradation converter 11: multiplexer 12: pallet RAM 13: pallet RAM 14: multiplexer

Claims (7)

(57) [Claims] 1. A display device capable of displaying image data of a plurality of display modes having different numbers of picture elements, display colors, etc. on a display panel, the number of bits corresponding to a selected display mode being displayed on the display panel. Storage means for storing image data that constitutes one picture element in the following; reading means for reading image data stored in the storage means; the number of picture elements in the selected display mode and the number of picture elements in the display panel Scaling means for scaling data of one picture element constituting image data read from the storage means to n × n picture element data by a magnification n (n is a positive number) determined based on Display control means for displaying the scaled image data on the display panel. 2. The image processing apparatus according to claim 1, wherein the image data is multi-valued data, and the image data read by the reading means is further converted into binary data. When binarizing by means,
The display device according to claim 1, wherein the data is scaled. 3. The method according to claim 1, wherein n is the number of vertical and horizontal picture elements of the display panel.
2. The display device according to claim 1, wherein the display mode is determined based on the number of vertical and horizontal picture elements of the selected display mode. 4. The display device according to claim 1, wherein said display panel is made of a ferroelectric liquid crystal. 5. The display device according to claim 1, wherein one picture element of said display panel comprises pixels of two different sizes. 6. A display method capable of displaying image data of a plurality of display modes having different numbers of picture elements, display colors, and the like on a display panel, wherein bits corresponding to the selected display mode are displayed on the display panel. The image data that constitutes one picture element in the number is stored in the storage means, the image data stored in the storage means is read, and the number of the picture elements of the selected display mode and the number of the picture elements of the display panel are stored. The data of one picture element constituting the image data read from the storage means is scaled to n × n picture element data by a magnification n (n is a positive number) determined based on the scaled image data. Is displayed on the display panel. 7. The method according to claim 6, wherein n is the number of picture elements in the vertical and horizontal directions of the display panel
7. The display method according to claim 6, wherein the display method is determined based on the number of vertical and horizontal picture elements of the selected display mode.