JP2864612B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2864612B2 JP2864612B2 JP1705190A JP1705190A JP2864612B2 JP 2864612 B2 JP2864612 B2 JP 2864612B2 JP 1705190 A JP1705190 A JP 1705190A JP 1705190 A JP1705190 A JP 1705190A JP 2864612 B2 JP2864612 B2 JP 2864612B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- substrate
- wiring pattern
- face
- external wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 81
- 239000000758 substrate Substances 0.000 claims description 65
- 239000011521 glass Substances 0.000 claims description 19
- 239000004973 liquid crystal related substance Substances 0.000 claims description 16
- 239000002184 metal Substances 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 13
- 238000000034 method Methods 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- -1 ITO Chemical class 0.000 description 1
- 229910010977 Ti—Pd Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Wire Bonding (AREA)
- Liquid Crystal (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、半導体装置の構造に関する。Description: TECHNICAL FIELD The present invention relates to a structure of a semiconductor device.
［従来の技術］ 従来、半導体装置の構造としては、特願平01−015511
号に示され、第２図に示されるような構造が知られてい
た。第２図は従来の半導体装置の構造を基板側から見た
図であり、１は少くとも表面が絶縁されている基板でそ
の絶縁表面上に２の装置外部との配線パターン及び３の
装置内部の配線パターンが、５の半導体素子の電極上に
形成されている金属突起４に相対するように形成されて
いる。８は絶縁樹脂であり、半導体素子５と、基板１は
この絶縁樹脂によって、配線パターンと、金属突起の電
気的接続を保ったまま、接着している。一般に半導体素
子の電極ピッチは50〜200μｍであり、外部装置との結
線を行う際は、さらにそのピッチを拡大し、第２図２に
示されるような配線パターンを形成することが多かっ
た。６は基板の端面を示し、７は基板端面と半導体素子
の距離を示す。従来の半導体装置の構造を液晶パネルに
応用した例を第３図に示す。11は基板ガラスであり、16
の対向ガラスとの間に液晶が封入されている。11の基板
ガラス上には、第２図で説明したような方式に従って、
駆動用半導体素子15が実装されている。12は駆動用半導
体素子へ入力信号を送出するための入力配線パターンで
あり、17のフレキシブルコネクターと異方性導電膜、ハ
ンダ付け等で接続され、外部回路と接続されていた。ま
た駆動用半導体素子15からの出力は出力配線パターン13
を通して液晶封入部へ導かれ、液晶駆動のための信号を
液晶に印加していた。[Prior Art] Conventionally, the structure of a semiconductor device is disclosed in Japanese Patent Application No. 01-015511.
The structure shown in FIG. 2 and shown in FIG. 2 was known. FIG. 2 is a view of the structure of a conventional semiconductor device as viewed from the substrate side. Reference numeral 1 denotes a substrate having at least an insulated surface, and a wiring pattern with the outside of the device 2 and the inside of the device 3 on the insulating surface. Are formed so as to face the metal protrusions 4 formed on the electrodes of the fifth semiconductor element. Reference numeral 8 denotes an insulating resin, and the semiconductor element 5 and the substrate 1 are adhered to each other by the insulating resin while maintaining the electrical connection between the wiring pattern and the metal protrusion. In general, the electrode pitch of a semiconductor element is 50 to 200 μm, and when connecting to an external device, the pitch is often further increased to form a wiring pattern as shown in FIG. 6 indicates an end face of the substrate, and 7 indicates a distance between the end face of the substrate and the semiconductor element. FIG. 3 shows an example in which the structure of a conventional semiconductor device is applied to a liquid crystal panel. 11 is a substrate glass, 16
The liquid crystal is sealed between the opposite glass. On the substrate glass of No. 11, according to the method described in FIG.
The driving semiconductor element 15 is mounted. Reference numeral 12 denotes an input wiring pattern for transmitting an input signal to the driving semiconductor element. The input wiring pattern was connected to the flexible connector 17 by an anisotropic conductive film, soldering, or the like, and was connected to an external circuit. The output from the driving semiconductor element 15 is the output wiring pattern 13.
The liquid crystal was guided to the liquid crystal enclosing section, and a signal for driving the liquid crystal was applied to the liquid crystal.
［発明が解決しようとする課題］ しかし、従来の半導体装置の構造では、第３図で示さ
れるように、半導体素子の出力配線パターンすなわち装
置内部の配線パターンと半導体素子をはさんで基板端面
側に入力配線パターンすなわち装置外部との配線パター
ンを有するような構造になっているために、基板端面と
半導体素子の距離７が必然的に長くなってしまうという
問題点を有していた。一般に基板は、例えば液晶表示装
置であれば液晶表示部、イメージセンサーであれば、フ
ォトダイオード及び駆動回路等、その装置にとって必要
不可欠な部分をできる限り大きくし、実装部等はできる
限り小さくし、基板からの装置の取り効率を上げようと
するため、できるだけ基板端面と半導体素子の距離７の
ようなスペースは削除する設計が行われる。そのため、
従来の半導体装置の構造では基板からの装置の取り効率
が悪いという問題点を有していたのである。[Problems to be Solved by the Invention] However, in the structure of the conventional semiconductor device, as shown in FIG. 3, the output wiring pattern of the semiconductor element, that is, the wiring pattern inside the device and the semiconductor element are sandwiched between the semiconductor element and the end face of the substrate. In addition, since the structure has an input wiring pattern, that is, a wiring pattern to the outside of the device, the distance 7 between the substrate end face and the semiconductor element is inevitably increased. In general, the substrate is, for example, a liquid crystal display unit in the case of a liquid crystal display device, and a photodiode and a driving circuit in the case of an image sensor. In order to increase the efficiency of removing the device from the substrate, a design is made to eliminate as much space as possible, such as the distance 7 between the end face of the substrate and the semiconductor element. for that reason,
The conventional structure of the semiconductor device has a problem that the efficiency of removing the device from the substrate is low.
そこで、本発明では前述のような問題点を解決するた
めに、基板端面と半導体素子の距離７をできる限り小さ
くし、基板からの装置の取り効率をできるだけ高めるよ
うな半導体装置の構造を提供することを目的としてい
る。Therefore, in order to solve the above-mentioned problems, the present invention provides a semiconductor device structure in which the distance 7 between the substrate end face and the semiconductor element is made as small as possible, and the efficiency of removing the device from the substrate is increased as much as possible. It is intended to be.
［課題を解決するための手段］ 前記問題点を解決するため、本発明の半導体装置は、
液晶表示部を有するガラス基板と、 前記液晶表示部を除く領域の前記ガラス基板上におい
て、前記基板の所定の端面に沿って、一辺が前記端面と
平行になるようにフェースダウン実装されている第１の
半導体素子および第２の半導体素子と、 前記第１の半導体素子の入力用電極と電気的に接続さ
れて前記ガラス基板の前記端面に引き出されている複数
の外部配線パターンと、 前記第１の半導体素子の出力用電極と電気的に接続さ
れ、前記ガラス基板内部に引き出されている内部配線パ
ターンと、を有する半導体装置であって、 前記端面における前記外部配線パターンのピッチが前
記第１の半導体素子の前記入力用電極のピッチよりも広
く、前記入力用電極との接合部を除く前記外部配線パタ
ーン全体にわたり該パターン幅が該配線パターンの前記
入力用電極との接合部の幅よりも広く形成され、 前記外部配線パターンの一部は、前記端面と直交する
前記第１の半導体素子の側面方向から引き出され、か
つ、 前記側面方向から引き出された前記外部配線パターン
は、前記第１の半導体素子と前記第２の半導体素子間に
あることを特徴とする。[Means for Solving the Problems] In order to solve the above problems, a semiconductor device of the present invention comprises:
A glass substrate having a liquid crystal display portion, and a face-down mounting on the glass substrate in a region other than the liquid crystal display portion along a predetermined end surface of the substrate such that one side is parallel to the end surface. A first semiconductor element and a second semiconductor element; a plurality of external wiring patterns electrically connected to an input electrode of the first semiconductor element and drawn out to the end face of the glass substrate; And an internal wiring pattern that is electrically connected to an output electrode of the semiconductor element and is drawn into the glass substrate, wherein a pitch of the external wiring pattern on the end face is the first. The width of the wiring pattern is wider than the pitch of the input electrodes of the semiconductor element, and the pattern width is equal to the entire width of the external wiring pattern excluding a joint with the input electrodes. A part of the external wiring pattern is drawn out from a side surface direction of the first semiconductor element orthogonal to the end face, and from the side surface direction. The extracted external wiring pattern is located between the first semiconductor element and the second semiconductor element.
また、本発明の半導体装置は、前記外部配線パターン
が接続されるコネクターを含むことを特徴とする。Further, the semiconductor device of the present invention includes a connector to which the external wiring pattern is connected.
［作用］ 本発明では、フェースダウン実装されている半導体素
子から外部へ引き出される配線パターンを半導体素子の
側面から多く引き出す構造としたので、半導体素子の電
極ピッチを、外部との接続が容易に得られるように配線
パターンのピッチを拡大する部分が半導体素子と基板端
部の間ではなく、半導体素子の側方を用いることができ
るため、半導体素子と基板端部の距離が短くなるという
作用を有する。[Operation] In the present invention, since the wiring pattern led out from the semiconductor element mounted face-down to the outside is largely pulled out from the side surface of the semiconductor element, the electrode pitch of the semiconductor element can be easily obtained. Since the portion where the pitch of the wiring pattern is increased can be used not between the semiconductor element and the end of the substrate but on the side of the semiconductor element, the distance between the semiconductor element and the end of the substrate is shortened. .
［実施例］ 以下に、本発明を実施例に基づき、詳細に説明する。Examples Hereinafter, the present invention will be described in detail based on examples.
第１図は、本発明による半導体装置の構造を基板側か
ら見た図である。１は基板であり、少なくとも表面が絶
縁された、金属、ガラス、セラミックス等が用いられる
ことが多い。第１図では、ガラス等の透明基板を用いた
例で説明する。基板上には、半導体素子５を基板外部と
接続するための装置外部との配線パターン２と、基板上
に形成された回路との接続を行うための装置内部の配線
パターン３とが形成されている。これらの配線パターン
は、通常、Cr,Ni,Ta等の金属やITO等の金属酸化物をフ
ォトパターニングして形成するか、導電インクを印刷し
て形成することが多い。装置内部の配線パターン３のピ
ッチは、基板１上に形成される回路のピッチが、半導体
素子５上に形成されている金属突起４のピッチと同程度
か、それ以下であるため、パターン設計上素直に引きま
わせば良いため問題無いが、装置外部との接続は、通
常、金属突起４のピッチより広くなければ、接続しにく
く、かつ半導体素子に供給する電源等は低インピーダン
スを求められることが多いため、装置外部との配線パタ
ーン２はできる限り幅広く設計することが多い。装置外
部との配線パターン４は半導体素子５の側面方向へ引き
出されており、こうすることで、配線パターンのピッチ
の拡大および低インピーダンス化すなわちパターンの幅
広化を行っているのである。当然、半導体素子５の外部
接続用金属突起も装置外部との配線パターン２に相対す
る位置に形成されている。通常、半導体素子の側向は何
も形成されないムダなスペースであることが多いので、
ここに装置外部との接続場所を形成することになる。こ
うすることによって、６の基板端面と、半導体素子５と
の距離７は、半導体素子５の基板端面６側に装置外部と
の接続場所を設ける方式に比較して、基板端面と半導体
素子の距離７を充分に短くすることができるのである。
第１図では、４本の装置外部との配線パターンを示した
が、その数はもちろん半導体素子、半導体装置によって
も異なるし、パターンの引き出しも、図のように半導体
素子の側面方向を中心に行えばよく、四角、及び一部は
半導体素子と基板端面とを結ぶ領域に存在してもかまわ
ない。要は、いかに、半導体素子側面のムダなスペース
を装置外部との接続パターンの引きまわしに用いれるか
を考えた設計を行えば良いのである。このように、半導
体素子と基板端面との距離を短くしたことで、基板寸法
を小さくでき、基板の原板からの取り効率が向上するの
で、基板のコストを低下させることができる。これは、
基板の面積当たりのコストが高いアクティブマトリクス
液晶パネル基板、イメージセンサー用基板等において著
しい効果がある。FIG. 1 is a view of a structure of a semiconductor device according to the present invention as viewed from a substrate side. Reference numeral 1 denotes a substrate, which is often made of metal, glass, ceramics, or the like, at least having an insulated surface. FIG. 1 illustrates an example using a transparent substrate such as glass. A wiring pattern 2 for connecting the semiconductor element 5 to the outside of the substrate and a wiring pattern 3 for connecting the circuit formed on the substrate to the outside of the device are formed on the substrate. I have. These wiring patterns are usually formed by photo-patterning a metal such as Cr, Ni, Ta or a metal oxide such as ITO, or by printing a conductive ink in many cases. The pitch of the wiring pattern 3 inside the device is equal to or less than the pitch of the metal protrusions 4 formed on the semiconductor element 5 because the pitch of the circuit formed on the substrate 1 is less than or equal to the pitch. There is no problem since it can be pulled straight, but connection with the outside of the device is usually difficult unless it is wider than the pitch of the metal protrusions 4, and a low impedance is required for the power supply and the like supplied to the semiconductor element. Therefore, the wiring pattern 2 to the outside of the device is often designed as wide as possible. The wiring pattern 4 to the outside of the device is drawn out toward the side surface of the semiconductor element 5, and thereby, the pitch of the wiring pattern is increased and the impedance is reduced, that is, the pattern is widened. Naturally, the external connection metal projection of the semiconductor element 5 is also formed at a position facing the wiring pattern 2 to the outside of the device. Usually, the side of the semiconductor element is often a wasteful space where nothing is formed,
Here, a connection place with the outside of the device is formed. By doing so, the distance 7 between the substrate end face 6 and the semiconductor element 5 is smaller than the distance between the substrate end face and the semiconductor element as compared with the method in which a connection place with the outside of the device is provided on the substrate end face 6 side of the semiconductor element 5. 7 can be made sufficiently short.
In FIG. 1, four wiring patterns with the outside of the device are shown. This may be performed, and the square and a part thereof may be present in a region connecting the semiconductor element and the end face of the substrate. The point is that the design should be made in consideration of how the wasteful space on the side surface of the semiconductor element is used to route the connection pattern to the outside of the device. As described above, by reducing the distance between the semiconductor element and the end face of the substrate, the dimensions of the substrate can be reduced, and the efficiency of removing the substrate from the original plate can be improved, so that the cost of the substrate can be reduced. this is,
It has a remarkable effect in an active matrix liquid crystal panel substrate, an image sensor substrate, and the like, which have a high cost per substrate area.
さらに、基板性能に関係のない部分が小さくでき、基
板を用いた製品の商品価値を高めることができる。液晶
パネル等では、額縁と呼ばれる部位に相当し、ここを小
さくできるので商品価値が高まる。Further, a portion irrelevant to the substrate performance can be reduced, and the commercial value of a product using the substrate can be increased. In a liquid crystal panel or the like, it corresponds to a part called a picture frame, which can be made smaller, thereby increasing its commercial value.
半導体素子５は、８の絶縁樹脂によって基板１と接着
しているのであるが、さらにこの様子をわかりやすくす
るために、第１図のＡ−Ａ′断面図を第４図に示す。第
４図中で、５は半導体素子を示し、その電極９上に、例
えばCr−Cu,Ti−Pd等の金属を被着した後、金属突起４
を形成する。金属突起４は、Au,Cu,ハンダ等の金属であ
り、電気メッキ，スパッタ等で形成されることが多い。
電極９は、半導体素子に供給する電源、入力信号、ある
いは出力信号を半導体素子外部へ取り出す接続部であ
る。４の金属突起が、基板１上の装置外部との配線パタ
ーン２及び装置内部の配線パターン３に、絶縁樹脂８の
接着力で押しつけられている。ここでは、接着剤による
半導体素子のフリップチップ実装についての例で説明し
たが、従来から行われているハンダバンプによる共晶接
続法や、金属突起の代替物質を印刷等で形成する方法で
もかまわない。The semiconductor element 5 is adhered to the substrate 1 by the insulating resin of FIG. 8, and in order to make it easier to understand, a cross-sectional view taken along the line AA ′ of FIG. 1 is shown in FIG. In FIG. 4, reference numeral 5 denotes a semiconductor element. After a metal such as Cr—Cu or Ti—Pd is applied
To form The metal projection 4 is a metal such as Au, Cu, or solder, and is often formed by electroplating, sputtering, or the like.
The electrode 9 is a connection part for extracting a power supply, an input signal, or an output signal supplied to the semiconductor element to the outside of the semiconductor element. The metal projection 4 is pressed against the wiring pattern 2 on the substrate 1 with the outside of the device and the wiring pattern 3 inside the device by the adhesive force of the insulating resin 8. Here, an example of flip-chip mounting of a semiconductor element using an adhesive has been described, but a conventional eutectic connection method using solder bumps or a method of forming a substitute material for metal projections by printing or the like may be used.
さらに、本発明の半導体装置の構造を液晶パネルに応
用した例を第５図に示す。11は基板ガラスであり、前述
の基板に相等し、16の対向ガラスとの間に液晶が封入さ
れている。11の基板ガラス上には第１図で説明したよう
な方式に従ってパネルの駆動用半導体素子15が実装され
ている。12は駆動用半導体素子へ入力信号を送出するた
めの入力配線パターンであり、13は駆動用半導体素子か
らの出力をパネルに出力するための出力配線パターンで
あり、それぞれ、装置外部との配線パターン２及び装置
内部の配線パターン３に相等する。入力配線パターンは
図示されるように、駆動用半導体素子間の空スペースで
接続ピッチを拡大し、17のフレキシブルコネクターと異
方性導電膜で実装，接続される。これは、何もフレキシ
ブルコネクターを用いなくとも、ハンダ付け，ワイヤー
ボンディング等既知の実装手段を用いても良い。FIG. 5 shows an example in which the structure of the semiconductor device of the present invention is applied to a liquid crystal panel. Reference numeral 11 denotes a substrate glass, which is equivalent to the above-described substrate, and has liquid crystal sealed between the glass and the opposite glass 16. A panel driving semiconductor element 15 is mounted on the substrate glass 11 according to the method described with reference to FIG. Reference numeral 12 denotes an input wiring pattern for sending an input signal to the driving semiconductor element, and reference numeral 13 denotes an output wiring pattern for outputting an output from the driving semiconductor element to the panel. 2 and the wiring pattern 3 inside the device. As shown in the figure, the connection pitch of the input wiring pattern is increased by an empty space between the driving semiconductor elements, and the input wiring pattern is mounted and connected to 17 flexible connectors and an anisotropic conductive film. For this, known mounting means such as soldering and wire bonding may be used without using any flexible connector.
［発明の効果］ 以上説明したように、本発明の半導体装置の構造で
は、半導体素子がフェースダウン実装されている基板上
で半導体素子の基板端面側の側面側から多くの装置外部
との配線パターンを引き出し、そこで、装置外部との接
続をとるようにしたので以下の効果を有する。[Effects of the Invention] As described above, in the structure of the semiconductor device of the present invention, many wiring patterns are formed on the substrate on which the semiconductor element is mounted face-down from the side face on the substrate end face side to the outside of the device. Is brought out, and the connection with the outside of the apparatus is taken. Therefore, the following effects are obtained.
（１） 半導体素子と基板端面との距離を小さくするこ
とができるため、基板寸法を小さくでき、基板の原板か
らの取り効率が向上するので、基板のコストを低下させ
ることができる。(1) Since the distance between the semiconductor element and the end face of the substrate can be reduced, the dimensions of the substrate can be reduced, and the efficiency of removing the substrate from the original plate can be improved, so that the cost of the substrate can be reduced.
（２）基板寸法が小さくなるにともなって、基板性能に
関係のない部分が小さくなるので、基板を用いた製品の
商品価値を高めることができる。(2) As the size of the substrate becomes smaller, a portion irrelevant to the performance of the substrate becomes smaller, so that the commercial value of a product using the substrate can be increased.
（３）基板寸法が小さくなるため、製品の重量を減らす
ことができる。(3) Since the board size is reduced, the weight of the product can be reduced.
第１図は、本発明による半導体装置の構造を、基板裏面
より見た平面図であり、第２図は、従来の半導体装置の
構造を基板裏面より見た平面図である。第３図は従来の
半導体装置の構造を示す斜視図であり、第４図は本発明
による半導体装置の構造を示す断面図である。第５図は
本発明による半導体装置の構造を示す斜視図である。 １……基板 ２……装置外部との配線パターン ３……装置内部の配線パターン ４……金属突起 ５……半導体素子 ６……基板端面 ７……基板端面と半導体素子の距離 ８……絶縁樹脂 ９……電極 11……基板ガラス 12……入力配線パターン 13……出力配線パターン 15……駆動用半導体素子 16……対向ガラス 17……フレキシブルコネクターFIG. 1 is a plan view of a structure of a semiconductor device according to the present invention as viewed from the back surface of a substrate, and FIG. 2 is a plan view of a structure of a conventional semiconductor device as viewed from the back surface of the substrate. FIG. 3 is a perspective view showing the structure of a conventional semiconductor device, and FIG. 4 is a sectional view showing the structure of the semiconductor device according to the present invention. FIG. 5 is a perspective view showing the structure of the semiconductor device according to the present invention. DESCRIPTION OF SYMBOLS 1 ... Board | substrate 2 ... Wiring pattern with the exterior of an apparatus 3 ... Wiring pattern inside an apparatus 4 ... Metal projection 5 ... Semiconductor element 6 ... Board end face 7 ... Distance between a board end face and a semiconductor element 8 ... Insulation Resin 9 Electrode 11 Substrate glass 12 Input wiring pattern 13 Output wiring pattern 15 Driving semiconductor element 16 Counter glass 17 Flexible connector
Claims (2)
て、前記基板の所定の端面に沿って、一辺が前記端面と
平行になるようにフェースダウン実装されている第１の
半導体素子および第２の半導体素子と、 前記第１の半導体素子の入力用電極と電気的に接続され
て前記ガラス基板の前記端面に引き出されている複数の
外部配線パターンと、 前記第１の半導体素子の出力用電極と電気的に接続さ
れ、前記ガラス基板内部に引き出されている内部配線パ
ターンと、を有する半導体装置であって、 前記端面における前記外部配線パターンのピッチが前記
第１の半導体素子の前記入力用電極のピッチよりも広
く、前記入力用電極との接合部を除く前記外部配線パタ
ーン全体にわたり該パターン幅が該配線パターンの前記
入力用電極との接合部の幅よりも広く形成され、 前記外部配線パターンの一部は、前記端面と直交する前
記第１の半導体素子の側面方向から引き出され、かつ、 前記側面方向から引き出された前記外部配線パターン
は、前記第１の半導体素子と前記第２の半導体素子間に
あることを特徴とする半導体装置。1. A glass substrate having a liquid crystal display section, and a face down on a glass substrate in a region excluding the liquid crystal display section along a predetermined end face of the substrate such that one side is parallel to the end face. A first semiconductor element and a second semiconductor element mounted thereon, and a plurality of external wiring patterns electrically connected to an input electrode of the first semiconductor element and drawn out to the end face of the glass substrate. And an internal wiring pattern electrically connected to the output electrode of the first semiconductor element and drawn out into the glass substrate, wherein a pitch of the external wiring pattern on the end face is provided. Is wider than the pitch of the input electrodes of the first semiconductor element, and the pattern width is equal to the entire external wiring pattern excluding a joint with the input electrodes. A part of the external wiring pattern is drawn out from a side surface direction of the first semiconductor element orthogonal to the end surface, and the side surface is formed so as to be wider than a width of a joint part of the wiring pattern with the input electrode. The semiconductor device according to claim 1, wherein the external wiring pattern drawn from a direction is between the first semiconductor element and the second semiconductor element.
ターを含むことを特徴とする請求項１記載の半導体装
置。2. The semiconductor device according to claim 1, further comprising a connector to which said external wiring pattern is connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1705190A JP2864612B2 (en) | 1990-01-26 | 1990-01-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1705190A JP2864612B2 (en) | 1990-01-26 | 1990-01-26 | Semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25310698A Division JP3058151B2 (en) | 1998-09-07 | 1998-09-07 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03222348A JPH03222348A (en) | 1991-10-01 |
| JP2864612B2 true JP2864612B2 (en) | 1999-03-03 |
Family
ID=11933197
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1705190A Expired - Lifetime JP2864612B2 (en) | 1990-01-26 | 1990-01-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2864612B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100433305C (en) * | 1996-09-12 | 2008-11-12 | 揖斐电株式会社 | Circuit-component carrying substrate |
| KR100327887B1 (en) * | 1996-09-12 | 2002-10-19 | 이비덴 가부시키가이샤 | Electronic Circuit Component Mounting Board |
| JP2004079693A (en) * | 2002-08-14 | 2004-03-11 | Sony Corp | Semiconductor device and its manufacturing method |
| JP4004994B2 (en) | 2003-06-05 | 2007-11-07 | 株式会社アドバンスト・ディスプレイ | Display device |
| JP4198736B2 (en) * | 2007-07-26 | 2008-12-17 | 三菱電機株式会社 | Source line driving circuit and display device including the source line driving circuit |
| JP6533139B2 (en) * | 2015-09-25 | 2019-06-19 | トッパン・フォームズ株式会社 | Method of manufacturing electronic component mounting body |
-
1990
- 1990-01-26 JP JP1705190A patent/JP2864612B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03222348A (en) | 1991-10-01 |
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