JP2861556B2 - Decoding circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a decode circuit for a CMOS integrated circuit.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing a conventional decoding circuit having four input lines and four output lines.

[0003] A conventional decoding circuit uses input signals (A ₀ to A ₀ ).
A ₃₎ through an input buffer (B ₀ ~B ₃₎ to drive the input lines (a ₀ ~a _3), the control signal CL buffers Q ₀
It drives the charge control line q ₀ through, power (V ₀ ~V
The respective drains of the P-type MOS transistor to a ₃₎ a charge control line q ₀ as the source and the respective gate inputs (P ₀ to P ₃₎ connected to the output line (d ₀ ~d _3), G
An N-type MOS transistor (N) having ND (G _{0 to} G ₁ ) as a source and a charge control line q ₀ as a gate input.
_{0 to} N ₁ ) to signal lines (g ₀ to
Connect to g _1), the input lines a ₀ to a gate input of the N-type MOS transistors T _0, the signal line g ₀ in the source, and connect the output line d ₀ to the drain, the gate input of the N-type MOS transistors T ₁ The input line a _{3 is connected} to the source, the signal line g ₀ is connected to the source, the output line d ₀ is connected to the drain, the input line a ₁ is connected to the gate input of the N-type MOS transistor T ₂ , and the signal line g ₀ is connected to the source.
And an output line d ₁ connected to the drain, an input line a ₂ to the gate input of the N-type MOS transistor T ₃ , a signal line g ₁ to the source, and an output line d ₂ to the drain,
The input line a ₁ to the gate input of the transistor T _4, the signal line g ₁ to the source, and connect the output line d ₃ to the drain, respectively output buffer output line _{(d 0 ~d 3) (R} 0 ~
R ₃ ) and output as output signals (D _{0 to} D ₃ ).

When the control signal CL is at a "low" level, N
Type MOS transistors (N _{0 to} N ₁ ) are turned off,
The P-type MOS transistors (P _{0 to} P ₃ ) become conductive, charge the output lines (d _{0 to} d ₃ ) to a “high” level, and when the control signal CL goes to a “high” level, an N-type MOS transistor
The transistors (N _{0 to} N ₁ ) are turned on and the P-type MOS
The transistors (P _{0 to} P ₃ ) are turned off, the sources of the N-type MOS transistors (T _{0 to} T ₄ ) go to “low” level, and the input lines (a _{0 to} a ₃ ) go to “high”. N in which an input line in a level state is used as a gate input
Type MOS transistor only becomes conductive, discharges the "low" level output line, a signal output line shapes the waveform via a buffer (R ₀ ~R ₃₎ an input signal (A ₀ ~A ₃₎ The output corresponding to the level is output to the output signal (D
_{0 to} D ₃ ).

[0005]

In the conventional decoding circuit described above, when the number of input lines and output lines and the like increase and the circuit scale becomes large and complicated, the load capacity of each signal line becomes large and a predetermined value is obtained. In order to ensure the operation speed of the above, the driving capability of each buffer must be increased in order to drive a signal line having a large load capacity, and there is a problem that a circuit area is extremely increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is therefore an object of the present invention to provide a novel decoding circuit capable of solving the above-mentioned problems inherent in the prior art. It is in.

[0007]

In order to achieve the above object, a decoding circuit according to the present invention comprises a plurality of input signal lines and a plurality of output signals outputting predetermined signals corresponding to the plurality of input signal lines. A control signal for controlling the line, the input signal line, and the output signal line, a circuit for charging all of the output signal lines to the second level when the control signal is at the first level, In this case, a circuit for discharging the signal line to the first level, an input signal line as a gate input so as to obtain a predetermined output corresponding to the input signal line, and a signal line to be discharged connected to the source and an output signal line And a plurality of MOS transistors having a drain connected to the drain and a second level when the control signal line is at the first level, and a first level when the control signal line is at the second level.
, And a circuit having a predetermined capacitance between the auxiliary signal line and the output signal line.

[0008]

Next, preferred embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment according to the present invention. The present invention has four input lines and four output lines.
This is a decoding circuit for the book.

Referring to FIG. 1, in a first embodiment of the present invention, input signals (A _{0 to} A ₃ ) are input to an input buffer (B _0).
.About.B ₃₎ via an input line (a ₀ ~a ₃₎ drives the control signal CL via the buffer Q ₀ drives the switch catcher over di control line q _0, the power (V ₀ ~V ₃₎ As the source, and the charge control line q
₀ is used as a gate input, and each drain of a P-type MOS transistor (P _{0 to} P ₃ ) is connected to an output line (d ₀ to
d ₃ ) and an N-type MO having GND (G _{0 to} G ₁ ) as a source and a charge control line q ₀ as a gate input.
The drains of the S transistors (N _{0 to} N ₁ ) are connected to the signal lines (g _{0 to} g ₁ ), and the N-type MOS transistors T
₀ , the input line a ₀ to the gate input, the signal line g ₀ to the source,
Connect the output line d ₀ to the drain, N-type MOS transistor the input line a ₃ to gate inputs of T _1, the signal line g ₀ source
, An output line d ₀ connected to the drain, an input line a ₁ to the gate input of the N-type MOS transistor T ₂ , a signal line g ₀ to the source, an output line d ₁ to the drain, and an N-type MOS transistor the input line a ₂ in the gate input of T _3, the signal line g ₁ to the source, and connect the output line d ₂ to the drain, the input line a ₁ to a gate input of the N-type MOS transistors T _4, the signal line to the source the g _1, connects the output line d ₃ to the drain, the control signal C
The L through the inverter gate (I ₀ ~I ₂₎ drives the auxiliary signal line (i ₀ ~i _2), the auxiliary signal line (i ₀ ~i ₂₎ and the output line (d ₀ ~d ₃₎ performs capacitance (C ₀ ~C ₁₁₎ the auxiliary signal line designed to put between the output line (d ₀ ~d ₃₎ buffer, respectively (R ₀ ~R ₃₎ shaping via an output signal (D _{0 to} D ₃ ).

When the control signal CL is at the “low” level, the N-type MOS transistors (N ₀ to N ₁ ) are turned off,
The P-type MOS transistors (P _{0 to} P ₃ ) are turned on, and the output lines (d _{0 to} d ₃ ) are charged to “high” level, but the auxiliary signal lines (i _{0 to} i ₂ ) are also “high”. It becomes level auxiliary signal line (i ₀ ~i ₂₎ and the output line (d ₀ ~d ₃₎ capacitance between the (C ₀ ~C ₁₁₎ by an output line (d ₀ ~d ₃₎ in a shorter period of time ""can be charged to level, the control signal CL is" high to high "level when N-type MOS transistor (N ₀ ~ N ₁₎ the conductive state, P-type MOS transistor (P ₀ ~P ₃₎ is non-conductive become a state, the signal line (g ₀ ~
g ₁ ) is discharged to the “low” level and the N-type MO is discharged.
The source side of the S transistor (T _{0 to} T ₄ ) is at the “low” level, and only the N-type MOS transistor whose gate input is the input line that is at the “high” level among the input lines (a _{0 to} a ₃ ) is conductive. ready to discharge the "low" level output wire, the auxiliary signal line (i ₀ ~i ₂₎ also "low" level auxiliary signal line (i ₀ ~i ₂₎ and the output line (d ₀ ~ d ₃ ), the output line (d ₀ -d ₃ ) can be discharged to the “low” level in a shorter time by the capacitance (C ₀ -C ₁₁ ), and the N-type MOS transistor (T
_{0 to} T ₄ ), the output line to which none of the conductive ones is connected is connected to the capacitor (C) so as not to be at the “low” level.
_{If 0 to} C ₁₁ ) are designed, the first embodiment of the decoding circuit according to the present invention can operate in a shorter time.

FIG. 2 is a circuit diagram showing a second embodiment according to the present invention. The present invention has four input lines and four output lines.
This is a decoding circuit for the book.

Referring to FIG. 2, according to a second embodiment of the present invention, input signals (A _{0 to} A ₃ ) are supplied to a NAND gate (H).
_{0 to} H ₃ ), and the control signal CL is input as the other input, and the input lines (a _{0 to} a ₃ ) are driven by the NAND gates (H _{0 to} H ₃ ). drives the charge control line q ₁ through the buffer Q _1, power (V ₀ ~
V ₃ ), the drains of P-type MOS transistors (P _{0 to} P ₃ ) each having a gate as a charge control line q ₁ are connected to output lines (d _{0 to} d ₃ ). drives the charge control line q ₀ through buffer _{Q 0, GND (G 0 ~G} 3) each N-type MOS transistor to each gate input charge control line q ₀ and the source (N ₀ to N ₃₎ the To the signal line (s ₀ to
s ₃ ), the input line a ₀ is connected to the gate input of the N- type MOS transistor T ₀ , the signal line s ₀ is connected to the source, the signal line s ₄ is connected to the drain, and the gate input of the N-type MOS transistor T ₁ is connected. Is connected to the input line a ₃ , the signal line s ₄ to the source, the output line d ₀ to the drain, the input line a ₁ to the gate input of the N-type MOS transistor T ₂ , the signal line s ₁ to the source, and the drain connect the output line d ₁ to the input line a ₂ in the gate input of the N-type MOS transistor T _3, the signal line s ₂ to the source, and connect the output line d ₂ to the drain, the N-type MOS transistor T ₄ the input line a ₁ to a gate input, a signal line s ₃ to the source, and connect the output line d ₃ to the drain, a control signal CL via the inverter gate (I ₀ ~I ₁₎ the auxiliary signal line (i ₀ ~ i ₁₎ the driven auxiliary signal line and the (i ₀ ~i ₁₎ and the output line (d ₀ ~d ₃₎ Performs auxiliary signal lines designed to add a capacitance (C ₀ ~C ₇₎ between the output buffer output line _{(d 0 ~d 3) (R} 0
To R ₃ ) and output as output signals (D _{0 to} D ₃ ).

[0014] When the control signal CL is "low" level, N-type MOS transistor (n ₀ ~N ₃₎ is non-conductive, P-type MOS transistor (P ₀ ~P ₃₎ becomes conductive, NAND gate the output of the (H ₀ ~H ₃₎ becomes "high" level irrespective of the level of the input signal (a ₀ ~A _3), the output line (d ₀ ~d _3), the signal line (s ₀ ~s ₄₎ To the “high” level, but the auxiliary signal lines (i ₀ to
i ₀ ) also has the auxiliary signal lines (i ₀ to
i ₁ ) and the capacitance between the output lines (d _{0 to} d ₃ ) (C ₀ to
Output line by _{C 7) (d 0 ~d 3} ), signal lines (s ₀ ~s
₄ ) can be charged to the “high” level in a shorter time, and when the control signal CL goes to the “high” level, the N-type MOS transistors (N _{0 to} N ₃ ) are turned on and the P-type MOS transistors (P _{0 to} P ₃ ) are turned off, and the signal lines (s _{0 to} s ₃ ) are discharged to a “low” level, and all the N-type MOs connected to a certain output line are discharged.
If the input line is "high" level state of the S transistor will be discharged to "low" level the output line, the auxiliary signal line (i ₀ through i ₁₎ also becomes "low" level, the auxiliary signal line ( i _{0 to} i ₁ ) and output lines (d _{0 to} d ₃ )
Capacitance between the (C ₀ ~C ₇₎ by an output line (d ₀ ~d ₃₎
Can be discharged to the “low” level in a shorter time, and the output line to which at least one of the N-type MOS transistors (T _{0 to} T ₄ ) is not connected is at the “low” level. The capacity (C _0-
If designing a C _7), the decoding circuit according to the present invention can operate in a shorter time than the second embodiment.

[0015]

As described above, according to the present invention,
Even if the number of input signal lines and output signal lines increases and the circuit scale becomes large and complicated, there is no need to make the driving buffer so large, and the effect that a decoding circuit with a high operating speed can be designed can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment according to the present invention.

FIG. 2 is a circuit diagram showing a second embodiment according to the present invention.

FIG. 3 is a circuit diagram showing an example of a conventional decoding circuit.

[Explanation of symbols]

A ₀ to A ₃ ... input signal a ₀ ~a ₃ ... input lines B ₀ ~B ₃ ... input buffer C ₀ -C ₁₁ ... capacitance CL ... control signal D ₀ to D ₃ ... output signal d ₀ to d ₃ ... Output line _{G 0 ~G 3 ... GND g 0} ~g 1 ... signal line H ₀ ~H ₃ ... NAND gate I ₀ ~I ₂ ... inverter gate N ₀ ~N ₃ ... N-type MOS transistor P ₀ ~P ₃ ... P-type MOS transistor Q ₀ to Q ₁ ... buffer q ₀ to q ₁ ... charge control line R ₀ to R ₃ ... output buffer T ₀ ~T ₄ ... N-type MOS transistor s ₀ ~s ₄ ... signal line V ₀ ~V ₃ ... Power supply

Claims (2)

(57) [Claims] A plurality of input signal lines; a plurality of output signal lines for outputting a predetermined signal corresponding to the input signal lines; a control signal for controlling the output signal line; A circuit that charges all of the output signal lines to a second level when the level is at a level, a circuit that discharges the signal lines to a first level when the control signal is at a second level, And a plurality of MOS transistors having the input signal line as a gate input, the discharged signal line connected to a source, and the output signal line connected to a drain so that a predetermined output is obtained. An auxiliary signal line having a second level when the control signal is at a first level and a first level when the control signal is at a second level; A decoding circuit comprising a circuit having a predetermined capacitance value between an auxiliary signal line and said output signal line. 2. A plurality of input signal lines, a plurality of output signal lines for outputting a predetermined signal corresponding to the input signal lines, a control signal for controlling the input signal lines and the output signal lines, A circuit for charging all of the output signal lines to a second level when the signal is at a first level; a circuit for discharging the signal lines to a first level when the control signal is at a second level; A plurality of MOS transistors each having a source and a drain connected in series between the discharged signal line and the output signal line with the input signal line as a gate input so that a predetermined output is obtained corresponding to the signal line. Wherein the control signal is at a second level when the control signal is at a first level, and is at a first level when the control signal is at a second level. It has a co signal line, the decoding circuit characterized by including a circuit as having a predetermined capacitance value between the auxiliary signal line and the output signal line and the signal line a plurality of transistors connected in series .