JP2848617B2 - Frequency doubler - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a frequency doubler using a dual gate field effect transistor.

(Prior Art) A microwave frequency multiplier is used when a high-frequency signal having a desired output level, frequency stability noise performance, or the like cannot be obtained by direct transmission or the like. In the future, frequency multipliers will become more and more important parts due to the use of higher frequency bands in communications and the like, for example, the use of millimeter waves.

Non-linear elements used in the multiplier include a diode, a field effect transistor (FET), and the like. When using FET,
It is suitable for monolithic microwave integrated circuits (MMICs), which have high conversion gain and are expected to develop in the future.

FIG. 3 shows a conventional example of a frequency doubler using a single gate FET (SGFET). The bias circuit is omitted for simplicity. In the figure, 101 is an SGFET, 102 is a matching circuit for a fundamental frequency (fo), and 103 is a matching circuit for a frequency doubled (2fo).

The fundamental frequency signal is applied from the input terminal 104 to excite the gate of the FET. Since the FET is normally biased near the pinch-off, high frequency components of fo, 2fo, 3fo... Nfo (1) are generated at the drain (b) point of the FET due to gate non-linearity.

Only a 2fo wave is extracted from an output terminal 106 by a band-pass filter (hereinafter abbreviated as BPF) 105.

In general, the termination condition for fo as viewed from the point (b) on the BPF side is selected to be short-circuit or open in order to increase the conversion efficiency. However, the fo wave reflected on the FET side at the point (b) appears on the gate of the FET via the feedback capacitance (C _f ) of the FET and C _f . The fo wave interferes with the fundamental frequency signal applied to the gate, and it may be very difficult to match the fo on the input side. Therefore, the termination condition on the BPF side from the point (b) is usually selected to be slightly more inductive than the short or open point. This eliminates the difficulty of matching, but may cause unstable operation such as oscillation when the load of the multiplier is inductive.

(Problems to be Solved by the Invention) As described above, in the conventional SGFET multiplier, matching on the input side is difficult due to the influence of the feedback capacitance, or unstable operation such as oscillation occurs.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a frequency doubler in which matching on the input side due to FET feedback capacitance is difficult and unstable operation is eliminated.

[Configuration of the invention]

(Means for Solving the Problems) A frequency doubler according to the present invention provides a dual gate field effect transistor with a source grounded and a proper phase delay between the first gate and the drain with respect to the fundamental frequency. A high frequency connection, a fundamental frequency signal is applied to the second gate, and a band-pass filter is connected to the drain to extract a frequency doubled signal therefrom.

(Operation) In the frequency doubler of the present invention, the fo wave reflected at the drain end of the DGFET and the wave appearing at the second gate via the feedback capacitor and the fo wave incident on the first gate via the phase delay circuit are transmitted to the second gate.
If the phase difference with the wave appearing at the gate is selected to be 180 °, the effect of the feedback capacitance can be eliminated.

Further, since the frequency doubler of the present invention utilizes the multiplication function of the DGFET, there is an advantage that the conversion gain is higher than that of the SGFET doubler that extracts a high frequency generated by the non-linear operation of the FET.

(Embodiment) An embodiment of the present invention will be described below with reference to FIG. 1 and FIG.

FIG. 1 shows a circuit diagram of a frequency doubler according to the present invention. Note that, in the conventional example, portions that are the same as those described with reference to FIG. 3 are denoted by the same reference numerals in the drawings, and description thereof will be omitted.

In FIG. 1, reference numeral 11 denotes a multiplication dual gate field effect transistor (hereinafter abbreviated as DGFET), and reference numeral 12 denotes a phase delay circuit, whereby the drain and the first gate of the DGFET are connected at a high frequency.

FIG. 2 is a diagram showing static characteristics of the DGFET. In the frequency doubler of the present invention, the DGFET is in the vicinity of the pinch-off (FIG. 2A,
B) or I _DSS (drain current when drain voltage _VDS is applied by short-circuiting between source and gate with common source)
Bias to the vicinity (FIG. 2C). Here, if the fundamental frequency (fo) signal is applied to the input terminal 104, DGFET11 the drain-source current (I _DS) is switched to the rectangular wave by the signal voltage. As a result, signals of fo, 3fo, 5fo,... (2n-1) fo,... (2) appear at the drain end (a) of the DGFET 11. Here, only fo is considered for simplicity. In the frequency doubler of the present invention, the termination condition on the BPF 105 side from the point (a) is selected to be open (prevention of oscillation stop).
As a result, the fo wave reflected by the BPF is divided into a wave incident on the drain of the DGFET 11 and a wave incident on the first gate via the phase delay circuit 12. Here, the wave incident from the drain and appearing on the second gate through the feedback capacitor is the same as the first wave.
If the phase delay circuits are selected so that the phase difference between the incident wave from the gate and the wave appearing at the second gate becomes 180 °, they cancel each other out and the influence of the feedback capacitance can be eliminated, and the input can be easily matched. The wave incident from the first gate is DG
The multiplication function of the FET 11 mixes with the fundamental frequency signal applied to the second gate. As a result, DC and 2fo appear at the drain end (a) of the DGFET 11. Here, only the 2fo wave is selected from the BPF, and the frequency doubled signal can be extracted from the output terminal 106.

Generally, when a signal is input from the first gate to the DGFET 11 whose source is grounded, the DGFET has an amplification function. Therefore,
The fo wave incident on the first gate from the drain end is amplified here, and then mixed with the fundamental frequency signal applied from the second gate. That is, the frequency doubler of the present invention can be divided into a fundamental frequency signal amplifier and a frequency converter. Therefore, as compared with an SGFET multiplier that extracts a harmonic component generated by the non-linear operation of the FET, the conversion gain is increased because of the amplification function.

Generally, the conversion gain of the SGFET multiplier is about 0 dB to 4 dB, but the conversion gain of the multiplier according to the present invention can be expected to be about 5 dB to 6 dB.

〔The invention's effect〕

As described above, according to the present invention, there is a remarkable advantage that it is possible to provide a frequency doubler in which input matching can be easily performed, operation is stable, and the conversion gain is excellent.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a DGFET frequency doubler according to the present invention, FIG. 2 is a static characteristic diagram of the DGFET, and FIG.
It is an equivalent circuit diagram of a frequency doubler. 11 DGFET 12 Phase delay circuit 102, 103 Matching circuit 104 Input terminal 105 Band-pass filter

Claims (1)

(57) [Claims] 1. A dual-gate field-effect transistor in which a source is grounded and a first gate and a drain are connected at a high frequency with an appropriate phase delay with respect to a fundamental frequency.
A frequency doubler for applying a fundamental frequency signal to a second gate and connecting a band-pass filter to a drain to extract a frequency doubled signal.