JP2840695B2 - Pattern detector - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern detection device suitable for application to, for example, a servo pattern detection unit of a sector servo type magnetic disk device.

[Summary of the Invention] The present invention is a pattern detecting device in which the interval between two pulses is a predetermined value suitable for application to, for example, a servo pattern detecting unit of a magnetic disk device of a sector servo system, wherein at least three patterns are provided. By detecting each interval between successive pulses, and determining that the pattern has been detected when the sum of the intervals is within a predetermined range, missing bits or extra bits are included in the pattern to be detected. Even if the pattern exists, the pattern can be surely detected.

2. Description of the Related Art A magnetic disk used as a recording medium in a magnetic disk device such as a so-called hard disk device and a floppy disk device is divided into a plurality of tracks in a radial direction and is divided into a plurality of sectors in a circumferential direction. , A track number (track address) and a sector number can be used to specify an area to be recorded or reproduced. As a control method for positioning the recording / reproducing head in the radial direction on the magnetic disk and holding the head on the center axis of the track having a predetermined track address, a normal data is recorded on the recording surface of the magnetic disk. There is known a sector servo method for recording servo data for positioning and time division (angle division).

FIG. 4 mainly shows signals of respective parts of a servo area of a conventional sector servo type magnetic disk and data corresponding thereto. As shown in FIG. 4, a data area (sector) is shown.
A servo area in which servo data is recorded is formed between the servo areas. The servo data includes a track address used for coarse positioning and a burst pattern used for fine positioning, etc., and a header at the head of the servo area indicates that it is a servo area. Is recorded.

Generally, in order to enable self-clocking, ordinary data is subjected to various modulations so that magnetization reversal occurs even when “1” or “0” continues, and the longest magnetization reversal interval (run length) in the data area is performed. ) Is, for example, several bits. Therefore, a pattern in which the magnetization reversal interval is longer than the run length of the data area is generally used as the servo header pattern.

In the example of FIG. 4, a pattern consisting of ten consecutive “0” s sandwiched between “1” is used as the servo header (FIG. 4A), and the recording data including this servo header is NRZ
The recording current is formed by modulation in the −I method (FIG. 4B). However, more complicated modulation is performed at least in the data area. The corresponding reproduction output by the recording / reproduction head is substantially equal to the differentiation of the recording current (FIG. 4C). When the reproduction output is binarized, for example, as shown in FIG. 4D, the binarized output is obtained. The numerical value of is the fourth
It is the reproduction data of FIG. Under normal conditions, the playback data is equal to the recorded data, so the number of consecutive "0" s in the playback data can be counted and the servo header can be detected on condition that the number matches a known value of 10. it can.

[Problems to be Solved by the Invention] However, when a defect (defect) exists in the header portion of the magnetic disk, the number of consecutive “0” s in the reproduced data changes, so that the servo header There is a problem that cannot be detected. Its “0”
When the number of the reproduced data changes, for example, as shown in FIGS. 4C to 4E, "1" of the reproduced data is changed to "0" by a missing bit (erased bit) in which the reproduced output pulse MP disappears, and the "0" When the number of “0” s increases and the number of “0” s decreases when “0” of the reproduced data changes to “1” due to extra bits (additional bits) that additionally generate a pulse EP in the reproduced output There is.

In general, the inability to detect the servo header is detected by a verification operation (verify) at the time of writing the servo data. In such a case, the writing of the servo data is repeated while avoiding the defect again. It takes time to write, and the use efficiency of the magnetic disk deteriorates. Especially in a multi platter system equipped with a plurality of magnetic disks, the probability of a defect in the header part of the servo area increases,
The servo data writing is repeated many times.

In view of such a point, the present invention considers the use of two
An object of the present invention is to detect a pattern in which the interval between two pulses is a predetermined value, and to detect the pattern even if some missing bits or extra bits occur.

[Means for Solving the Problems] A pattern detection device according to the present invention is a device for detecting a pattern in which an interval between two pulses is a predetermined value, for example, as shown in FIG. 5) detecting each interval between at least three consecutive pulses,
When the sum of the intervals (detected by the circuit (6)) falls within a predetermined range, it is determined that the pattern has been detected.

According to the present invention, when a pulse is generated between the two pulses by, for example, an extra bit,
Although the sum of the respective intervals between three consecutive pulses becomes smaller than the predetermined value, it is determined that the pattern has been detected as long as the sum falls within the predetermined range. When the interval between the two pulses is widened by the missing bit, the sum of the intervals between three consecutive pulses (the interval between the first two pulses is 0) is larger than the predetermined value. It is determined that the pattern is detected as long as is within the predetermined range.

[Embodiment] An embodiment of the present invention will be described below with reference to FIGS. In this embodiment, the present invention is applied to a servo header detection circuit in a servo area of a magnetic disk drive.

FIG. 1 shows a header detection circuit according to the present embodiment. In FIG. 1, (1) denotes an input terminal, and the input terminal (1) has an output from a recording / reproducing head and a binarization circuit (not shown). The playback data DB to be supplied is supplied. The reproduced data DB is a pulse when the value is "1" and is a flat signal when the value is "0". The reproduced data DB is supplied to an input terminal of a phase locked loop (PLL) circuit (2) and a counter ( The signal is supplied to the clear terminal CL of 3), the clock terminal CK of the first latch circuit (4), and the clock terminal CK of the second latch circuit (5).

The PLL circuit (2) outputs a clock pulse CP synchronized with the pulse of the reproduction data DB. The pulse of the clock pulse CP is not interrupted even in a flat portion (a portion where the value is “0”) of the reproduction data DB. The clock pulse CP is used as the count pulse input terminal of the counter (3).
CK, the count output of the counter (3) is supplied to the data input of the latch circuit (4), and the latch output of the latch circuit (4) is supplied to the data input of the latch circuit (5).

(6) is an addition circuit, and (7) is a comparison circuit. The value of the value M obtained by adding the latch outputs of the two latch circuits (4) and (5) by the addition circuit (6) is shown. The data is supplied to a comparison circuit (7). Further, data of the lower limit value P is supplied to the comparison circuit (7) from the first limit setting circuit (8), and data of the upper limit value Q is supplied from the second limit setting circuit (9). The comparison circuit (7) becomes high level “1” when P ≦ M ≦ Q ≦ (1) holds, and the equation (1)
Is generated, the header signal J having a low level "0" when is not satisfied, and this header signal J is supplied to one input terminal of the AND circuit (10). For example, N servo headers sandwiched between two “1” s (N is, for example, 10)
In this example, the lower limit value P and the upper limit value Q in the limit setting circuits (8) and (9) are determined as follows.

P = N−1, Q = N + 2 (2) In this case, even if there are two missing bits or one extra bit as described later, the servo header can be reliably detected.

(11) shows a window signal generation circuit, and this circuit (11) generates a window signal W which becomes "1" in the vicinity of the present servo header, for example, based on the previously detected servo header. This window signal W can also be generated based on angle information output from the rotation mechanism of the magnetic disk. The window signal W is supplied to the other input terminal of the AND circuit (10), and the header detection signal HS output from the AND circuit (10) is supplied to a control circuit (not shown) via the output terminal (12). And the signal HS is used as a window signal generation circuit (11).
Feedback to As a result, a window signal W for the next servo area is generated.

To explain the servo header detection operation of this example,
It is assumed that the number of consecutive “0” s between the leading “1” and the trailing “1” in the servo header is ten. In this case, the lower limit value P is 9 and the upper limit value Q is 12 according to equation (2).

First, when there is no error in the reproduction data DB, the count value of the counter (3) is cleared at "1" at the head of the reproduction data DB, and the clock pulse at the counter (3) is obtained until the value reaches "1" at the rear end. The CP count is 10. Then, at "1" at the rear end, the count output of the counter (3) is held in the first latch circuit (4), and the held count output is supplied to the adder circuit (6). Since the latch output of the second latch circuit (5) is normally 0, the addition result M of the addition circuit (6) is 10. Therefore, since the expression (1) is satisfied, the header signal J output from the comparison circuit (7) becomes high level "1" and the window signal W is also "1". The output header detection signal HS also becomes "1", and the servo header is detected.

Next, a detection operation when one missing bit exists in the servo header will be described with reference to FIG. The case where there is one missing bit includes, for example, a case where the leading “1” of the reproduced data in the header portion in the error-free state shown in FIG. 2A changes to “0” (FIG. 2B), and There is a case where “1” one bit before the first bit changes to “0” (FIG. 2C).

In the example of FIG. 2B, the count output of the counter (3) is 11 at the rear end of "1" of the servo header and the latch circuit (4).
And is supplied to the comparison circuit (7) via the addition circuit (6). Since the expression (1) is satisfied, the header signal J of "1" is output.

Further, in the example of FIG. 2C, one bit “0” exists before the original servo header, and the counter (3) counts the output (value is “1”) of the pulse “P1” of “1” at the head of the original servo header. 1) is held in the latch circuit (4). Then, the latch output of the latch circuit (4) is held by the latch circuit (5) and the count output (value 10) of the counter (3) is held by the latch circuit (4) at the rear end pulse P2. , The addition result M of the addition circuit (6) becomes 11. Also in this case, since Expression (1) is satisfied, the header signal J output from the comparison circuit (7) becomes high level "1". Further, in this example, since the upper limit value Q supplied to the comparison circuit (7) is 12, the servo header can be reliably detected even if there are two missing bits.

The detection operation when one extra bit exists in the servo header will be described with reference to FIG. The case where there is one extra bit is, for example, the case where “0” following “1” at the beginning of the reproduced data in the header part in the error-free state shown in FIG. 3A changes to “1” (see FIG. 3A). B) and the case where “0” in the middle part changes to “1” (FIG. 3C).

In the case of FIG. 3B, "1" at the rear end of the servo header
Then, the count output (the value is 9) of the counter (3) is supplied to the adder circuit (6) via the latch circuit (4), but since the expression (1) is satisfied, the comparison circuit (7) The header signal J becomes "1".

In addition, in the case of FIG.
"0" are divided into four "0" and five "0" by three pulses Q1 to Q3. And the first pulse
The count value of the counter (3) is cleared in Q1, the count output (value is 4) of the counter (3) is held in the latch circuit (4) by the intermediate pulse Q2, and the count value of the counter (3) is Cleared. Thereafter, the latch output of the latch circuit (4) is held in the latch circuit (5) by the trailing end pulse Q3, and the count output (value is 5) of the counter (3) is held in the latch circuit (4). Is done.

That is, the first latch circuit (4) holds the count output corresponding to the interval between the pulses Q2 and Q3, and the second latch circuit (5) holds the count output corresponding to the interval between the pulses Q1 and Q2. Then, the addition circuit (6) obtains an addition result M (= 9) corresponding to the sum of the two intervals. Since the addition result M satisfies the expression (1), the header signal J output from the comparison circuit (7) becomes "1", and the servo header is reliably detected.

Although the original servo header is divided by three pulses in the example of FIG. 3C, the original servo header without error shown in FIG. 3A is also divided by three pulses R1, R2 and R3. Can be regarded as being. However, in this case, "0" is set between the first pulse R1 and the next pulse R2.
Does not exist, and the interval between the pulse R2 and the trailing pulse R3 is
Since it is 10, the addition circuit (6) adds 10 and 0 to obtain the original value of 10.

As described above, according to this example, the addition result M corresponding to the sum of the intervals of three consecutive pulses is detected, and the addition result M is determined by the lower limit value P (= 9) and the upper limit value Q (= 12). ), It is determined that the servo header has been detected. Therefore, even if there are two missing bits or one extra bit in or near the servo header, the servo header is surely detected. There is a benefit in detecting the header. In this case, by changing the lower limit value P and the upper limit value Q, the allowable number of missing bits and extra bits can be set to desired values.

Therefore, the probability of an error occurring due to the confirmation at the time of writing the servo pattern is reduced, and the probability of rewriting the servo pattern is also reduced, so that the servo pattern can be written at a high speed and the use efficiency of the magnetic disk can be increased. it can. Further, according to the present embodiment, when the probability of occurrence of an error at the time of writing a servo pattern becomes equal to or lower than a predetermined level, the write operation can be performed at a higher speed by omitting the verification operation (verify) at the time of writing. In particular, in a multi-platter system, the probability that a defect is mixed in the header section increases, so that the header detection circuit according to the present embodiment that can allow the mixing of missing bits or the like into the servo header is effective.

Further, in this example, a window signal W is separately generated so that the header detection signal HS becomes high level "1" only in the servo area.
Even if a pattern as shown in FIG. C exists, it is not erroneously recognized as a servo header. However, assuming that the number of consecutive “0” s in the servo header is n, the window signal W can be omitted if n / 2 or more “0” s do not continue in the normal data area. .

In the above embodiment, the sum of two intervals between three consecutive pulses is detected. For example, the sum of three or more intervals between four or more consecutive pulses is detected. Is also good. Specifically, the latch circuits (4) and (5)
By increasing the number of, it is possible to easily detect many intervals.

In the example of FIG. 1, two latch circuits (4) and (5)
However, the second latch circuit (5) may be omitted and the count output of the counter (3) may be directly supplied to one input section of the adder circuit (6). In this case, as the count value of the counter (3) increases, the addition circuit (5)
Also increases. Therefore, for example, the limit setting circuit (9) for setting the upper limit value Q is omitted, and when the addition result M of the adder circuit (6) reaches the lower limit value P, it is considered that the servo header has passed, and the comparison circuit ( The header signal J, which is the output of 7), can be set to a high level "1".

Note that the present invention is not limited to the above-described embodiment, and may adopt various configurations without departing from the gist of the present invention, for example, application to an optical disk device.

According to the present invention, each interval between at least three consecutive pulses is detected, and when the sum of the intervals falls within a predetermined range, it is determined that a pattern to be detected has been detected. Thus, there is an advantage that even if a missing bit or an extra bit exists during the turn to be detected, the pattern can be reliably detected.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a header detection circuit according to one embodiment of the present invention, FIG. 2 is a diagram for explaining the operation when one missing bit exists in the embodiment, and FIG. 3 is an embodiment. FIG. 4 is a timing chart showing a signal and the like of a conventional servo area for explaining the operation when one extra bit exists. (3) is a counter, (4) and (5) are latch circuits, respectively.
(6) is an addition circuit, (7) is a comparison circuit, J is a header signal, W is a window signal, and HS is a header detection signal.

Claims (1)

(57) [Claims] An apparatus for detecting a pattern in which an interval between two pulses is a predetermined value, wherein each interval between at least three consecutive pulses is detected and a sum of the intervals is within a predetermined range. A pattern detecting device for determining that the pattern has been detected.