JP2840374B2 - Display control device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for a display device, and in particular, a scanning signal line and an information signal line are sandwiched between matrix electrodes, and a scanning signal and an information signal are applied respectively. The present invention relates to a control device for displaying video information using a display device having a memory property and having a temperature dependency on driving conditions in a liquid crystal display device driven by .

[Conventional technology]

Recently, displays such as a liquid crystal display device required for a personal computer, a work station, and the like have a large screen and a high resolution year by year. When cold, the commonly used IBM
Take PC / AT personal computer as an example.
As display modes for the display, there are over ten display modes such as CGA, EGA, VGA, and 8514 / A as specifications of the image adapter, and the resolution and the number of colors that can be displayed are different.

As a product that enables many display modes to be displayed on a single display, the CRT uses NEC's MultiSync
II, MultiSync 3D, 4D, 5D, etc. Multi as an example
Table 1 shows the Video Modes (display modes) supported by Sync 4D and 5D.

On the other hand, display devices having memory properties such as ferroelectric liquid crystal display devices are based on various basic devices used in conventional display devices such as CRT, STN-LCD (super twist liquid crystal display) and PDP (plasma display). It is different from the operating principle. So far, U.S. Patent No.
No. 4,655,561 discloses a partial writing scanning method utilizing the memory property, which the present inventors have proposed,
Japanese Patent Application Laid-Open No. 63-285141 discloses a method of realizing “low frame frequency driving + partial writing scanning” for performing high-resolution display on a display device having this memory property.

However, using this ferroelectric liquid crystal display (FLC),
In order to respond to the demands for supporting the various display modes as described above, it cannot be realized by a conventional method due to a new driving principle. The user uses this ferroelectric liquid crystal display device connected to the computer to use any of the various display modes from power-on, and to change the display mode as necessary. We have to propose a control method.

Using a ferroelectric liquid crystal display as an example, supporting various display modes especially for IBM PC / AT machines,
In addition, the overall configuration for supporting the 1280 × 1024 high-definition mode and its control method are presented.

A ferroelectric liquid crystal display device, which is a typical example of a display device having a memory property, has a temperature dependency of driving conditions represented by FIG. In this example 7Hz at 10 ° C, 10Hz at 25 ° C and 4
At 0 ° C., the frame frequency is 20 Hz (1024 scanning lines, 24 V drive voltage, KMT-
When using 408). Thus, when the temperature is 10 ° C. when the power is turned on, flickering can be prevented by the previously proposed eight interlaces in the low frequency driving. However, if the ambient temperature of the display rises with the start of operation, for example, if the ambient temperature rises due to heating by turning on the backlight or forced use of an external heater, etc.
When the temperature reaches ° C, flickering can be sufficiently prevented by using four interlaces, and the only disadvantage of eight interlaces, when displaying moving picture screens, can be reduced, for example, the splitting phenomenon of the display screen in scroll display or the like. Even at the same temperature, the driving method further changes depending on the display mode. For example, in Table 1, in the display mode with 1024 scanning lines,
The FLC display, which was 10 Hz, has 480 scanning lines in the vga mode, and the frame frequency is 20 Hz or more. With normal (two) interlaces, flicker can be sufficiently prevented, and the screen division at the time of displaying a moving image can be further reduced. However, in the conventional method, there is a method of determining the display mode, but none of the methods can change the display frame frequency together with the display environment temperature.

Further, since the FLC display is an XY matrix display, the change in the number of pixels cannot be changed by a simple method of changing the beam frequency as in the display mode. X
The number of physical pixels of a -Y matrix display is uniquely determined at the time of production and cannot be changed. Therefore, it is necessary to convert the number of logical pixels required for the display mode into the number of physical pixels.

Further, when the color and the number of gradations that can be displayed on the display side do not match the input information, for example, the display side has a monochrome 8-gradation display performance and the input information side has 256 RGB each.
If a gradation is requested, the relationship between the colors of the input information and the output information and the number of gradations must be determined for each display mode.

Further, when the driving conditions of the FLC display are not satisfied, for example, when the environmental temperature does not reach the display operating temperature range, a wait request may be issued from the display side to the image information generating side to cause the image information generating side to stand by. In addition, after the reset, when it is desired to quickly return to the display mode before the reset, it is necessary to read out various control / driving parameters and sometimes image information before the reset.

Even if individual means for satisfying the above-mentioned necessary conditions are prepared, it is desirable that it can be easily changed based on a certain procedure not only at the time of power-on but also at the time of operation from the viewpoint of the user. . Otherwise, every time the display mode is changed, the power must be turned off and then turned on or reset.

In particular, when changing the display mode once set, it may not be sufficient to simply reset the display mode to a new display mode. For example, suppose that the current mode is the VGA mode, and a certain application software requests the EGA mode, so that the mode is reset to the EGA mode. When trying to return to the original display mode after the application software ends, the display cannot be restored unless the various FLC display control parameters before the change of the display mode are saved somewhere. At times, the previous image information must be expanded again. Therefore, it is necessary to read out the image data before the control of the FLC display or the drive parameters and the conversion to the image information on the FLC display by a certain programming.

In order to produce an FLC display-equipped computer that satisfies the above requirements, it is necessary to prepare in advance a ROM (referred to as a ROM BIOS) in which the requirements are programmed according to the product. This ROM BIOS actually controls the interface between the computer and the FLC display control and display, and the user can control the display mode and the like without requiring detailed knowledge for controlling and driving the FLC display.

[Problems to be solved by the invention]

However, by controlling and driving the display panel using the ROM BIOS program that controls communication,
Two problems have arisen.

One is that the HOST CPU issues a display mode request using application software.
When control is started, if external noise is superimposed on the control line or the control line is opened or short-circuited during the control, the program in the ROM BIOS cannot be continued. As a result, the program in the ROM BIOS cannot perform subsequent control, for example, transfer of image information to the display panel, while receiving the display mode conversion request from the HOST CPU. HO in this state
The ST CPU cannot update the image increase on the display panel, making it impossible to monitor the status of the CPU.
Then, since the CPU is reset to return, the information processed up to that point may be destroyed.

Second, when the above state occurs, the display panel cannot receive image information, and the same image information remains on the display panel until the display panel returns from this state. This causes long-term afterimage development called "burn-in" on the panel.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display device which solves the above-mentioned problem that the malfunction during the display panel control gives to the HOST side or the display panel side.

[Means for Solving the Problems (and Action)] According to the present invention, first, a graphic controller having a means for transmitting display mode data and a means for transmitting image data, a method for storing image data and display mode data, Receiving, according to the image data and the display mode data,
A display unit controller that controls a display device having a backlight, and a display control device that has a communication unit that executes communication between a graphic controller and a display unit controller by handshake communication. Means for interrupting the handshake communication when a communication error occurs, outputting a display mode data retransmission request from the display unit controller to the graphic controller, and resuming the interrupted handshake communication, After interruption of handshake communication,
The above problem is solved by a table control device that operates so as to shut off the power of the backlight. Second, a graphic controller having a unit for transmitting display mode data and a unit for transmitting image data, A display unit controller that receives data and display mode data and controls a display device including a drive circuit according to the image data and display mode data, and handshake communication between the graphic controller and the display unit controller A display control device having a communication means for executing, when a communication error occurs during communication of display mode data, interrupting the handshake communication, and displaying the display mode from the display unit controller to the graphic controller. Outputting a retransmission request for over data, and means for restarting the handshake communication has been interrupted, after the handshake communication interruption, by the display control unit to operate to stop the driving state of the driver circuit,
This is to solve the above problem. The second problem is solved by the display control means having means for controlling the turning off and on of the driving element power supply of the driving condition control means and the peripheral device power such as a backlight necessary for the display element after the control is interrupted. Is the solution.

〔Example〕

 Hereinafter, details will be described based on embodiments.

FIG. 1 shows a display panel 2 (1280 × 1024 pixels) which is a ferroelectric liquid crystal display device according to an embodiment of the present invention.
s), display drivers 3 and 4, a display unit controller 8 incorporating a control program of the present invention, a graphics controller 9 having a VRAM 10 as an image information standard memory, and a Host CP indicating an IBM PC / AT.
Built-in hardware configuration of U11 and Host Bus12 and whole controller monitor program of the present invention
ROM BIOS 13, backlight 13 as a back light source for display panel 2, inverter 14 for supplying power,
A driver power supply 15 for supplying power to the display drivers 3 and 4 is shown.

(1) Function of Signal Line In FIG. 1, the function of a signal line provided between the host CPU 11 and the graphics controller 9 will be described below.

Host Bus: A standard interface hardware bus specified by IBM Corporation called AT Bus for IBM PC / AT machines.

In FIG. 1, the function of each signal line provided between the FLC display unit controller 8 and the graphics controller 9 will be described below.

1) PD0 to PD7: Data bus. 8-bit bidirectional. Data transfer speed 10MHz /
8 bits.

2) CLK: Transfer clock. 20MHz.

3) AH / DL: Identification signal between drive information and video information. For driving information,
Hi level. At video information, Lo level.

4) IH / OL: I / O identification signal of data bus. As seen from the graphic controller, when PD0-7 are in input mode, Hi level. Lo level in output mode.

5) INT: An interrupt signal from the display device to the graphics controller.

6) FLG: Data output enable signal from the display device to the graphics controller. High level when output is enabled.

7) Hsync: Horizontal synchronization signal. Data reception permission signal from the display device to the graphics controller.

8) Vsync: vertical sync signal, sync signal for each display screen. 9) DRSW: a control line for controlling the power ON / OFF of the display drivers 3 and 4.

10) BLSW: Turn on the inverter power supply 14, which is the power supply source for the backlight 13.
/ OFF control line.

First, a basic operation when display control is performed normally will be described.

(2) Basic operation R from the video information generation side, that is, Host CPU
A function defined in the OM BIOS 13 is called according to a predetermined calling rule, and parameters necessary for realizing the function are sometimes passed to the graphics controller 9. ROM BIO
In the S13 foot, when called in a regular procedure, it is translated by a GCPU (Graphics Control Central Operator) 14 or works directly on the display controller 9 to realize the required function.

The following is a description of specific translating or directly acting contents and an outline of the operation.

The graphics controller 9 transfers drive information and video information to the FLC display unit using the bidirectional data buses PD0 to PD7. However, since the drive information and the video information are transferred on the same transmission path, the two types of information must be distinguished. The signal for this identification is AH / DL. When the AH / DL signal is at the Hi level, the information on the PDs 0 to 7 indicates "drive information", and when the AH / DL signal is at the Lo level, it indicates "video information".

FLC display unit controller 8 is PD0 ~ 7
The drive information is extracted from the video signal with the drive information transferred as “1”, and the processing based on the drive information is performed. on the other hand,
The video information is sent to the shift register 6 on the information electrode drive circuit side based on the transfer clock.

Further, in this embodiment, since the drive display of the FLC display and the generation of the drive information and the video information in the graphics controller 9 are performed asynchronously, it is necessary to synchronize the devices when transferring the display information. The signals that govern this synchronization are Hsync and Vsync, where Hsync is Fsync every horizontal scanning period and Vsync is Fsync every vertical scanning period during refresh.
Generated in the LC display unit controller 8,
Send it to the graphics controller 9 side. The graphics controller 9 constantly monitors these sync signals, and transfers display information (driving information + video information) when Vsync is at the Hi level and Hsync is at the Lo level. In other cases, the graphics information is transferred once. After the transfer is completed, the process waits until the next transfer permission signal comes.

Fig. 4 is from the graphics controller 9 side.
This is a basic communication timing chart when sending display information to the controller 8 of the FLC display unit 1, and its operation will be described.

Upon detecting that Hsync has become Lo level (and INT = Hi & Vsync = Hi & IH / OL = Lo must be low), the graphics controller 9 immediately sets the AH / DL signal to Hi level and starts transferring display information. The controller 8 of the FLC display unit 1 sets Hsync to Hi level during the display information transfer period. After a series of processes based on the transferred drive information is completed, the controller 8 of the FLC display 1 sets Hsync to the Lo level again and is ready to receive the next display information.

Fig. 5 shows FL on the graphics controller 9 side.
This is a basic communication timing chart when reading display information from the controller 8 side of the C display unit 1, and its operation will be described.

First, the graphics controller 9 uses the controller 8 of the FLC display unit 1 as drive information.
Is sent to the controller 8 of the display unit 1 at the timings A0 to A15 in FIG. 5 and the 1H / OL signal is set to Hi to enter the data input mode. I do. At this time, the data buses PD0 to PD7 are in a high impedance state (Z) when viewed from the graphics controller 9 side. When the controller 8 of the FLC display unit 1 recognizes the "information read request data", it confirms that the IH / OL line is at the Hi level, puts information on the data buses PD0 to PD7, and further sets the FLG signal to the Hi level. . When the graphics controller 9 detects that the FLG line has become Hi, it reads the data on the data buses PD0 to PD7 and stores it in the GCPU 14.

(3) Communication operation at the time of displaying an image At the time of displaying an image on the display, display information is sent from the graphics controller 9 to the display, which is the same as the communication at the time of FIG. At this time, the drive information is the scanning line address information, which is transferred to the display controller 8 after being placed on the positions A0 to A15 in FIG.

In more detail, the scanning line address information is extracted by the controller 8 of the FLC display unit 1 and input to the scanning line electrode driving circuit side decoder 7 in accordance with the timing of driving the designated scanning line, and the display is operated. Is selected. On the other hand, the video information is transferred to the information electrode drive circuit side shift register 6 and is shifted in units of 8 pixels by the transfer clock (CLK). When the shift register 6 completes the shift for one scanning line in the horizontal direction, the video information for 1280 pixels is transferred to the line memory 5 provided therewith and stored for one horizontal scanning period. After the writing operation to the display panel 2 is completed after a predetermined horizontal scanning period, the controller 8 of the display unit changes Hsync to the Lo level again, and receives display information of the next scanning line.

By repeating these series of communication operations, a write operation and a partial write operation on the display panel screen are performed.

(4) Operation at the time of setting the display mode-At the time of setting from the Host side-Setting and changing the display mode for the display device is basically
It is based on the request from the Host side, and basically
It conforms to the timing chart shown in the figure. This will be specifically described below.

When the graphics controller 9 receives a display mode change request from the Host CPU 11 side, the drive information portion (when the AH / DL line is at the Hi level, that is, when the display information is transferred to the controller 8 of the display unit 1; "Display mode change request data" is added to the above (A0 to A15 timings).

The controller 8 of the display unit 1 sets the Hsync line to the Lo level after recognizing the predetermined "display mode change request data".

Next, the graphics controller 9 sends the "display mode number" as drive information to the controller 8 of the display unit 1 at the timings A0 to A15 in FIG. 6, and sets the IH / OL signal to the Hi level to make the data bus. P
Switch D0 to D7 to input mode.

The controller 8 of the display unit 1 receives the “display mode number”, determines the driving conditions of the display panel according to the display mode, and determines whether the relationship between the number of physical pixels and the number of logical pixels or the color and the number of gradations. Or the relationship of one or both of them, the size of the effective display screen and the outer frame portion of the display portion in the display screen, and the relationship of one or both of the color and the number of gradations of the outer frame portion. Or
Transfer of information from the image information storage unit to the display device Determines the format and / or timing of the information, and the "display mode number" received to confirm whether communication has been performed properly is the Hi level of the IH / OL line. After confirming that the FLG signal is
Set to Hi level.

Graphic controller 9 has FLG line Hi
After confirming that the level has reached the level, the data of the “display mode pick-up” output to the data buses PD0 to PD7 is stored in the GCPU 14.

The GCPU 14 compares the received data with the “display mode number” transferred earlier, and after confirming, sets the IH / OL signal to the Lo level.

Controller 8 of display unit 1 is IH / OL
After confirming that the line is at the Lo level, the Hsync line is set to the Lo level and waits for the next display information.

Graphics controller 9 has Hsync line L
After confirming that the level has reached o, according to the result of the display mode check, if it is normal, send normal scanning line address + video information, and if abnormal, send "display mode conversion request data" again. Start over.

With the above procedure, the display mode can be changed and the display panel can be driven and controlled according to each display mode.

(5) Operation at the time of setting the display mode-at the time of setting from the display side-As an example, the graphics controller 9 and the controller 8 of the display unit 1 are each configured by separate power supplies, and the power supply of the controller 8 of the display unit 1 Graphics controller 9
When entering after the (Host side) is started, it is impossible for the controller 8 of the display unit 1 to know in what display mode the graphics controller 9 is already operating. In such a case, the controller 8 of the display unit 1 sends an INT signal to the graphics controller 9 to make a display mode setting request. Graphic
Upon receiving the INT signal from the display unit controller 8, the controller 9 sends display mode change request data to the display unit controller 8.

Thereafter, the display mode is set in the same procedure as in (4) Operation at the time of setting the display mode-at the time of setting from the Host side.

If necessary, the display device can issue a read request to the main device. In this case, the display device is the same as the display mode setting,
First, an INT signal is sent to the controller 9. Upon receiving the INT signal from the display device, the graphics controller 9 sends display mode change data to the display unit controller 8. After that, temperature information reading processing is performed in the same procedure as when a request is made from the main unit.

Next, in the above-mentioned communication procedure, during the communication control, a control for a case where an external noise enters a control line (signal line shown in (1)) for performing communication, or a case where the control line is opened or short-circuited. explain. FIG. 2 is a flowchart showing the control. The graphics controller control program in FIG. The display unit controller control program is provided by the display unit controller 8.
Is built in the storage element. The numbers of the handshake communication part in FIG. 2 correspond to the procedure numbers in the display mode setting of (4).

 The following description is an important point of the present invention.

The operation when the display mode is set in (4) will be described as an example. When the display mode is changed in response to a request from the HOST side, the graphic controller 9 sets the (4)
Communication is performed by handshake with the display controller 8 in the order of... To control the display panel. When the graphics controller 9 is in the state of, it is assumed that the graphics controller 9 determines that the confirmation result of the display mode number is correct and sends image information (scanning address number) to the display controller 8. At this time, extraneous noise enters the control line PD0-7, which causes the display unit controller 8 to immediately receive the image information (scanning address signal) as the display mode change request data. The Hsync signal is set to "L" level and the display mode number is received from the graphics controller 9 via the path A in the figure. (This display mode number is incorrect) and
Waiting for IH / OL signal to go to “H” level. On the other hand, after sending the image information, the graphics controller 9 confirms that the next Hsync signal is at the "L" level, sends the next image information, and continues around the loop B in FIG.

If the functions of TgOUT and TdOUT in FIG. 2 are not used (when the time settings of Tg and Td are made infinite), the display unit controller 8 waits until the IH / OL signal level becomes "H" level. Subsequently, no image information is written to the display panel 1. Here, if a finite time is set as Td = several 100 ms, the display unit controller 8 sets the backlight 13 to BL after Td, ie, after several 100 ms.
After turning off by SW signal, display driver 3,
4 is turned off by the DRSW signal, and the INT signal is sent to the graphics controller 9. Upon recognizing the INT signal, the graphics controller 9 restarts communication again according to the communication procedure of (4), and control returns to normal.

As another example, a case where the connection of the IH / OL signal line is opened during the communication control of (4) will be described. In this state, the display unit controller 8 keeps waiting for the IH / OL signal to go to the "H" level while the communication procedure of (4) is performed. Therefore, since the FLG signal, which is the next process, cannot be set to the "H" level, the graphics controller 9 also keeps waiting for the FLG signal to go to the "H" level.

Here, if the time Tg <Td = several 100 ms is set, the graphics controller 9 exits the handshake communication after the Tg time, and the processing shifts to the loop B, so that the INT signal of the display unit controller 8 can be accepted. State. On the other hand, the display unit controller 8 also turns off the backlight 13 of the display unit 1 in the same manner as described above after the Td time, that is, several hundred ms.
F and turn off display drivers 3 and 4 and INT
Send out a signal. Here, if the release of the IH / OL signal line returns to normal, the drive operation returns to normal. During this time, the driver power and backlight applied to the display panel 1 are kept OFF.

The time settings of Tg and Td described above are realized by software counters in each controller.
It is also possible to wait for a hardware counter outside the GCPU 4 or the display unit controller 8 and control the set value of the counter. At this time, the control line that informs that the counter value has reached the value for the set time
What is necessary is just to input to the display unit controller 8.

〔The invention's effect〕

As explained above, the pre-stored BIOS RO
The communication control program in the M13 and the program of the display unit controller 8 include means for forcibly interrupting the communication control means, means for arbitrarily changing the interruption timing, and means for performing control again. Therefore, even if data reception malfunction due to external noise or malfunction due to opening or shorting of the communication control line occurs,
Image information can be transferred normally again without the need for resetting the HOST CPU. This is the HOST CPU
HOST processing until a malfunction occurs in the reset operation of
You will not have to destroy CPU information.

In addition, since the power of the power supply backlight 13 of the display drivers 3 and 4 can be controlled to be turned off until the malfunction is improved, the "burn-in" phenomenon of the display panel can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram of the present invention, and FIG. 2 is a control flowchart of a display unit controller used in the present invention. FIG. 3 is a characteristic diagram showing temperature dependence of driving conditions (frequency) with respect to temperature in the ferroelectric liquid crystal device used in the present invention. FIGS. 4, 5, and 6 are timing charts of the communication system used in the present invention. FIG. 7 is a display mode diagram in the case of CRT display.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ identification symbol FI G09G 3/20 670 G09G 3/20 670F (58) Field surveyed (Int. Cl. ⁶ , DB name) G09G 1/00-5 / 40

Claims (3)

(57) [Claims] A graphic controller having a means for transmitting display mode data and a means for transmitting image data; a graphic controller for receiving image data and display mode data; and a backlight according to the image data and display mode data. A display control device, comprising: a display unit controller for controlling a display device; and a communication means for executing communication between a graphic controller and the display unit controller by handshake communication, wherein a communication error occurs during communication of display mode data. Means for interrupting the handshake communication, outputting a display mode data retransmission request from the display unit controller to the graphic controller, and resuming the interrupted handshake communication, After Eku communication interruption, the display control apparatus to operate so as to shut off the power of the backlight. 2. A graphic controller having a means for transmitting display mode data and a means for transmitting image data, a graphic controller for receiving image data and display mode data, and a driving circuit according to the image data and display mode data. A display control device, comprising: a display unit controller for controlling a display device; and a communication means for executing communication between a graphic controller and the display unit controller by handshake communication, wherein a communication error occurs during communication of display mode data. Means for interrupting the handshake communication, outputting a display mode data retransmission request from the display unit controller to the graphic controller, and resuming the interrupted handshake communication. After click communication interruption, the display control unit to operate to stop the driving state of the driving circuit. 3. The display control device according to claim 1, wherein the display device has a display panel including a ferroelectric liquid crystal.