JP2735072B2 - Image display control device and electronic device having the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display control device which can easily perform a moving image superimposition process called a sprite in a raster scan type display device for displaying a moving image. The present invention relates to a data selection device that selects color pattern data of a sprite having the highest priority when a plurality of sprites overlap a pixel, and controls the color pattern data to be color data for one pixel.

[0002]

2. Description of the Related Art An image display control device having a sprite function can display a plurality of sprites and a background screen. For example, the background screen is fixed, a character pattern is defined in the sprite,
By changing the display position (coordinates) of the sprite on the display screen, it is possible to easily move the character pattern on the display screen.

[0003] Sprites have a priority order.
When more than one sprite overlaps, a sprite having a higher priority is displayed, and a sprite having a lower priority is not displayed.

Conventionally, the priority order of sprites is determined as shown in FIG.
Is realized by a circuit as shown in FIG.

[0005] The priority data selection device shown in FIG. 1 uses a sprite having a width of 16 dots on one horizontal line of the screen.
Six colors can be selected, and 16 colors can be expressed by designating 4-bit data for one sprite pixel. Therefore, the pattern shift circuit 11 is provided with four shift registers 15 each having a length of 16 bits. Sixteen colors are represented by the 4-bit data 103 transmitted simultaneously from the four shift registers 15. Further, by using the 16 pattern shift circuits 11, up to 16 sprites can be selected on one horizontal line. The pattern shift circuit 11
A latch circuit 16 for storing an X coordinate of a display position of a sprite, in addition to a shift register 15 having a width of 16 bits,
A coincidence detection circuit 17 for detecting coincidence between the count number of the horizontal dot counter 19 and the X coordinate in the latch circuit 16
And the shift register 105 receives the detection signal 104 output from the coincidence detection circuit
And a clock control circuit 18 for controlling the transmission of the clock signal.

The priority data selection device shown in FIG.
16 pattern shift circuits 11 called P16
And data 1 output from each pattern shift circuit 11
03 is a priority pattern selection circuit that selects the data with the highest priority.

A method for selecting a sprite will be briefly described with reference to FIG. Sprite data to be displayed in the next horizontal display period during the horizontal flyback period of the display device is taken in parallel to the shift register 15 in the pattern shift circuit 11 by the 16 pattern input signal lines 100. The shift register 15 takes in each data by the read clock signal 102 applied in order from the top in FIG. When the pattern data is taken into the top shift register 15 of the pattern shift circuit, an operation of taking in the display coordinates (X coordinate) of the sprite into the latch circuit 16 through the input line 101 is also performed. Next, in the horizontal display period, the horizontal dot counter 19 starts counting operation, and the coincidence detection circuit 17 compares the count number of the horizontal dot counter 19 with the X coordinate in the latch circuit 16. When the count number matches the X coordinate, the coincidence detection circuit 17 outputs a detection signal 104, and the clock control circuit 18 receives the detection signal 104 and supplies a shift clock 105 to the shift register 15. The shift register 15 continuously outputs sprite data in synchronization with the shift clock 105. In the priority data selection device of FIG. 1, the sprite data of the pattern shift circuit 11 of SP1 has the highest priority, and the priority is lower in the order of SP1, SP2,..., SP16. The data of (0, 0, 0, 0) out of the 16 color data of the sprite is not colored but transparent.
Not included in the range of data to be selected. That is, the output of the pattern shift circuit 11 is (0, 0, 0,
If 0), it is determined that the data to be selected does not exist. As soon as “1” exists in the data 103 output from the pattern shift circuit 11 of SP1,
The output (enable signal a) of the NOR circuit 12 which is not transparent is "0". Since the output of the pattern shift circuit of SP2 has an AND circuit configuration with the enable signal a, the output of the AND circuit 13 is "0". SP3
Similarly, since the output of the pattern shift circuit 11 has an AND circuit configuration with the enable signal a, the output of the AND circuit is "0". At this time, as the output of the OR circuit 14, the logical sum of the outputs of the 16 AND circuits 13 is obtained, and the same data as the sprite data of the pattern shift circuit 11 of SP1 is output.

That is, the output of the pattern shift circuit 11 is input to the NOR circuit 12, and the output of the NOR circuit 12 is used as an enable signal, whereby the outputs of the pattern data of lower priority are all set to "0". The OR circuit 14 is configured to output the same data as the sprite data having the highest priority among the data output at that time.

[0009]

However, in the circuit configuration of the prior art, the NOR circuit 12 which outputs the enable signals a, b, c,... The delay times of the enable signals a, b, c,... Differ as in a>b>c>. The pattern shift circuit 11 of SP2 to SP16
The AND circuit 13 to which the output of (1) is input has more inputs as the AND circuit processes sprite data with lower priority. Generally, the delay time increases as the number of input gates increases. Therefore, the operation speed of the conventional circuit is SP1
6 is the slowest when sprite data is selected,
There is a clear operational speed bottleneck. In particular, when the conventional circuit is applied to a case where the operation speed is high, there arises a problem that means for eliminating an operation bottleneck must be taken into consideration. That is, the NOR circuit 1
For 2, the transistor size needs to be optimized according to the difference in the gate serving as a load, and for the AND circuit 13, the transistor size needs to be optimized according to the number of input signals. Generally, in order to increase the operation speed, it is necessary to increase the size of a transistor constituting a gate circuit which can be expected to have a delay time.

If such a conventional circuit configuration is realized by a semiconductor integrated circuit, the transistor size is optimized. Each transistor has a different size, and each gate has a different number of inputs. The sizes of the circuits are not the same because the transistor sizes are different, and cannot be made into cells (standardized). In addition, there is also an annoyance that a gate circuit must be created according to each transistor size. In addition, since gate circuits of different sizes must be arranged, and there are also concentrated portions of signal lines, the occupied area of the logic section and the wiring area are increased, and the occupied area on the chip is increased. Has a problem that it becomes large.

The present invention has been made to solve the above-mentioned conventional problems by providing a circuit suitable for a semiconductor integrated circuit that can obtain priority data stably even at a high operation speed. is there.

[0012]

According to the present invention, there is provided an image display control apparatus for controlling a display position of an image pattern to be displayed on a screen and outputting display pattern data. (2 ≦ M) data selection circuits, and the N-th (2 ≦ N ≦ M) data selection circuits each store image data and output display pattern data at a predetermined display position. An output circuit, a priority determination circuit that performs priority determination of the display pattern data output by the pattern data output circuit, and a display pattern output from the pattern data output circuit of the stage in response to an output of the priority determination circuit A priority selection circuit for selecting data or display pattern data output from the data selection circuit in the preceding stage, and The preselection circuit holds the selected display pattern data based on the timing signal output by the timing generation means, and outputs the held output to the next stage to sequentially perform priority determination, and When the priority selection circuit in the data selection circuit outputs display pattern data to be displayed with the highest priority, and when the output of the priority determination circuit in the N-th data selection circuit indicates a priority state, The priority selection circuit in the data selection circuit of the stage selects and outputs display pattern data output from the pattern data output circuit of the stage, and in other cases, selects the data of the (N-1) th stage. The display pattern data output from the circuit is selectively output.

Further, in the image display control device according to claim 1, the output of the priority determination circuit includes a signal indicating that the pattern data is not in a priority state when the pattern data indicates a transparent color. It is characterized by the following.

Further, any one of claims 1 to 2
In the image display control device of the mounting serial to claim, timing signal the timing generating means generates includes a first timing signal and a second timing signal do not overlap each other, and the odd-numbered stages and even-numbered stages The holding is performed based on different timing signals.

Further, electronic equipment of the present invention includes: any one of the serial mounting the image display control apparatus to claim one of claims 1 to 3, the display pattern data to which the image display control apparatus outputs the composite signal Converting means for displaying an image corresponding to the highest priority display pattern data based on the composite signal.

[0016]

[Action] The image display control device configured as described above, the table
A priority selection circuit for selecting the display pattern data.
The priority selection circuit in the data selection circuit of the stage is
The display pattern data is output by the timing generator.
Hold based on the timing signal, and transfer the held output to the next stage
Since the priority is determined sequentially by outputting, only the priority of only two sprite data is determined sequentially.
The operation of determining the priority of the selected data and the next comparison data is sequentially repeated within one operation cycle, thereby performing M-1 determination operations on M pieces of data.

It is only necessary to determine the priority of two data in one operation cycle. The number of passing gate circuits in one operation cycle is reduced, and the delay time allowed for each gate circuit is increased. Therefore, even when the operation speed is high, consideration such as optimizing the transistor size in order to increase the operation speed becomes unnecessary.

Further, according to the above circuit configuration, since it is a repetitive circuit and it is not necessary to optimize the transistor size, in the semiconductor integrated circuit, each gate circuit can be formed into a cell. If the pattern of the basic circuit block is formed into cells, the patterning of the circuit can be easily realized by repeating the cells.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an image display control device according to the present invention will be described in detail.

FIG. 2 is a system block diagram of a personal computer to which the present invention is applied, and mainly comprises an image display control device (VDC) 1, a CPU 2, and a video color encoder (VCE) 3.

The image display control device 1 reads out image data in accordance with the stream from a video RAM (VRAM) 6 under the control of a CPU 2 which decodes a program such as a video game stored in a ROM 5 and a video color encoder 3. To supply. The CPU 2 performs a predetermined control based on a program in the ROM 5, and temporarily stores data, calculation results, and the like in the RAM 4. Video R
The AM 4 receives read / write control from the CPU 2 through the image display control device 1 and stores image information (coordinates, patterns, pattern numbers, etc.). The video color encoder 3 having input the image data outputs a video color signal (including a luminance signal and a color difference signal) based on the internal color data. The video color signal output from the video color encoder 3 is converted into a composite signal via an interface (I / F) 7 and provided to a television (CRT) 8.

FIG. 3 is a block diagram of the image display control device 1 in the embodiment shown in FIG. This image display device 1
Is a one-chip IC. Image control device 1 of FIG.
Are the control unit 30, the address unit 31, the CP
U read / write buffer 32, sprite attribute table buffer 33, sprite shift register 34, background shift register 35, data bus buffer 36, synchronization circuit 37, priority circuit 3
8

When the CPU 2 writes / reads data to / from the video RAM 6 when the CPU 2 cannot process the image display control device 1 in time,
A BUSY terminal for outputting a signal for causing U2 to hold the state, an IRQ terminal for outputting an interrupt request signal,
A CK terminal for inputting a clock of a dot (pixel) frequency, a RESET terminal for inputting a reset signal for initialization, and an EX8 / for inputting a data bus width switching signal for selecting an 8-bit / 16-bit data bus width. It has 16 terminals.

The address unit 31 is connected to terminals MA0 to MA15 for outputting an address signal of the video RAM 6. The address space of the video RAM 6 is 6553.
It is 6 words (1 word 16 bits). Further, an address unit 31, a CPU read / write buffer 32,
The sprite attribute table buffer 33, the sprite shift register 34, and the background shift register 35 are connected to MD0 to MD15 terminals via a data bus. Data in the video RAM 6 is input / output via the MD0 to MD15 terminals.

Sprite attribute table buffer
A33Indicates a sprite (16 x 16 dots)position
Internal memory for storing (X, Y), color, pattern number, etc.
It is.

Sprite attribute buffer 33
Is the sprite display position (X, Y), pattern number,
After obtaining the sprite color and the like, the video RAM 6 is accessed based on the sprite pattern number during the horizontal retrace period one raster before the raster to be displayed.
The pattern data read from the sprite generator is stored in the sprite shift register 34. The sprite shift register 34 also stores the X coordinate and sprite color data of the sprite stored in the sprite attribute buffer 33. Next, when the raster to be displayed is reached, the count number of the horizontal dot clock counter in the sprite shift register 34 and the X coordinate become X.
The data is compared by the coordinate coincidence detection circuit. When the two coincide, the pattern data is output from the pattern shift circuit in the sprite shift register 34, and is output from the sprite shift register 34 through the priority data selection device.
The priority data selection device selects the pattern data having the highest priority when the pattern data is output from a plurality of pattern shift circuits (storage means) that fetch and store the pattern data. The address unit 31 generates an address of the video RAM 6 from the raster position, reads an attribute table in the video RAM 6, generates an address of a character generator obtained from the address table, and generates a pattern read based on the address. It is stored in the background shift register 35 together with the area color.

The data bus buffer 36 is connected to data input / output terminals D0 to D15. Read / write from the CPU 2 is performed via the data bus buffer 36. The image display control device 1 can select an 8-bit interface or a 16-bit interface in accordance with the data width of the system including the CPU 2, and when the 8-bit interface is selected, D
Terminals D0 to D7 of terminals 0 to D15 are used.

The synchronizing circuit 37 outputs a DISP terminal indicating a signal indicating a display period, a VSYNC terminal for outputting a signal for vertically synchronizing the CRT and inputting an external vertical synchronizing signal, and a signal for horizontally synchronizing the CRT. And an HSYNC terminal for inputting an external horizontal synchronizing signal.

The priority circuit 38 is connected to terminals VD0 to VD7 for outputting video data, and to an SPBG terminal for outputting a signal "H" when the video data is sprite data and a signal "L" when the video data is background data. It is connected. The priority circuit 38 switches between sprite data output from the sprite shift register 34 and background data output from the background shift register 35 in accordance with an internal setting.

The control unit 30 is provided with a CS terminal so that the CPU 2 can read / write the internal register in the control unit 30. C
When the “L” signal is input to the S terminal, the CPU 2 can read / write the internal register of the control unit 30. Read / write selection is RD terminal, WR
The selection is made by setting one of the terminals to “L”. The A0 terminal and the A1 terminal are connected to the address bus of the CPU2, and in combination with the RD and WR signals,
The type of the data bus signal is selected. The MRD terminal is a timing output when the image display control device 1 reads data from the video RAM 6, and the MWR terminal is a timing output when the image display control device 1 writes data to the video RAM 6.

The image display control apparatus according to one embodiment using the present invention and the system according to one embodiment including the image control apparatus have been described.

Next, the main part of one embodiment of the present invention will be described. FIG. 4 is a circuit diagram showing a main part of the sprite shift register 34 of the image display control device of FIG.

In FIG. 4, the circuit according to the present embodiment includes basic circuit blocks BP1, BP2,.
16 has a circuit configuration in which 16 stages are stacked. The basic circuit block surrounded by the dotted line is a pattern shift circuit 4
1, a NOR circuit 42, an AND circuit 43, a clocked NOR circuit 44, an inverter circuit 45, a clocked NAND gate 46, and an inverter 47. Pattern shift circuit 4
1 is four shift registers 48 each having a length of 16 bits.
A latch circuit 49 for storing the display coordinates (X coordinate) of the sprite, a latch circuit 50 for storing the count number of the horizontal dot counter 53, and a relation between the X coordinate in the latch circuit 49 and the count number in the latch circuit 50. A coincidence detection circuit 51 for performing coincidence detection, and a detection signal 114 of the coincidence detection circuit 51
And a clock control circuit 52 that supplies the shift clock 115 to the shift register 48. The output 116 of the latch circuit 50 in the pattern shift circuit 41 is connected to both the coincidence detection circuit 51 and the input of the latch circuit 50 in the pattern shift circuit 41 at the next stage.

Next, the operation of this embodiment will be described. During the horizontal retrace period prior to the display, the image display control device 1 transmits the sprite pattern data read from the sprite generator in the video RAM 6 to the pattern shift circuit 41.
The X-coordinate of the sprite stored in the sprite attribute buffer 33 is read out in parallel through a pattern input signal line 110 in a shift register 48 therein, and the pattern shift circuit 41 is read out through an input line 111.
And stored in the latch circuit 49. By repeating this operation 16 times, 16 pieces of sprite data are stored. The pattern shift circuit 41 accumulates each data according to the read clock signal 112 connected to each shift register 48.

Next, in the display period, the horizontal dot counter 53 starts counting. The latch circuits 50 are connected in cascade, and sequentially send the count number of the horizontal dot counter 53 to the next-stage latch circuit 50. The coincidence detection circuit 51 compares the X coordinate stored in the latch circuit 49 with the count number of the latch circuit 50, and outputs a detection signal 114 to the clock control circuit 52 when they match. The clock control circuit 52 supplies the shift clock 115 to the shift register 48 in response to the detection signal. The shift register 48 receives the clock 115 and sends out the pattern data serially.

The transmitted data is transmitted to a NOR circuit 42,
The signal is input to the AND circuit 43. The inputs of the AND circuit 43 are the pattern data of the pattern shift circuit 41 and the enable signal output from the preceding basic circuit block, and the output of the AND circuit 43 is input to the clocked NOR circuit 44. The input of the clocked NOR circuit 44 is the output of the AND circuit 43 and the data output from the preceding basic block. The output of the clocked NOR circuit 44 is the input of the inverter circuit 45, and the output of the inverter circuit 45 is It is output as pattern data to the basic circuit block of the stage. The output of the NOR circuit 42 is input to the clock NAND circuit 46 together with the enable signal output from the previous basic block. The output of the clock NAND circuit 46 is inverted via the inverter 47, and the output of the inverter 47 is Is an enable signal for the basic circuit block.

The clocked NOR circuit 44 outputs data when the clock is "H", and holds the data by the stray capacitance between the clock and the input of the inverter circuit 47 when the clock is "L". That is, it operates as a dynamic latch circuit. The clock NAND circuit 46 also operates as a dynamic latch. Although a dynamic latch circuit is used in the present embodiment, the present invention can be implemented using a static latch circuit, and the present invention is not limited to the dynamic latch circuit. For example, the clocked NOR circuit 44 can be realized by using a NOR circuit and a static latch circuit.

In the circuit of this embodiment, the pattern data stored in the pattern shift circuit in the block of BP1 has the highest priority, and hereinafter BP2, BP3,.
6 in the order of the data. The operation clock of the odd-numbered circuit blocks BP1, BP3,...
The operation clock of the even-numbered circuit block of 2, BP4,... Is φ2. The phase relationship between φ1 and φ2 is a non-overlapping two-phase clock as shown in FIG. The control clock of the latch circuit 50 in the pattern shift circuit 41 in the odd-numbered block of the basic circuit blocks BP1, BP3, BP5,... And the shift clock of the shift register 48 are synchronized with φ1, and the basic circuit blocks BP2, BP4 , BP
The control clock of the latch circuit 50 in the pattern shift circuit 41 in the even-numbered block of 6,... And the shift clock of the shift register 48 are synchronized with φ2.

Now, from the pattern shift circuit 41 of BP1
It is assumed that pattern data is output when 1 is "H". If "1" to be selected exists in the output data, the output of the NOR circuit 42 becomes "0" and the enable signal a becomes "0". The output of the inverter circuit 45 is
The same data as the data output from the pattern shift circuit 41 is obtained. When φ1 becomes “L”, the enable signal a
The output of the inverter circuit 45 holds data because the clocked AND circuit 46 and the clocked NOR circuit 44 perform a latch operation. Next, φ2 becomes “H”,
Assuming that data is output from the pattern shift circuit 41 of BP2, since the enable signal a is “0”,
All outputs of the AND circuit 43 of BP2 become “0”, and B
The same data as the output data of the inverter circuit 45 of BP1 at this time is output to the output of the inverter circuit 45 of P2.

The enable signal b becomes "0" because the enable signal a is "0". Next, when φ2 becomes “L”, the enable signal b and the inverter circuit 4
The output of No. 5 holds data because the clocked NAND circuit 46 and the clocked NOR circuit 44 perform a latch operation as described above. Next, when φ1 becomes “H” and the pattern data is output from the pattern shift circuit 41 of BP3, the output of the inverter circuit 45 of BP3 becomes the output of BP2 at this time because the enable signal b is “0”. It becomes the same data as the output data of the inverter circuit 45. As described above, by sequentially performing the operation of selecting and holding the priority data in synchronization with the clock using the latch circuit, B
The priority data is obtained from the inverter circuit of P16. In this example, the same data as the pattern data of BP1 is extracted as the priority data.

FIG. 5 shows another embodiment of the present invention. The circuit of the present embodiment also has a circuit configuration in which 16 stages of basic circuit blocks BP1, BP2,... The basic circuit block includes a pattern shift circuit 61, a NOR circuit 62, an AND circuit 63, a clocked NOR circuit 64, and an inverter circuit 65.
Having. The pattern shift circuit 61 includes a shift register 66, a latch circuit 67, a latch circuit 68, a coincidence detection circuit 69, and a clock control circuit 70 as in FIG. The horizontal dot counter 71 is connected to the latch circuit 68. The pattern shift circuit 61 used in FIG. 5 operates in the same manner as the pattern shift circuit 41 in FIG. The basic circuit operation of FIG. 5 is the same as the circuit of FIG. In the circuit of the embodiment of FIG. 5, the pattern data stored in the pattern shift circuit in the block of BP16 has the highest priority, and hereinafter, BP15, BP14,.
The order is P1. The operation clock of the odd-numbered circuit block of BP1, BP3,...
The operation clock of the even-numbered circuit blocks of P4,... Is φ2.

Assume that pattern data is output when φ1 is “H” from the pattern shift circuit 61 of the BP1. At this time, the output of the inverter circuit 65 becomes the same data as the pattern data output from the pattern shift circuit 61. Next, when φ1 becomes “L”, the inverter circuit 65
Is held in data because the clocked NOR circuit 64 performs a latch operation. Next, when φ2 becomes “H” and the pattern data is output from the pattern shift circuit 61 of BP2 and there is “1” to be selected in the output data, the output of the NOR circuit 62 of BP2 becomes “0”,
The outputs of the AND circuit 63 of BP2 are all "0". Therefore, the output of the inverter circuit 65 at this time becomes the same data as the data output from the pattern shift circuit 61 of BP2. Next, when φ2 becomes “L”, the output of the inverter circuit 65 of BP2 is held as it is by the latch operation. Next, when φ1 becomes “H”, the output of the pattern shift circuit 61 of BP3 and the inverter circuit 65 of BP2
Is compared with the output of BP3 pattern shift circuit 6
If all the outputs of 1 are "0", the output of the inverter circuit 65 of BP2 is selected, and the output of the inverter circuit 65 of BP3 is selected.
Is the same data as the data of the inverter circuit 65 of BP2 at this time. As described above, the operation of selecting and holding priority data is sequentially performed in synchronization with the clock using the latch circuit.
From which priority data can be obtained.

As described above, in this embodiment,
Using a dynamic latch circuit, the priority of the two data is sequentially determined in synchronization with the operation clock,
While repeating this operation, all data are compared to obtain priority data.

[0044]

The image display control apparatus according to the present embodiment is provided with a plurality of pattern shift circuits (shift registers) in order to perform a plurality of moving image superimposition processes, and performs a pattern shift according to display coordinates on a screen. It outputs pattern data from the circuit, and performs the operation of judging priority sequentially in synchronization with the operation clock by combining the selection circuit and the latch circuit for the superimposition processing of a plurality of moving images. It repeatedly displays the highest priority pattern data to be displayed. In particular, the operation in one operation cycle is only comparison and selection of two pattern data, and the number of passing gate stages in one operation cycle Has the advantage of being able to reduce For this reason, even if the delay time permitted for each gate circuit within one operation cycle is long, it operates reliably. For example, consider the case where frequency is operated at high speed 21MH _Z. In the image display control apparatus of the present invention embodiment, since by the comparison and selection operation of the two pattern data of a half clock period, half of the period (approximately 23n of 21MH _Z
This operation must be completed within sec), but the delay time of a typical gate circuit of an ordinary semiconductor integrated circuit is about 2 to 3 nsec. In this embodiment, the gate from the pattern shift circuit to the latch circuit is Since the number of circuit stages is required to be about 5 including the number of gate circuits in the pattern shift circuit, the pattern data is taken into the latch circuit in about 10 to 15 nsec, and the circuit operation is sufficiently ensured. Will be. Thus, when the operation speed is fast even (21MH _Z), the desired priority data stably obtained.

Further, in this embodiment, the circuit is a repetition of the same circuit block. This repetition is a repetition of the same pattern on the artwork when this circuit is formed into an IC. Therefore, when the basic circuit block is formed into cells, patterning can be achieved only by stacking the cells. Also, since the wiring of the signal lines is formed only by stacking the blocks, there is no need to provide a special wiring area connecting the cells, and the wiring is efficiently performed, and the wiring portion on the chip The occupied area can be reduced. This embodiment thus is easy IC artwork, there is effect that it is possible to further reduce the occupied area on the chip, Ru circuit der suitable for semiconductor integrated circuits. As described above, the image display control device of the present invention
Controls the display position of the image pattern to be displayed on the screen
Image display control device that outputs display pattern data
The timing generation means and M data selection (2 ≦ M)
And an N-th stage (2 ≦ N ≦ M).
Each of the selection circuits stores the image data and sets a predetermined display position.
Output pattern data to output display pattern data to
Path and the display output by the pattern data output circuit
A priority determination circuit for determining priority of the pattern data;
According to the output of the priority determination circuit, the pattern
Display pattern data output from the data output circuit or
Display pattern data output from the data selection circuit
And a priority selection circuit for selecting data.
The priority selection circuit in the data selection circuit is connected to the selected display pattern.
The turn data is output by the timing generation means.
Hold based on the imaging signal and output the held output to the next stage.
The priority of the data selection in the M-th stage
Display that the priority selection circuit in the selection circuit displays with the highest priority
Pattern data is output, and the data selection of the N-th stage is performed.
When the output of the priority determination circuit in the selection circuit indicates a priority state,
In the case, the priority selection circuit in the data selection circuit of the stage
Is output from the pattern data output circuit of the stage.
Select and output the display pattern data to
Is a table output from the data selection circuit in the (N-1) th stage.
Display pattern data is selected and output.
Delay until the highest priority display data pattern is output.
The delay time does not depend on the number of stages, so if the operating speed is fast,
A if desired priority data in a stable can be obtained. Ma
The last row has the highest priority, and
An image display control device that operates so that the priority is low is obtained.
It is. Further, the image display control device of the present invention further comprises:
The output of the priority determination circuit is that the pattern data is a transparent color.
, The pattern data has priority.
Since it contains a signal indicating that it is not in the state,
Treat light colors as a kind of color and treat them in the same way as other colors
Is possible, and colors that are not transparent are given priority.
Can be. Further, the image display control device of the present invention further comprises
A timing signal generated by the timing generation means.
Are the first non-overlapping timing signal and the second
The odd-numbered stage and the even-numbered stage
The holding based on the different timing signals.
Therefore, the odd-numbered stage and the even-numbered stage
The priority judgment is performed alternately so that they do not overlap.
No misjudgment occurs. Therefore, the data selection circuit
Can be reliably processed within the delay time of one stage.
Further, the electronic device of the present invention, the image display control device,
The display pattern data output by the image display control device is
Means for converting the composite signal into a composite signal.
Response to the highest priority display pattern data based on the
Since multiple images are displayed, multiple screens
One screen is formed according to the priority and there is no misjudgment at high speed.
Can be displayed on a display device.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a conventional example.

FIG. 2 is a system block diagram of a personal computer to which the present invention is applied.

FIG. 3 is a block diagram showing an image display control device which is formed into an IC by applying the present invention.

FIG. 4 is a circuit diagram showing one embodiment of the present invention.

FIG. 5 is a circuit diagram showing another embodiment of the present invention.

FIG. 6 is a timing chart of a clock used in the present embodiment.

[Explanation of symbols]

 In FIG. 1, 11 ... Pattern shift circuit 12 ... Nor circuit 13 ... And circuit 14 ... OR circuit 15 ... Shift register 18 ... Latch circuit 17 ... Match detection circuit 18 ... Clock control circuit 19 ... Horizontal dot counter In FIG. Image display control device 2 CPU 3 Video color encoder 4 RAM 5 ROM 6 Video RAM 7 Interface 8 Telegraph In FIG. 3, 1 Image display control device 6 Video RAM 80 Control unit 31 Address unit 32 CPU read / write buffer 33 sprite attribute table 34 sprite shift register 35 background shift register 36 data bus buffer 37 synchronization circuit 38 priority circuit In FIG. Road 42 ... NOR circuit 43 ... AND circuit 44 ... Clocked NOR circuit 45 ... Inverter circuit 46 ... Clock donand circuit 47 ... Inverter 48 ... Shift register 49 ... Latch circuit 50 ... Latch circuit 51 ... Match detection circuit 52 ... Clock control circuit 53 ... horizontal dot counter In FIG. 5 61 ... pattern shift circuit 62 ... NOR circuit 63 ... AND circuit 64 ... clocked NOR circuit 65 ... inverter circuit 66 ... shift register \ 67 ... latch circuit 68 ... latch circuit 69 ... coincidence detection circuit 70: Clock control circuit 71: Horizontal dot counter

Continuation of the front page (72) Inventor Yasuaki Hagiwara 3-5-5 Yamato, Suwa-shi, Nagano Seiko Epson Corporation (56) References JP-A-62-35393 (JP, A)

Claims (4)

(57) [Claims] 1. An image display control device for controlling a display position of an image pattern displayed on a screen and outputting display pattern data, comprising: a timing generation means; and M (2 ≦ M) data selection circuits. The data selection circuits of the N-th stage (2 ≦ N ≦ M) each store image data and output display pattern data at a predetermined display position; and the pattern data output circuit outputs the pattern data output circuit. A priority determination circuit that determines the priority of the display pattern data; and a display pattern data output from the pattern data output circuit of the corresponding stage or a display output from the data selection circuit of the preceding stage in accordance with an output of the priority determination circuit. A priority selection circuit for selecting the pattern data, wherein the priority selection circuit in the data selection circuit of each stage includes the selected display pattern. Data is held on the basis of a timing signal output by the timing generation means, and the held output is output to the next stage to sequentially determine priority. ,
The display pattern data to be displayed with the highest priority is output. If the output of the priority determination circuit in the data selection circuit of the Nth stage indicates a priority state, the priority selection in the data selection circuit of the stage is performed. The circuit selectively outputs the display pattern data output from the pattern data output circuit in the stage, and selectively outputs the display pattern data output from the data selection circuit in the (N-1) th stage, except in the above case. An image display control device, comprising: 2. An image display control device according to claim 1, wherein an output of said priority determination circuit includes a signal indicating that said pattern data is not in a priority state when said pattern data represents a transparent color. An image display control device, characterized in that: 3. A request for any one of the claims 1 to 2
The image display control device of the mounting serial to claim, timing signal the timing generator occurs,
An image display control device comprising: a first timing signal and a second timing signal that do not overlap each other, wherein the odd-numbered stages and the even-numbered stages perform the holding based on respective different timing signals. Wherein any one of claims one of claims 1 to 3
A serial mounting the image display control apparatus in the item display pattern data in which the image display control apparatus outputs and means for converting the composite signal, the image corresponding to the display pattern data of the highest priority based on said composite signal Electronic equipment characterized by displaying.