JP2723847B2 - Microprocessor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a microprocessor, and more particularly, to a microprocessor having a plurality of register sets.

[0002]

2. Description of the Related Art First, an interrupt response function of a conventional microprocessor will be described.

A function required for interrupt processing in a general microprocessor is, first, a mechanism for selecting a process corresponding to a specific interrupt response and changing an execution destination address in order to execute a predetermined process. The second is a mechanism for completely guaranteeing the state before the occurrence of the interrupt when returning to the interrupted processing after the end of the interrupt processing.

An object of the present invention relates to the above-mentioned second mechanism. From the viewpoint of the second mechanism, the above-described interrupt processing in a general microprocessor will be described.

[0005] When an interrupt occurs in the microprocessor, the process currently being executed is first interrupted, and then the interrupt process corresponding to the interrupt factor is started. At that time,
In order to return to the interrupted process, the address data of the execution program of the interrupted process and the status data at that time (hereinafter P
SW). Normally, in order to effectively use the function for re-interruption of another factor during interrupt processing (hereinafter referred to as multiple interrupts), generally, an area called a stack area is secured in memory and loaded in it. Realize. By doing so, it is possible to avoid losing information necessary for return to multiple interrupts.

Next, at the beginning of the interrupting program, registers to be used for the interrupt processing are explicitly saved by an instruction, and then processing specific to the interrupt processing is performed. The reason is that there is a possibility that those registers are being used in the processing of the interrupted side. Generally, this saving is also performed in the stack area in the memory described above.

When the interrupt process is completed, the registers saved at the beginning of the interrupt process are restored again, and then the process returns to the interrupted process. At this time, the automatically saved execution destination address data and PSW state are restored. As a result, the interrupted process can be resumed from the point at which it was interrupted. The reason why the registers to be saved at the beginning of the above-described interrupt processing are explicitly saved by an instruction is that registers used on the interrupt processing side differ depending on the contents of each interrupt processing.

The above-described general microprocessor mechanism has an advantage that it is only necessary to secure a set of continuous stack areas in the memory and to manage only the size of the stack area for multiple interrupts. However, input and output to and from the memory generally consumes time, and these times are times that should be eliminated if possible in the original processing. In particular, a microprocessor incorporated in an electronic device needs to quickly respond to frequently occurring interrupts, and the interrupt processing itself is often simple and simple. Therefore, in the case of the above-described interrupt processing mechanism of the general microprocessor, the extra processing of saving the register results in a performance that cannot be ignored.

Therefore, in the embedded microprocessor, a plurality of register sets are provided in order to minimize the register saving time in the above-described interrupt processing, and the register set is switched every time an interrupt is generated, so that the register set is changed. Many have a function of omitting the evacuation processing. Hereinafter, two examples of the conventional microprocessor having the plurality of register sets will be described.

FIG. 6 is a block diagram showing a first example of a conventional microprocessor. It will be described with reference to FIG.

The conventional microprocessor includes an execution unit 200, a register set group 201, and an interrupt control unit 2.
02, a register set selecting unit 205, a specific register set is assigned in advance to each interrupt factor, and the corresponding register set is automatically selected when an interrupt occurs.

The execution section 200 is a main body of the microprocessor and executes a program.

The register set group 201 is a group of a plurality of register sets used in the execution unit. The register set group 201 includes a plurality of signal lines. The output signal group 11 exchanges data with each other.

The interrupt control unit 202 receives a plurality of interrupt request signal groups 1 from the outside of the microprocessor and includes a plurality of signal lines for instructing the execution unit 200 what kind of interrupt processing is to be performed. The interrupt vector signal 3 is provided to the execution unit 200. Execution unit 200
Receives the interrupt vector signal 3, changes the execution address to the designated interrupt processing, and starts the interrupt processing. Also, the execution unit 200 sends an interrupt control unit 202
And an IE signal 2 notifying that the execution unit can accept the interrupt, an INT signal 4 indicating that the interrupt process has been accepted, and an IRET signal 5 indicating the return from the interrupt process. The consistency between the unit 202 and the execution unit 200 is obtained.

The register set selecting unit 205 generates a register set specifying signal 10 composed of signal lines required to specify the number of register sets in order to specify a register set to be used in the program currently being executed. This is given to the register set group 201.

For this reason, the register set selection unit 205
Has a storage unit for designating a register set corresponding to each interrupt vector, and has a function of outputting a register set designation signal 10 appropriate for the value of the interrupt vector signal 3 from the interrupt control unit 202. In the storage unit, a correspondence table is written in advance by the register set advance designation signal group 13 at the initial stage of program execution from the normal execution unit 200. Further, the execution unit 200 stores an interrupt vector shallower than the depth of the currently executed interrupt processing.
It has a mechanism that can return to the register set of the process interrupted by the input IRET signal 5.

In addition to the configuration and signal lines described above, the microprocessor normally needs to externally supply a clock signal 6 for giving a unit of execution progress and a reset signal 7 for initially initializing the operation of the microprocessor. There is. The reason is that the execution unit 200, the interrupt control unit 202
And the register set selection unit 205 for synchronization.

Although this mechanism cannot be used for multiple interrupts of the same factor, a register set can be assigned for each specific interrupt factor, so the application is relatively simple and the number of interrupt factors is smaller than the number of register sets. In some cases, it is an effective mechanism. An example of this mechanism is disclosed in JP-A-3-209528.

However, in the case of this conventional example, if the number of interrupt factors is equal to or greater than the number of register sets, it is necessary to devise the assignment between register sets for each interrupt factor, and at the same time, the interrupt factors not assigned to the register set However, there is no other method than using the mechanism of the general microprocessor described above, and there is a disadvantage that the response time is sharply increased in the interrupt processing.

In today's embedded microprocessors, the number of required interrupt sources is increasing significantly compared to the number of register sets that can be economically held by the microcomputer as the functions become more sophisticated. .

FIG. 7 is a block diagram showing a second conventional microprocessor. It will be described with reference to FIG.

This conventional microprocessor automatically increases the value of the register set designating signal 10 when an interrupt occurs in the register set selecting section 205 for selecting a register by the interrupt vector signal 3 of the first conventional example. It is replaced by a register set selection unit 204 having a mechanism for reducing the number of bits by returning from an interrupt, and the other functions are the same.

The register set selection unit 204 does not need the interrupt vector signal 3 and the register advance designation signal from the execution unit 200 since the selection of the register set is obtained by the counting means. An example of this is disclosed in
No. 33558. Hereinafter, the register set selecting section 205 of the first conventional example and the register set selecting section 204 of the second conventional example are distinguished by reference numerals.

In the case of this conventional example, it is not necessary that the number of interrupt factors is smaller than the number of register sets as compared with the first conventional example, and the depth of multiple interrupts during actual operation of the microprocessor is smaller than the number of register sets. The difference is that it works effectively if it is small. In general, during the actual operation of the microprocessor, the depth of multiple interrupts is smaller than the number of interrupt sources, so for the same application, this conventional example can deal with a smaller number of register sets than the first conventional example. Become.
The reason will be described below.

Assuming that the probability of occurrence of any interrupt in any given state of the microprocessor is P, n
The probability of occurrence of more interrupts is P raised to the nth power.
This probability is not affected by the number of interrupt sources. Of course, as the number of interrupt factors increases, the probability P of occurrence of an interrupt increases, but it is reasonable to consider that the probability P of some kind of interrupt processing in the general operation of the microprocessor is at most １ ／ or less. Here, assuming that the number of register sets is eight as a value practically possible by the microprocessor, the probability of occurrence of eight or more interrupts is 1/128. As described above, in the case of eight register sets, the possibility that the register set becomes insufficient is extremely small.

The problem with this mechanism is that some protection mechanism is required when multiple interrupts occur in the actual operation that exceed the number of register sets held by the microprocessor. In general, there is a mechanism for counting the depth of an interrupt, and when multiple interrupts greater than the number of register sets occur by detecting the value by the microprocessor, a method for switching to the mechanism of the general microprocessor described above is used. Conceivable.

However, when the depth of the multiple interrupts is equal to or greater than the number of register sets, the first problem similar to the first conventional example in which the saving process to the memory always occurs in all the interrupt processes and the response time sharply increases. There is a second problem that is disadvantageous in comparison with the first conventional example in which an interrupt depth overflow check process must be performed at the beginning of all interrupt processing programs.

[0028]

As described above, in the first conventional example, when the interrupt factor is equal to or larger than the number of register sets, the extra processing at the time of the occurrence of the interrupt cannot be effectively reduced. Also, in the second conventional example, the same number of register sets can cope with more interrupt factors than the first conventional example, but when the depth of the interrupt becomes larger than the number of register sets in actual operation, There are a first problem that extra processing at the time of occurrence of an interrupt suddenly increases, and a second problem that a process of detecting the depth of the interrupt is required at the beginning of all interrupt processing programs.

An object of the present invention is to improve an interrupt response time in a microprocessor having a plurality of register sets.

[0030]

Therefore, the present invention comprises a plurality of register sets, controls acceptance of an interrupt request according to an interrupt enable signal, and returns from an interrupt signal indicating that the interrupt request has been accepted and interrupt processing. A microprocessor having an interrupt processing function of performing selection control of the register set in response to a return signal indicating that the count value has been incremented by the generation of the interrupt signal and decremented by the generation of the return signal. Means, an increment suppressing means for suppressing an increment of the count value when the count value reaches a maximum value equal to the set number of the register set, and a decrement of the count value when the count value reaches a minimum value. And a signal indicating that an interrupt request has been accepted when the count value is the maximum value. And an interrupt processing control means comprising: an overflow notification means for outputting as control information for the only processing; and a minimum value notification means for outputting a signal indicating that the count value is the minimum value as control information for the interrupt processing. .

A storage processing means for storing address data and status data of a program executed before the interruption when the interrupt signal is generated in an area in the register set selected before the interruption; Return processing means for returning the address data and the status data from the selected area in the register set when a return signal is generated, and continuously executing the program.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the microprocessor of the present invention.

The microprocessor of this embodiment includes an execution unit 200, a register set group 201, an interrupt control unit 202 for controlling acceptance of an interrupt request according to an interrupt enable signal, an interrupt signal indicating that an interrupt request has been accepted, and an interrupt process. A register set selection unit 204 for controlling the selection of a register set in response to a return signal indicating that the operation has returned from the CPU, and an interrupt processing control unit 203. Note that this register set selection unit 204
Like the usual counter, the position of the selected register set
If an interrupt occurs when the value is
The position of the register set becomes the minimum value, and the position of the register set becomes
When returning from an interrupt when the value is at the minimum value, the register
The position of the unit changes to the maximum value. The difference from the microprocessor of the second conventional example shown in FIG. 7 is that an interrupt processing control unit 203 is added. Other blocks are omitted because it is the same as FIG.

The microprocessor of this embodiment inputs the overflow signal 8 and the minimum value signal 9 output from the interrupt processing control unit 203 to the execution unit 200, and outputs the logic values of these two signal lines to the execution unit. It is read by 200 instructions, and the interrupt processing program is controlled by those values.

FIG. 2 is a circuit diagram showing a detailed configuration of the interrupt processing control unit 203 in the first embodiment of FIG. The description will be continued with reference to FIG.

The interrupt processing control unit 203 includes a counter 100, an increment suppressing means including an AND circuit 101 and a NOT circuit 102, and an AND circuit 103 and a NOT circuit.
It comprises a decrement suppressing means consisting of a circuit 104 and an overflow notifying means consisting of a JKFF 105 and an AND circuit.

The interrupt processing control unit 203
The microprocessor has four input signals, an INT signal 4 for notifying that the interrupt has been accepted, an IRET signal 5 for notifying return from the interrupt, a clock input signal 6, and a reset signal 7 for initializing the circuit. It has two output signals, an overflow signal 8 indicating that the number of sets has continuously occurred and a minimum value signal 9 indicating that the counter 100 has the minimum value. INT signal 4 and I
The RET signal 5 is assumed to be a signal having a logical value of 1 for a period of one clock width when one event occurs. The clock signal 6 is obtained from a basic clock that supports the operation timing of the microprocessor.

The counter 100 is a counter capable of counting the number of register sets included in the microprocessor, and includes a MAX output for outputting a logical value 1 when the internal count value is a maximum value, and a minimum output value. Output logical value 1 when
It has an IN output. Note that the maximum value and the
And the minimum value is a numerical value that can be used to count the number of register sets.
For example, if the minimum value is 0, the maximum value is
The number of register sets minus 1, if the minimum value is 1, the maximum
The value will be the number of register sets. An input CK to which the clock signal 6 is input, an increase input U for increasing the count value inside the counter 100 by one when the signal of the input CK changes to a logical value 1 if the logical value is 1; When the signal changes to a logical value 1, if the logical value is 1, the decreasing input D for decreasing the internal count value of the counter 100 by one, and the logical value 1 is input when the logical value 1 is inputted regardless of the other inputs. It has four inputs R, to which a reset signal 7 for initializing the internal count value of 100 to 0 is input.

In the counter 100, the input U and the input D described above do not become 1 at the same time, and if both the input U and the input D have the logical value 0, the signal of the input CK becomes the logical value. It has a mechanism that the internal count value does not change even when it changes to 1. Since this counter already exists as a single product, further description will be omitted.

Next, in the increment suppressing means including the AND circuit 101 and the NOT circuit 102, the NOT circuit 10
The input of 2 is input from the MAX output of the counter 100. The AND circuit 101 receives the output of the NOT circuit 102 and the INT signal 4 as inputs, and outputs the output to the input U of the counter 100.

Similarly, in a reduction control means comprising an AND circuit 103 and a NOT circuit 104, the NOT circuit 1
04 is input from the MIN output of the counter 100. The AND circuit 103 receives the output of the NOT circuit 104 and the IRET signal 5 as inputs, and outputs the output to the input D of the counter 100.

The JKFF 105 and the AND circuit 1
In the overflow notification unit 06, the AND circuit 106 receives the MAX output of the counter 100 and the INT signal 4 as inputs and outputs the input to the input J of the JKFF 105. The input K of the JKFF 105 has an IRET signal 5
, And a reset signal 7 is applied to its input R. JKFF105 which is a JK flip-flop
When the input CK changes to the logical value 1, the logical value 1 is output if the input J is the logical value 1, the logical value 0 is output if the input K is the logical value 1, and both the input J and the input K are output. If the logical value is 0, the output does not change. The output Q of this JKFF105
Thus, the overflow signal 8 is generated.

Further, by outputting the MIN output of the counter 100 as the minimum value signal 9, the minimum value notification means is constituted.

Next, the details of the operation of the interrupt processing in the microprocessor will be described with reference to the drawings.

FIG. 3 is a flowchart showing a typical example of an interrupt processing program for realizing the effect of the present invention in the present embodiment. FIG. 4 is a graph prepared in order to make the description easier to understand, and shows a time-series example of a change in the depth of the interrupt in the actual execution of the program, with the vertical axis representing the depth of the interrupt. For ease of explanation, the vertical axis indicates the depth of interrupt and the horizontal axis indicates time. Hereinafter, description will be made with reference to FIG.

The lower left of the graph in FIG. 4 is the start of the execution of the microprocessor. When the horizontal line of the graph changes to an upward vertical line, an interrupt occurs, and when the horizontal line changes to a downward vertical line, it means return from the interrupt.

The time point a is when a single interrupt occurs. Time point b is the occurrence of a single interrupt after all interrupt processing has been completed once. All of the interrupt processing has the configuration of the format shown in FIG.

From the time point a to the interrupt processing immediately before the time point b and the time point c, since the overflow signal 8 does not overflow at the beginning of the interrupt processing in FIG. Then, the process proceeds to step 303 without executing step 302. Also, when returning from the interrupt processing, since the minimum value signal 9 is not the minimum value, the interrupt return instruction of step 308 is executed without executing step 307. During this period, the register set is sequentially switched and used between all the interrupt processes.

At time point c, since the register set has been used up, the overflow signal 8 is valid at the first time point of the interrupt processing.
Is executed. As a result, the currently selected registry
The contents of the tuset are saved, but its registers are
This is used when the depth of the embedding is 0.

Similarly, in the interrupt processing at the time points d and e, the register is saved because the overflow signal 8 is valid. The register set saved at this time is:
Used when the interrupt depth was 1 and 2
It is.

However, as a feature of the present invention, the minimum value signal is valid at the return point j of the interrupt processing generated at the time point c and at the return points g and f of the interrupt processing at the subsequent time points d and e. Therefore, the process of restoring the register set in step 307 of FIG. 3 is not performed. Even if the return process is not performed,
Register set has a current interrupt depth
Since it is a register set used in 0 to 3,
This is because it is not necessary at this point.

Further, a characteristic point is that when an interrupt process occurs at time point h , the interrupt process control unit 203
Since the counter 100 in FIG.
No overflow signal 8 is generated, resulting in step 3
02 is not executed. However, use at this point
The register bank that is set to
Used in the generated interrupt processing program
There is no problem if used as it is. The contents of the register set saved at the time points c, d and e are restored at the time points m, l and k. This operation is a feature of the present invention, and the reason can be easily understood from the circuit of FIG. 1 and the flowchart of FIG. For this reason, the save and restore processing of the contents of the register set in the case of the present invention
It is optimized to the minimum number of times in an actual series of multiple interrupt operations.

As described above, the present invention has the effect of minimizing the extra processing that occurs due to the processing of saving the contents of the register set in the interrupt processing.

The case of a mechanism for simply detecting the depth of multiple interrupts, which is different from the present invention, will be described with reference to the example of FIG. 4. The return processing is performed at time f, time g, time i, and time j. Therefore, the evacuation process and the restoration process in this case are eight times in total, which is always larger than six times in the example of the present invention.

A feature of the present invention is that the save of the register set and the process of restoring the register set are unnecessary unless the continuous interrupt generation or the return from the continuous interrupt continues for more than the number of register sets. The feature is that the save and restore processing of the register set is not required while the occurrence and return of the register set are up and down with a small width.

Further, a circuit for realizing the technique of simply detecting the depth of an interrupt described in the prior art must incorporate a counter for the depth of an actually generated interrupt. However, there is a disadvantage that a counter close to the address value of the microprocessor is required.

Next, the interrupt processing in step 302 of FIG. 3 in the first embodiment is an interrupt processing after the depth of the interrupt reaches the number of register sets or more, and step 307 is executed. Interrupt processing
Usually, it is performed at the time of return from interrupt processing in which the depth of the interrupt is shallow.

On the other hand, the ordinary microprocessor unitarily manages the return address data from the interrupt and the save destination of the PSW and the save and restore destinations of the register set in steps 302 and 307 in FIG. 3 by a set of stack pointers. ing. Further, the call of the normal subroutine and the return from the subroutine also use the stack pointer. The reason for this comes from the advantage that it is only necessary to secure one continuous stack area in the memory as described in the prior art.

Therefore, when the first embodiment is applied, if the save area of the register set is secured in the same stack area as the stack area for saving the return address data from the interrupt and the PSW, the order of saving and restoring will be out of order. ,
In some cases, a problem may occur in which consistency cannot be obtained. A method for avoiding this is to secure the save area of the register set independently of the execution destination address data upon return and the save area of the PSW, but it is necessary to secure the area of the required size independently for each. Is not desirable in terms of memory utilization efficiency.

Further, in the first embodiment, FIG.
In step 307, it cannot be determined which register has been saved. If all register sets are saved when all register sets are saved,
It is possible to unconditionally restore all register sets at the time of restoration, but unnecessary saving of registers directly causes a reduction in execution time. As a solution to this, it is possible to add the information of which register was saved last when the register set is saved, and to write the added information, so that the contents can be read first and the system can be restored based on the content. Further, by adding a dedicated instruction for performing the above-described processing to the microprocessor, the capacity and execution speed of the program can be improved. As a solution to the problems in the first embodiment, a second embodiment will be described below.

FIG. 5 is a block diagram showing a second embodiment of the microprocessor of the present invention.

The microprocessor according to the second embodiment has a mechanism for solving the problem in the first embodiment. Referring to FIG.
A PC storage unit 50 for storing address data of an execution program at the time of returning from an interrupt in the register set group 201
5 and PSW storage unit 506 for storing the PSW at the time of interruption
And a new storage processing unit 503 and a restoration processing unit 504
And have been added.

Next, the operation of the microprocessor of this embodiment will be described.

The storage processing unit 503 receives the INT signal 4 from the execution unit 200, and receives the INT signal 4 from the PC 501 as the program counter in the execution unit 200 and the PSW 502 as the PSW control register as the return information of the execution program at the time of occurrence of the interrupt. The data is read out and written to the PC storage unit 505 and the PSW storage unit 506 in the currently specified register set, respectively.

When the writing is completed, the interrupt control unit 2
2 and outputs a delayed INT signal 14 instead of the INT signal 1 in FIG. 2 to the register set selection unit 204 and the interrupt processing control unit 203. The reason for this is
This is because it is necessary to write the data of the PC 501 and the PSW 502 to the register set before switching the current register set.

Further, when the return processing unit 504 receives the IRET signal 5 at the time of return from the interrupt processing, the recovery processing unit 504 waits until the register set switching by the register set selection unit 204 is completed, and then the PC storage unit 505 and the PSW storage unit 506. And read the data from
Return to C501 and PSW502. When the return is completed, the execution unit 200 starts restarting the interrupted process.

For the effect of the present invention, the above-described PC storage unit 505 and PSW storage unit 506 do not necessarily need to be secured as dedicated registers, and can use a part of ordinary registers. .

That is, in the interrupt processing program that permits re-interruption and the processing unit that may be interrupted in the main program, the PC storage unit 505 and the P
It is only necessary that the register determined to be used as the SW storage unit 506 is not used. Otherwise, the PC storage unit 505 and the PSW storage unit 506
Is available as a normal register.

Here, the reason why the problem in the first embodiment is solved by the present embodiment will be additionally described.

The present embodiment is different from the first embodiment in that a re-execution address for returning from an interrupt and a PSW are stored in a register set without being stacked on a stack in a process when an interrupt occurs. Therefore, it is a feature that no explicit stack is used for interrupt processing unless an instruction that uses a stack such as a subprogram call is executed during processing of multiple interrupts. Therefore, the order of saving and restoring the stack on the stack even if step 302, which is the saving process of the register used, and step 307, which is the restoring process of the saved register in FIG. There is no contradiction because the relationship is always reversed.

As described above, the problem in the first embodiment can be solved by adding a new configuration.

[0073]

As described above, the present invention relates to a microprocessor having a plurality of register sets.
Interrupt processing control means for outputting, as interrupt processing control information, a signal indicating that the depth of multiple interrupts is equal to or greater than the number of register sets and a signal indicating that the depth of multiple interrupts is the minimum value This makes the interrupt response time when the depth of multiple interrupts is less than the number of register sets equal to that of the conventional example, and saves register sets when the depth of multiple interrupts exceeds the number of register sets. And minimize the return process,
This has the effect of minimizing the interrupt response time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a microprocessor of the present invention.

FIG. 2 is a circuit diagram showing a configuration of an interrupt processing control unit in the first embodiment of FIG.

FIG. 3 is a flowchart showing a typical example of an interrupt processing program.

FIG. 4 is a graph showing an example of a change in the depth of interruption in a time series.

FIG. 5 is a block diagram showing a second embodiment of the microprocessor of the present invention.

FIG. 6 is a block diagram showing a first example of a conventional microprocessor.

FIG. 7 is a block diagram illustrating a second example of a conventional microprocessor.

[Explanation of symbols]

Reference Signs List 1 interrupt request signal group 2 IE signal (interrupt enable signal) 3 interrupt vector signal 4 INT signal (interrupt signal) 5 IRET signal (return signal) 6 clock signal 7 reset signal 8 overflow signal 9 minimum value signal 10 register set designation signal REFERENCE SIGNS LIST 11 register input / output signal group 13 register set advance designation signal 14 delayed INT signal 100 counter 101, 103, 106 AND circuit 102, 104 NOT circuit 105 JKFF (JK flip-flop) 200 execution unit 201 register set group 202 interrupt control unit 203 Interrupt processing control unit 204, 205 Register set selecting unit 300 Interrupt processing start step 301 Overflow signal detection step 302 Register saving step used in interrupt processing unit 303 Interrupt Step of re-enabling an interrupt in the control unit 304 Main step of interrupt processing 305 Step of prohibiting interrupt 306 Step of detecting minimum value signal 307 Step of restoring saved register 308 Step of IRET (return instruction from interrupt) Step 501 PC (execution unit 200 502 PSW (PSW control register in the execution unit 200) 503 Save processing unit 504 Return processing unit a First interrupt position b Start position of an interrupt that becomes an interrupt with a depth equal to or greater than the number of register sets c Register set The start position of the interrupt that has a depth greater than or equal to d The re-interrupt position after d c The re-interrupt position after d f The return position from the interrupt of e g The return position from the interrupt of d h The number of register sets or more Start position of re-interruption at depth i Return position from the interrupt of j j return position from the interrupt of c c return position from the interrupt that restores the register saved at the interrupt of ke l return position from the interrupt that restores the register saved at the interrupt of l d mc From the interrupt that restores the registers saved at the time of the interrupt

Claims (2)

(57) [Claims] A plurality of register sets for controlling reception of an interrupt request in accordance with an interrupt enable signal, and providing said register with an interrupt signal indicating that the interrupt request has been received and a return signal indicating that the process has returned from interrupt processing. A microprocessor having an interrupt processing function of performing selection control of a set, a counting means for incrementing a count value by generation of the interrupt signal and decrementing the count value by generation of the return signal; Increment suppression means for suppressing the increment of the count value when the maximum value equal to the set number of the count value is reached; reduction count suppression means for suppressing the reduction of the count value when the count value reaches the minimum value; and the count value Is the maximum value, a signal indicating that an interrupt request has been accepted is output as control information for interrupt processing. And Bafuro notification unit, a microprocessor in which the count value is characterized in that it comprises an interruption processing control means comprising a minimum value notification unit for outputting a signal indicating that said the minimum value as the control information of the interrupt processing. 2. A storage processing means for storing address data and status data of a program executed before an interrupt when the interrupt signal is generated, in an area in the register set selected before the interrupt, and 2. The microprocessor according to claim 1, further comprising: return processing means for returning the address data and the status data from the area in the register set selected when a return signal is generated, and continuously executing the program.