JP2710777B2 - Test circuit for intermediate control unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a test circuit of an intermediate control device having a function of controlling an interface between a host computer and a terminal device, comprising: a test circuit for performing a test function of an external device;
Intermediate control having at least a control circuit for controlling whether data can be transmitted / received to / from an external device via an external interface with a view to providing a test circuit of an intermediate control device capable of testing all of the internal circuits An apparatus for temporarily storing a test pattern for a loopback test to be provided to the control circuit and a test pattern for an external test to be provided to an external device via the external interface; A return test and an external test read register for temporarily holding a response pattern from the control circuit to the test pattern and a response pattern from an external device input via an external interface, a normal use online mode and a test return test mode According to the selection of the external in A selection circuit for selecting an input signal from an external device input through the interface and a test pattern for the loopback test from the write register and providing the selected test pattern to the control circuit; and a normal use online mode and an external test mode for testing. According to your choice,
A first selection circuit for selecting a control signal from the control circuit and a test pattern for an external test from a write register and providing the selected test pattern to an external device via the external interface; and selecting a loopback test mode and an external test mode for the test A second selection circuit that selects a response pattern from the control circuit and a response pattern from an external device input through an external interface according to
A check means is provided for setting a test pattern for testing in the write register and reading the response pattern set in the read register and comparing it with an expected pattern.

[Industrial applications]

The present invention relates to a test circuit of an intermediate control device having a function of controlling an interface between a host computer and a terminal device.

Generally, as shown in FIG. 3 (a), the intermediate control device 1 is located between the host computer 2 and a plurality of terminal devices 3, and transmits data provided from the host computer 2 to one of the output terminal devices 3. Or a data multiplexer and a transmission / reception control to send data from any of the input terminal devices 3 to the host computer.

That is, as shown in FIG. 3B, the intermediate control device 1 has the MPU 11 therein,
A control circuit that controls whether data can be transmitted and received between the host computer 2 and the I / O controller 12 through the external device 0, sends a request signal to an external device, and receives a response signal to the request. And at least a control circuit for receiving a request signal for the request and sending a response signal to the request to an external device.

In order to improve the reliability of the whole system, it is necessary to check whether this intermediate control device operates correctly, and it is very important that the test be performed quickly and accurately on demand.

[Conventional technology]

Conventionally, in the test of the intermediate control device, a self-diagnosis method that has a test circuit that gives a test pattern to the control circuit in the device and outputs the response pattern, and compares the response pattern and the expected value pattern with the MPU in the device Was used.

FIG. 4 is a configuration diagram of a test circuit in a conventional intermediate control device. In the figure, the whole is a part of the channel controller 10 in the intermediate control device 1, 100 is a control circuit for controlling whether data can be transmitted and received, 101 is an external interface connected to an external host computer or I / O controller. With a driver / receiver inside, 102 is a return test write register that temporarily holds a test pattern for a return test given to the control circuit, and 103 is a return test that temporarily holds a response pattern from the control circuit 100 to the test pattern Read register, 104,
105 and 106 are selection circuits for switching the input signal input route to the control circuit 100 in accordance with the selection between the normal use online mode and the test loopback test mode.

When online, the online mode designation signal 1040 is “1” and the loopback test mode designation signal 1060 is “0”. Therefore, the control signal 1041 from the external device via the external interface 101 is transmitted via the AND gate 104 and the OR gate 105. The response signal input to the control circuit 100 and sent from the control circuit 100 is sent to an external device via the external interface 101 and is normally used. On the other hand, in the test mode, the online mode designating signal 1040 is “0” and the return test mode designating signal is
Since 1060 becomes “1”, the control signal 1041 from the external device is not gated to the output of the AND gate 104, and the test control signal 106 for the test pattern from the write register 102 is output.
1 is a control circuit 1 via an AND gate 106 and an OR gate 105
Input to 00. This test pattern is read from the internal memory under the control of the MPU 11 in the intermediate control device and set in the write register 102. A response pattern to the given test pattern is output from the control circuit 100, and an output control signal 1030 of the response pattern is set in the read register 103. Response pattern set is M
The signal is input to the PU 11, where it is compared with the expected pattern, and a test for the operation of the control circuit 100 is performed.

[Problems to be solved by the invention]

As described above, conventionally, the control circuit in the intermediate control device has been performed using only the test circuit that performs the self-diagnosis, so that the entire device cannot be tested. Host computer,
In addition, there is a problem that it is necessary to perform a test by connecting a terminal device. In addition, there is a possibility that a test circuit is configured to include a pseudo host circuit and a pseudo terminal circuit in the intermediate control device. However, there is a problem that a redundant circuit becomes large and the device becomes expensive.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a test circuit of an intermediate control device which has a test circuit for performing a test function of an external device and can test all internal circuits.

[Means for solving the problem]

FIG. 1A is a configuration diagram of the present invention. The present invention provides a control circuit 100 for controlling the transmission / reception of data, an intermediate control device having at least an external interface 101 connected to an external device, and a return test pattern to be given to the control circuit 100 and an external device via the external interface 101. A loopback test for temporarily holding a test pattern for an external test to be given and a write register for external test 102 '
And control circuit for test pattern for loopback test
A return test and an external test read register 103 ′ for temporarily holding a response pattern from the external device 101 and a response pattern input from the external device 101 via the external interface 101.
A control circuit for selecting an input signal from an external device to be input via the external interface 101 and a test pattern for a loopback test from the write register 102 'according to selection of a normal use online mode and a loopback test mode for testing; The control signal from the control circuit 100 and the write register 102 'are selected according to the selection circuit 15 applied to the control circuit 100 and the selection between the normal use online mode and the test external test mode.
A first selection circuit 13 for selecting a test pattern for an external test from the control circuit 100 and providing the same to an external device via an external interface 101; a response pattern from the control circuit 100 according to the selection of a test loopback test mode and an external test mode; A second selection circuit 14 for selecting a response pattern from an external device input via the external interface 101 and supplying the response pattern to the read register 103 ', and setting a test pattern for testing in the write register 102' and setting in the read register 103 ' There is a checking means 11 for comparing the read response pattern with the read expected pattern.

[Action]

According to the present invention, the internal loopback test function of the self-diagnosis function in the intermediate control device is converted into the control function of the external interface so that the test of the external connection portion including the external interface can be executed.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings. First
FIG. 2B is an embodiment diagram showing a configuration of a test circuit in the intermediate control device of the present invention. In the figure, the same components as those in FIGS. 1A and 4 are denoted by the same reference numerals.
The whole is a part of the channel controller 10 in the intermediate controller (1 in FIG. 3), 100 is a control circuit for controlling whether data can be transmitted and received, and 101 is an external circuit connected to an external host computer or I / O controller. An interface having an internal driver / receiver; 102 ', a loopback test for temporarily holding a loopback test pattern to be given to the control circuit 100 and an external test pattern to be given to an external device via the external interface 101; The test write register 103 'is a return register for temporarily storing the response pattern from the control circuit 100 to the return test pattern and the response pattern from the external device via the external interface 101, and the read register for external test is used, and 104, 105 and 106 are normally used. According to the choice of online mode and wrap test mode for testing A selection circuit for switching an input route for an input signal to the control circuit 100, 13
Is a first selection circuit for switching an input route for an input signal to the external interface 101 in accordance with a selection between a normal use online mode and an external test mode for testing, and 14 is a read circuit in accordance with the selection of a loopback test mode for testing and an external test mode. This is a second selection circuit for switching an input route for an input signal to the register 103 '.

At the time of online, since the online mode designating signal 1040 is “1” and the return test mode designating signal 1060 and the external test mode designating signal 1310 are both “0”, the control signal 1041 input from the external device via the external interface 101
Is the control circuit 10 via the AND gate 104 and the OR gate 105
The response signal input to 0 is sent from the control circuit 100 to the external device via the external interface 101, and is normally used.

On the other hand, in the test mode, the online mode designating signal 1040 is “0” and the loopback test mode designating signal 1060
Alternatively, one of the external test mode designating signals 1310 becomes “1”. Therefore, the control circuit 1041 from the external device does not gate the output of the AND gate 104. However, in the present invention, the control signal 1041 is supplied to the second selection circuit 14.
If the external test mode signal 1310 is "1", the signal state can be set in the read register 103 'via the OR gate 142. Also,
If the external test mode signal 1310 is “1”, the output signal 1061 from the write register 102 ′ gates the AND gate 131 in the first selection circuit 13 and is input to the external interface 101 via the OR gate 132. Therefore, the test pattern in the write register 102 'can be given to an external device via the external interface 101. Therefore, the MPU 11 in the intermediate control device gives a test pattern to the external device via the write register 102 ', and observes a response pattern input from the external device via the external interface 101 via the read register 103'. By comparing with the expected pattern, it is possible to check at least the normality of the driver and the receiver in the external interface 101.

Further, in the present invention, if the loopback test mode designating signal 1060 is "1" in the test mode, the write register
A test control signal 1061 of the test pattern from 102 ′ is input to the control circuit 100 via the AND gate 106 and the OR gate 105. This test pattern is the MP in the intermediate control unit.
The data is read from the internal memory under the control of U11 and is set in the write register 102 '. A response pattern from the control circuit 100 to the write pattern is a control signal 1030.
And input to the AND gate 140 of the second selection circuit. Since the loopback test mode designating signal 1060 is “1”, the logic state of the control signal 1030 is determined by the AND gate 140.
Is set in the read register 103 'via the OR gate 142. The set response pattern is input to the MPU 11, where it is compared with the expected pattern, and the normality of the operation of the control circuit 100 can be checked.

Thus, in the present invention, in particular, by setting the external test mode designating signal to "1", the test pattern from the write register 102 'can be given to the external device, and the response pattern can be input to the read register 103'. It is possible.

FIG. 2 is a configuration diagram showing an interface between the intermediate control device and an external device in the external test mode of the present invention.
In the figure, the same parts as those in FIG. 1 (b) are indicated by the same numbers. When the test pattern from the write register 102 'is given to an external device, an external test mode designation signal
By setting 1310 to “1”, the signal of the test pattern is input to the external interface 20 of the external device 2 ′ via the external interface 101 through the AND gate 131 and the OR gate 132. In the external device, if the online mode designation signal 24 is set to “1”, it is used normally, and the input signal is given to the control circuit 23 via the AND gate 21. The response signal from the control circuit 23 gates the AND gate 22 and is provided to the external interface 101 on the intermediate control device side via the external interface 20 and further to the read register 103 'via the AND gate 141 and the OR gate 142. It is read and checked by the MPU 11 in the device. Therefore, in the present invention, it is possible to check the normality of the route that is input from the output of the external interface 101 to the external interface 101 again via the external device by specifying the external test mode.

In the present invention, of course, the internal self-diagnosis function has an internal loopback test function. A control signal is set as a test pattern in the write register 102 'in the same operation sequence as that of the external interface, and the control circuit 100 is operated. The pattern is read into the read register 103 'and the MPU
At 11 you can also check the operation.

In the present invention, first and second selection circuits 13 and 14 for selecting a signal relating to the control function of the external interface are added to the loopback test circuit. Then, the write register 10 used for the external test as well as the loopback test
In 2 ', a control signal of an operation sequence to an external device is set as a test pattern via the external interface 101, and the response pattern is set in a read register 103' which is also used for an external test, and the MPU 11 reads it. To check the operation.

〔The invention's effect〕

Therefore, according to the present invention, even when the host computer and the terminal device do not have the test function, the internal circuit of the intermediate control device can substitute for the test function, and the test of the entire control device including the external connection portion is performed by a simple circuit. Moreover, it can be executed at high speed.

[Brief description of the drawings]

1 (a) is a block diagram of the present invention, FIG. 1 (b) is a block diagram of a test circuit in the intermediate control device of the present invention, and FIG. 2 is an interface between the intermediate control device of the present invention and an external device. FIG. 3 is a configuration diagram of a computer system, and FIG. 3 is a configuration diagram of a test circuit in a conventional intermediate control device. 11 ... checking means, 13 ... first selection circuit, 14 ... second selection circuit, 15 ... selection circuit, 100 ... control circuit, 101 ... external interface, 102 '... write register, 103 '... Read register.

Claims (3)

(57) [Claims] 1. A test data set by an internal test function of a self-diagnosis function in a control device is supplied to an external device, and the return data returned from the external device and the test data are subjected to a self-diagnosis of the control device. A control device for testing the external device by comparing the functions with an internal test function. 2. The internal test function includes a conversion unit for converting a write-back test register into a control signal of an external interface circuit, and a setting unit for setting a response signal of the external interface circuit in a read register for loop test. The control device according to claim 1, wherein: 3. An external interface (10) with an external device.
1) An intermediate control device having at least a control circuit (100) for controlling whether data can be transmitted and received via the external interface (101) and a loopback test pattern to be given to the control circuit (100). A return test and an external test write register (102 ') for temporarily holding a test pattern for an external test given to an external device; a response pattern from the control circuit (100) to the test pattern for the return test; 101), a return test and an external test read register (103 ') for temporarily holding a response pattern from an external device input through the external interface (101') according to the selection between a normal use online mode and a test return test mode. 101) and an input signal from an external device through the light register. The control circuit (15) selects a test pattern for the loopback test from the master (102 ') and supplies it to the control circuit (100), and the control circuit (15) selects the normal use online mode and the external test mode for testing. A first selection circuit (1) which selects a control signal from the circuit (100) and a test pattern for an external test from the write register (102 ') and supplies the same to an external device via the external interface (101).
3) selecting a response pattern from the control circuit (100) and a response pattern from an external device input via an external interface (101) according to selection of a loopback test mode for test and an external test mode; (Ten
3 ') and a test pattern for testing in the write register (102'), and a response pattern set in the read register (103 ') is read and compared with an expected pattern. A test circuit for an intermediate control device, characterized by having a check means (11).