JP2709102B2 - Optical information reproducing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical information reproducing apparatus for simultaneously reproducing information from a plurality of recording areas on a recording medium.

[Conventional technology]

When reproducing information from a recording medium that records or reproduces information using light from an optical disk, optical card, or the like, a method of irradiating a single track with a single light emitted from an optical head and scanning the same is known. Generally known. However, in this method, the light scans the track according to the relative speed between the optical head and the recording medium. Then, the optical information obtained by reflection or transmission from the recording medium is sequentially converted into an electric signal to obtain information. Therefore, the information reading speed is determined by the relative speed between the optical head and the recording medium,
You can't go any faster.

Therefore, US Pat. No. 4,730,293 discloses a technique for simultaneously irradiating a plurality of tracks with light. It is described that the reading speed can be quadrupled by simultaneously irradiating a plurality of tracks with light and reading them out.

However, US Pat. No. 4,730,293 does not describe how to process light obtained from a recording medium to obtain recorded information as a signal.

[Problems to be solved by the invention]

The applicant has devised a data processing system shown in FIG. Here, a case is shown in which track n and track n + 1 are simultaneously irradiated with light and read.

In FIG. 7, light obtained by irradiating the track n is converted into an electric signal via the photoelectric conversion detecting element 11. The electric signal passes through an amplifier 12 and is converted into a binary signal by a binarizing circuit 13. After that, the phase comparator 14VFO (variable fr
equency oscillator) circuit 15. FIG. 7 shows a data processing system in the case where information is recorded by a modulation method using a self-clock. A phase comparator 14 and a VFO circuit 15 constitute a PLL (phase-locked loop) circuit. I have. The electric signal that has passed through the PLL circuit is demodulated by a data demodulator 16 to obtain a data demodulated signal 17.

On the other hand, the light obtained by irradiating the track n + 1 is also the same as the light obtained by irradiating the track n, and the photoelectric conversion detecting elements 21,
A data demodulation signal 27 is obtained via an amplifier 22, a binarization circuit 23, a phase comparator 24, a VFO circuit 25, and a data demodulator 26.

The obtained data demodulated signals 17, 27 are sequentially selected by a controller (not shown) for controlling the entire apparatus and reproduced as information.

However, when processing data in accordance with this data processing system, a data processing system corresponding to the number of tracks that are simultaneously irradiated with light and read is required. FIG. 7 shows that two data processing systems formed by the data demodulators 16 and 26 from the photoelectric conversion detecting elements 11 and 21 are used to read the two tracks n and n + 1.

Therefore, when the data processing system according to FIG. 7 is used, there arises a problem that the scale of the circuit is increased and the cost is increased. Further, since there are a plurality of circuit systems and processing is performed by many elements, there is a possibility that the reliability of data may be reduced.

[Means and actions for solving the problem]

The present invention is directed to an apparatus for reproducing information by simultaneously irradiating light to a plurality of recording areas on an optical card and relatively reciprocating the optical card and the light. Photoelectric conversion means for converting light into a plurality of electric signal strings as information of each recording area, storage means for storing at least one of the plurality of converted electric signal strings, and the photoelectric conversion means or the storage means Performing the reproduction process of the output signal, signal processing means less than the number of the electric signal sequence, and a selection means for selectively outputting the output signal of the photoelectric conversion means or the storage means to the signal processing means, The reproduction processing operation of the signal processing means is performed during a period in which the movement of the optical card and the light decelerates and stops.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1 to 3 show a first embodiment of the present invention. Also in the first embodiment, the track n and the track n
The case where light is simultaneously irradiated to +1 will be described.

The light obtained by irradiating the track n is the photoelectric conversion detecting element 31.
Is converted into an electric signal. This electric signal is converted into a binary signal by a binarizing circuit 33 after passing through an amplifier 32,
To enter.

A selector 34 receives a select signal 34a from a controller (not shown), and the data of the track n is first sent to the phase comparator 35 by the select 34a. And
After passing through a PLL circuit composed of the phase comparator 35 and the VFO circuit 36, the data passes through a data demodulator 37 to obtain a data demodulated signal of the track n.

On the other hand, the light obtained by irradiating the track n + 1 is converted into an electric signal by the photoelectric conversion detecting element 41, and is converted into a binary signal by the binarizing circuit 43 after passing through the amplifier. So far,
It proceeds simultaneously with the data processing of track n. Then, the data of the track n + 1 passes through the binarization circuit 43 and is then input to the memory unit 44 and stored. A reset signal 44a and an R / W (read / write) switching signal 44b from the controller are input to the memory unit 44, and the track n +
1 is generated.

FIG. 2 shows a configuration example of the memory unit 44. The memory unit 44 includes a clock module 441, a counter 442, and a semiconductor memory 443.

When storing the binary signal from the binarization circuit 43 in the semiconductor memory 443, the R / W switching signal 44b specified by the controller is set to the write state, and the counter 442 is reset by the reset signal 44a. The counter 442 is counted up by the clock signal from the clock module 441, and the output is input to the semiconductor memory 443 via the address bus as the address of the semiconductor memory 443. On the other hand, a write pulse which is an AND output of the clock signal from the clock module 441 and the R / W switching signal 44b is input to the semiconductor memory 443. This write pulse is synchronized with the setting of the address. Binarization circuit 43-2
The value output, that is, the data of track n + 1, follows the write pulse, and 1bi is set to the set address in the semiconductor memory 443.
It is memorized by t. When the writing of data to the semiconductor memory 443 is completed, the R / W switching signal 44b is set to the read state. For example, when a card-shaped optical recording medium is used, if the storage capacity of one track is 1 Mbit, the same binary information as that of the recording on the optical card is stored. Therefore, a 1-Mbit semiconductor memory may be used. .

While the data of track n + 1 is stored in the semiconductor memory 443, the data demodulator 37 outputs a data demodulated signal of track n. After the data of the track n is output, the data of the track n + 1 is selected to be demodulated by the select signal 34a, and the data stored in the semiconductor memory 443 is read. When reading, the R / M switch signal is in the read state from the end of writing and the counter
442 is counted up after being reset by the reset signal 44a, and when the address is incremented, the track n + 1 corresponding thereto is read. Semiconductor memory
Writing to 443 and reading from semiconductor memory 443
Although shown in the drawings as being performed with the same terminal, the processing may be performed with a semiconductor memory having different terminals. The read data is obtained as a data demodulated signal of track n + 1 via the selector 34, the phase comparator 35, the VFO circuit 36, and the data demodulator 37.

FIG. 3 is a diagram showing the timing of storing data in the semiconductor memory 443. A is an output signal from the photoelectric conversion detecting element, and B is a signal obtained by binarizing A. For the track n, demodulation is performed from the binary signal B. C
Is an enlarged view of B in the time axis direction for easy viewing,
In the case of the data of the track n + 1, C is stored at the timing of the write pulse D. Therefore, the semiconductor memory 44
3 stores the waveform of E. As shown in FIG. 3E,
x and y are sampling errors when stored in the semiconductor memory 443. In general, in recording / reproducing by light or recording / reproducing by magnetism, when fluctuation occurs in the time axis direction, it causes jitter. The sampling error xy occurring here can be similarly considered as jitter. If the jitter amount due to this sampling can be suppressed to about 5%, there is no significant effect on data reproduction. Thus, for example, in the case of an optical card, the read speed is about 10 kbit / sec to 100 kbit / sec, so if the frequency of the write pulse is set to about 500 KHz to 5 MHz, the jitter amount can be suppressed to about 5%. .

As described above, in the first embodiment, the memory section is provided,
By using a single data demodulation circuit composed of a PLL circuit and a data demodulator, data can be read out by simultaneously irradiating a plurality of tracks with light with a miniaturized circuit configuration.

In this embodiment, the case where two tracks are simultaneously irradiated with light to read data is described. However, even if the number of tracks from which data is read by simultaneously irradiating light is further increased, the data is read in the same manner as in this embodiment. The demodulation circuit can be one system. Hereinafter, also in the second and third embodiments, the first embodiment
Similar to the embodiment, a case where two tracks are irradiated with light will be described. However, even if the number of tracks increases, the same applies.
Of course, it can be configured.

Next, a second embodiment of the present invention will be described with reference to FIGS. The same parts as those in FIG. 1 of the first embodiment are denoted by the same reference numerals, and the details are omitted. The differences from the first embodiment are:
In the first embodiment, the speed of writing to and reading from the semiconductor memory is the same, whereas in the second embodiment, the reading speed is faster than the writing speed. Therefore, in the memory section 54, as shown in FIG. 5, the R / W switching signal 54b is set to a write state at the time of writing, and the selector 544 selects the clock signal of the clock module 541a by the signal in the write state. In accordance with a clock signal from the clock signal of the clock module 541a, the counter 542 is counted up, and an address of the semiconductor memory 543 is set and a write pulse is generated at the same time. On the other hand, at the time of reading, the R / W switching signal 54b is set to the reading state, and the selector 544 uses the clock module 541 as the reading state signal.
Select the clock signal of b. Clock module 541b
Thereafter, a clock signal having a frequency which is m times as high as that of the clock signal from the clock module 541a at the time of writing is generated. Here, two types of clock modules are selected, but it is also possible to select whether or not to use a counter by using only one and dividing the frequency by m using a counter. The read speed of the data on track n is determined by the relative movement between the optical head and the recording medium. For track n + 1, the read speed can be increased up to the maximum read frequency determined by the semiconductor memory 543. In the present embodiment, the data signal of the track n. + 1 read from the memory unit 54 has a frequency which is m times the frequency of the data signal of the track n based on the clock signal from the clock module 541b. Accordingly, the synchronization frequency of the PLL circuit including the phase comparator 55 and the VFO circuit 56 is switched in time constant by giving the command signal 55a, and when demodulating the data of the track n + 1, the time constant of demodulating the data of the track n is changed. Double and synchronize. The data signal of track n + 1 that has passed through the PLL circuit whose synchronization frequency has been multiplied by m is demodulated by the data demodulator 37 at a speed that is m times faster than that of track n.

Here, the PLL circuit switches the synchronization frequency by switching the time constant. However, there is also a method of digitally adjusting the phase and frequency. In this case, the target frequency may be switched.

With the configuration described above, the speed of reading information can be further increased.

Also, taking an optical card as an example, there is a method of reading information by reciprocating a recording medium. In this case, when reversing the direction of movement of the recording medium, deceleration / stop operations are always performed. During this time, information cannot be read from the track. If the information stored in the semiconductor memory is demodulated during this time, the efficiency of the read operation is further improved.

Next, a third embodiment of the present invention will be described with reference to FIG.
The same parts as those in FIG. 1 of the first embodiment are denoted by the same reference numerals, and the details are omitted.

A feature of the third embodiment is that data of a track that does not pass through the memory unit 44 can be selected.

To implement this, the data of track n and track n + 1 that have passed through the binarization circuits 33 and 43 are stored in the first selector 64.
To enter. The first selector 64 outputs a first select signal 64
a, the data to be sent to the second selector 65 and the memory 44
Select the data to send to. For example, a path indicated by a broken line in the figure in which the data of track n is input to the second selector 65 and the data of track n + 1 is input to the memory unit 44, and the data of track n is input to the memory unit 44, The path of the double line in the figure for inputting data to the second selector 65 is selected by the first select signal 64a. The second selector 65 selects the data sent from the first selector 64 and the data to be read from the memory unit 44 by the second select signal 65a, similarly to the selector 34 in the first embodiment. Note that the method of storing data in the memory unit 44, the PLL circuit after the second selector 65, and the demodulation circuit (not shown) are the same as those in the first embodiment, and therefore description thereof is omitted.
As described above, it is possible to select, from among the information to be read from the track, information on a track that passes through the memory unit and information on a track that does not pass through the memory unit. If there is a case where the track to be read first is determined among the tracks, the data of that track can be demodulated by selection without going through the memory unit, so that the data can be demodulated first. Further, since the information does not pass through the memory unit, this information does not include jitter due to sampling.

Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, in the embodiment, data of a certain track is always demodulated without passing through the storage means. However, data of all tracks is stored in the shared storage means, and then demodulated by one system of demodulation circuit. It may be. Further, in USPAT. No. 4730293 cited as a prior art, a single light beam irradiates a plurality of tracks, but this may be applied to the present invention as it is, or a plurality of tracks may be applied by a plurality of beams. Irradiation may be performed. Further, in the embodiment, the case where a plurality of tracks are irradiated with a light beam at the same time according to USPAT.4730293 has been described.However, when a plurality of sectors exist on the same track, each sector is irradiated with light at the same time. The present invention can be applied to the case of reproducing information.

〔The invention's effect〕

As described above, according to the present invention, at least one row of the electric signals obtained corresponding to the plurality of recording areas is stored, so that the number of the signal processing means is reduced by reading out from the storage means at a desired time. As a result, the cost of the apparatus can be reduced. Further, since the reproduction processing operation of the signal processing means is performed during a period in which the movement between the optical card and the light is decelerated and stopped, the efficiency of the reproduction operation can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention, FIG. 2 is a block diagram showing a configuration example of a memory unit used in FIG. 1, and FIG. 3 is an operation timing in the memory unit of FIG. FIGS. 4 and 5 are block diagrams showing the configuration of a second embodiment of the present invention, FIG. 6 is a block diagram showing the configuration of a third embodiment of the present invention, and FIG. It is a block diagram which performs information reproduction thought by a person. 44,54 …… Memory part, 34,64,65,544 …… Selector, 441,5
41a, 541b: Clock module, 442, 542: Counter, 443, 543: Semiconductor memory.

Claims (1)

(57) [Claims] An apparatus for reproducing information by simultaneously irradiating a plurality of recording areas on an optical card with light and relatively reciprocating the optical card and the light, comprising: Photoelectric conversion means for converting the return light into a plurality of electric signal strings as information of each recording area; storage means for storing at least one of the plurality of converted electric signal strings; and the photoelectric conversion means or the storage means A signal processing unit for performing a reproduction process of the output signal of the number of the electric signal trains, and a selection unit for selectively outputting an output signal of the photoelectric conversion unit or the storage unit to the signal processing unit. An optical information reproducing apparatus, wherein a reproduction processing operation of the signal processing means is performed during a period in which the movement of the optical card and the light decelerates and stops.