JP2707157B2 - Display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active display device, and more particularly to an active liquid crystal display device. Two P-channel and N-channel thin-film insulated gate field effect transistors are complementary to each pixel. (Hereinafter referred to as TFT) and a display device having pixels.

[0002]

2. Description of the Related Art Conventionally, an effective display device has been
2. Description of the Related Art An active liquid crystal display device using an FT is known. In this case, a semiconductor having an amorphous or polycrystalline structure is used for the TFT, and a TFT having only one of the P and N conductivity types is used for one pixel. That is, generally, an N-channel TFT (referred to as NTFT) is connected in series to the pixel. FIG. 6 shows a typical example.

In general, an active matrix type liquid crystal display device has a very large number of pixels of 480 × 640 or 1260 × 960. FIG. 6 shows the same meaning as above, and is shown in a 2 × 2 matrix arrangement for simplicity of explanation. A plurality of gate lines G ₁ , G ₂ and a plurality of signal lines D ₁ , D ₂ are arranged orthogonally, and a pixel display element is provided at the intersection of the matrix. This pixel display element includes a liquid crystal unit 102 and a TFT unit 101. Peripheral circuits 106 and 107 for each pixel
And a predetermined pixel is selectively turned on or off to perform display.

However, when these liquid crystal display devices are actually manufactured and displayed, the output of the TFT, that is, the voltage _VLC 100 of the input to the liquid crystal (referred to as the liquid crystal potential) is:
Often, when “1” (High) should be “1” (H
i), and conversely, when it should be “0” (Low), it does not become “0” (Low). This occurs because there is no symmetry in the characteristics of the switching element that applies a signal to the pixel, that is, the TFT. In other words, this is because the state of charge and the state of discharge to the pixel electrode have a difference in electrical characteristics. The liquid crystal 102 is inherently insulative in its operation, and the liquid crystal potential (V _LC ) floats when the TFT is off. Since the liquid crystal 102 is equivalently a capacitor, _VLC is determined by the electric charge stored therein. This charge is a relatively small resistance in the _RLC of the liquid crystal, leaks due to the presence of dust or ionic impurities, and when the _RGS 105 is generated by a pinhole in the gate insulating film of the TFT, the charge is generated therefrom. Leakage occurs, and _VLC is in an incomplete state. For this reason, a liquid crystal display device having 200,000 to 5,000,000 pixels in one panel has a problem that a high yield cannot be achieved.

As the liquid crystal 102, a TN (twisted nematic) liquid crystal is generally used. A rubbed alignment film is provided on each electrode to align the liquid crystal.
A weak dielectric breakdown occurs due to static electricity generated by the rubbing process, and leakage occurs between adjacent pixels or adjacent conductors, or the gate insulating film is weak and leaks.

[0006]

In an active type liquid crystal display device, it is extremely important that the liquid crystal potential is constantly set to the same value as the initial value for one frame to maintain a predetermined level. However, in practice, there are many malfunctions of the active element, and in reality, the liquid crystal potential cannot always be kept at the same level as the initial value and maintained at a predetermined level during one frame.

[0007] The present invention solves the above-mentioned problems and increases the current margin, that is, increases the response speed. Further, the potential of the pixel in each pixel, that is, the liquid crystal potential V _LC
Are fixed to "1" and "0" with sufficient stability so that the level does not drift during one frame.

[0008]

According to the present invention, a pair of first and second signal lines are arranged in a matrix in an X direction, and a third signal line is arranged in a matrix in a Y direction. In a display device provided with a complementary thin film transistor and a pixel electrode, a source (drain) portion of an N-channel thin film transistor connected to a first pixel is connected to a first signal of a pair of signal lines in an X direction. And a source (drain) portion of a P-channel thin film transistor connected to the first pixel is connected to a second signal line of a pair of signal lines in the X direction, and is adjacent to the first pixel. The source (drain) portion of the P-channel thin film transistor connected to the second pixel connected to the same third signal line is connected to the second signal line of another pair of signal lines in the X direction. And the P-ch of the first pixel Display device, characterized in that provided next to each other and the second signal line second signal line and the P-channel thin film transistor of the second pixel that channel thin film transistor is connected is connected.

That is, the complementary structure is characterized in that a signal line to a thin film transistor connected to a pixel has the same function between adjacent pixels and is provided in the vicinity thereof. In other words, between adjacent pixels, for example, an NTFT signal line or a PTFT signal line is provided adjacent to each other.

As a configuration of a display device to which the present invention can be applied, one pixel may be configured by connecting two or more C / TFTs to one pixel. One more
One pixel may be divided into two or more, and one or more C / TFTs may be connected to each.

With such a configuration, when the C / TFT connected to the pixel is actually driven, the PTFT and the NTFT overlap, and when a signal of the input is applied, V _{DD is} doubled at the maximum. ( _VSS ) voltage is applied between the signal lines, so that no leak occurs between the signal lines, and the signal lines that have become identical have the same function (signal lines to NTFT or signal lines to PTFT). ), Only about V _DD ( _VSS ) is applied between the signal lines. Therefore, there is little leakage in this part.

A typical example of the structure of a display device to which the present invention can be applied is shown as a circuit diagram in FIGS. FIGS. 7, 8, and 9 show examples of actual pattern layouts (arrangement diagrams), respectively. For simplicity,
Here, a 2 × 2 matrix configuration will be described as an example. In the example of the 2 × 2 matrix shown in FIG.
And the gate of the PTFT are connected to each other, further connected to the third signal line 3 or 4 in the Y-axis direction, and the common output terminal of the C / TFT is connected to the liquid crystal 15. The input terminal (10 side) of the NTFT is connected to the first signal line 5 or 7 of the pair of signal lines in the X-axis direction, and the input terminal (20
Side) is the second signal line 8 of the pair of signal lines in the X-axis direction.
Or it is connected to 6.

In such a configuration, as shown in FIG. 2, the third signal is applied during the period in which the ON signal waveform is applied between the pair of the first signal line 5 and the second signal line 8. When an ON signal waveform is applied to the line 3, the liquid crystal potential (V _LC )
14 is the voltage V _GG -Vth applied to the first signal line. Further, the third signal line 3 is supplied during a period in which the off signal waveform is applied between the pair of the first signal line 5 and the second signal line 8.
When a signal waveform of OFF is applied, the liquid crystal potential (V _LC )
14 has no potential. Further, when the ON signal waveform is not applied to the third signal line 3 during the period when the ON signal waveform is applied between the pair of the first signal line 5 and the second signal line 8, the liquid crystal potential (V _LC ) 14 similarly has no potential. As described above, the liquid crystal potential (V _LC ) 14 is given according to the voltage applied to the third signal line, and the potential difference applied to the liquid crystal can be arbitrarily changed by changing the voltage of the signal applied to this signal line. Can be.

The counter electrode 16 has an offset voltage V
_OFFSET is applied, and the voltage actually applied to the liquid crystal 15 is V _GG + V _OFFSET −Vth or V
_{It is} a binary value of _OFFSET . In the driving method of the present invention, the on / off of the liquid crystal driving can be arbitrarily changed by changing the offset voltage V _OFFSET applied to the counter electrode. Further, since the threshold value for actually driving the liquid crystal differs depending on the liquid crystal material, it is possible to adjust the threshold value only by changing the offset voltage V _OFFSET in order to match the value of the liquid crystal. it can.

Further, the C / TFT of the adjacent pixel connected to the common third signal line during a period in which the ON signal waveform is applied between the pair of the first signal line 5 and the second signal line 8. If the oFF signal is applied to the first and second signal lines of the pair as well to, between the signal line 8 and the signal line 6 is not only applied potential difference V _SS, and half of the potential difference in the case of normal Become. Therefore, the leak between the signal lines is reduced, and if the same degree of leak can be tolerated, the interval between the signal lines can be reduced to just half.

In the example shown in FIG. 3, the third signal line 3 in the Y direction shares the four gate electrodes of the NTFT 13 PTFT 22 forming the first C / TFT and the NTFT 24 and PTFT 25 forming the second C / TFT. To N
The input terminals of the TFT 13 and the NTFT 24 are made common, and the input terminals of the PTFT 22 and PTFT 25 are made common and connected to the first signal line 5 in the X direction. The output of the two C / TFTs is made common and one liquid crystal 1
5 is connected to the pixel electrode 17 which is one electrode.
Thus, even if either one of the two NTFTs or the two PTFTs leaks to some extent, the pixels can be driven because they have the same phase.

FIG. 5 shows that, in one pixel 23, two pixel electrodes 17, 26 and their corresponding C / T
In this example, two FTs are provided. The gate electrode of the two C / TFTs is made common, and the first input is performed. The input of each NTFT and each PTFT of each C / TFT is connected to a first signal line 5 and a second signal line 8. Thus, one of the two pixels in one pixel does not become inoperable due to a defect such as a TFT leak. In addition, even if the operation is delayed, the other operates normally, so that the defect is less noticeable in the matrix configuration operation.

[0018]

[Embodiment 1] This embodiment will be described using a liquid crystal display device having a circuit configuration as shown in FIG. FIG. 7 shows an actual arrangement of electrodes and the like corresponding to this circuit configuration.
For simplification of description, only portions corresponding to 2 × 2 are described.

First, a method for manufacturing a liquid crystal display device used in this embodiment will be described with reference to FIGS. In FIG. 10A, a silicon oxide film as a blocking layer 51 is formed on a glass 50 that can withstand a heat treatment at an inexpensive temperature of 700 ° C. or less, for example, about 600 ° C. by using a magnetron RF (high frequency) sputtering method. It is made to a thickness of 3000 mm. The process conditions are 100% oxygen atmosphere, film formation temperature 15 ° C., output 400 to 800 W, pressure 0.5 Pa.
And The deposition rate using quartz or single crystal silicon as the target was 30 to 100 ° / min.

A silicon film was formed thereon by an LPCVD (low pressure gas phase) method, a sputtering method or a plasma CVD method. When formed by the reduced pressure gas phase method, the temperature is 1
450-550 ° C lower by 00-200 ° C, for example 530 ° C
With disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H
₈ ) was supplied to a CVD apparatus to form a film. The pressure in the reactor was 30 to 300 Pa. The deposition rate is 50-250 ° /
Minutes. In order to control the threshold voltage (Vth) of the NTFT and PTFT to be substantially the same, boron is used to diborane to 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ^−3.
May be added during the film formation.

When the sputtering is performed, the back pressure before the sputtering is set to 1 × 10 ⁻⁵ Pa or less, and the single crystal silicon is used as a target in an atmosphere containing 20 to 80% of hydrogen mixed with argon. For example, argon 20%, hydrogen 8
0%. The film forming temperature is 150 ° C. and the frequency is 13.56.
MHz, sputter output 400-800W, pressure 0.
It was 5 Pa.

When a silicon film is formed by a plasma CVD method, the temperature is set to, for example, 300 ° C., and monosilane (S
iH ₄ ) or disilane (Si ₂ H ₆ ) was used. These were introduced into a PCVD apparatus, and a high-frequency power of 13.56 MHz was applied to form a film.

The coatings formed by these methods are:
It is preferable that oxygen is 5 × 10 ²¹ cm ⁻³ or less. If the oxygen concentration is high, crystallization is difficult, and the thermal annealing temperature must be increased or the thermal annealing time must be increased. If the amount is too small, the leakage current in the off state increases due to the backlight. Therefore 4 × 10
The range was ¹⁹ to 4 × 10 ²¹ cm ⁻³ . Hydrogen is 4x
10 ²⁰ cm ⁻³ and silicon 4 × 10 ²² cm
As compared with ⁻³ , it was 1 atomic%. In order to promote crystallization of the source and the drain, the oxygen concentration is set to 7 × 10 ¹⁹ cm ⁻³ or less, preferably 1 × 1 ¹⁹ cm ⁻³ or less.
0 ¹⁹ cm ⁻³ or less, and oxygen is ion-implanted into the channel forming region of the TFT forming the pixel at 5 × 1
You may add so that it may become 0 < ²⁰ > -5 * 10 < ²¹ > cm < ^-3 >. At this time, since light is not irradiated to the TFTs constituting the peripheral circuit, it is effective to reduce the mixing of oxygen and to have a higher carrier mobility for high-frequency operation.

Next, the amorphous silicon film is
After being formed to a thickness of 00 to 5000 °, for example, 1500 °, heat treatment is performed at a temperature of 450 to 700 ° C for 12 to 70 hours in a non-oxide atmosphere at a medium temperature, for example, at a temperature of 600 ° C in a hydrogen atmosphere. . Since a silicon oxide film having an amorphous structure is formed on the surface of the substrate below the silicon film, no specific nucleus is present in this heat treatment, and the whole is uniformly heat-annealed. That is, it has an amorphous structure at the time of film formation, and hydrogen is simply mixed therein.

By the annealing, the silicon film shifts from an amorphous structure to a highly ordered state, and a part of the silicon film exhibits a crystalline state. In particular, a region having a relatively high order in a state after the formation of silicon is particularly likely to be crystallized to be in a crystalline state.
However, since the silicon existing between these regions is bonded to each other, the silicon mutually pulls each other. When measured by laser Raman spectroscopy, a peak shifted from the single crystal silicon peak 522 cm ^-1 to a lower frequency side is observed. Calculated from its half-width, the apparent particle size is 50 to 500 °, which is like a microcrystal. However, in fact, there are many regions with high crystallinity and a cluster structure. A film having a semi-amorphous structure bonded (anchored) by silicon was formed.

As a result, the coating exhibits a state substantially free of grain boundaries (hereinafter referred to as GB). Carriers can easily move from one cluster to another through the anchored locations between the clusters, so-called GB
Carrier mobility higher than that of polycrystalline silicon that clearly exists. That is, hole mobility (μh) = 10 to 200
cm ² / VSec, electron mobility (μe) = 15 to 300
cm ² / VSec is obtained.

On the other hand, when the film is polycrystallized by high-temperature annealing at 900 to 1200 ° C. instead of annealing at the above-mentioned medium temperature, segregation of impurities in the film occurs due to solid phase growth from nuclei, and GB Impurities such as oxygen, carbon, and nitrogen increase, and the mobility in the crystal is large. However, a barrier (barrier) is formed in GB to hinder the movement of carriers there. As a result, a mobility of 10 cm ² / Vsec or more cannot be easily obtained. That is, in this embodiment, a silicon semiconductor having a semi-amorphous or semi-crystalline structure is used for such a reason.

In FIG. 10A, a silicon film is firstly formed.
Photo-etching with a photo mask of PTF
A region 22 for T (channel width 20 μm) was formed on the right side of the drawing, and a region 13 for NTFT was formed on the left side.

On this, a silicon oxide film was formed as a gate insulating film to a thickness of 500 to 2000 {for example, 1000}. This was made under the same conditions as those for forming the silicon oxide film as the blocking layer. During the film formation, a small amount of fluorine may be added to fix the sodium ions.

Thereafter, 1 to 5 × 10
A silicon film having a concentration of ²¹ cm ⁻³ or a multilayer film of the silicon film and molybdenum (Mo), tungsten (W), MoSi ₂ or WSi ₂ was formed thereon. This was patterned using a second photomask to obtain FIG. Gate electrode 21 for PTFT, N
A gate electrode 9 for a TFT was formed. For example, a channel length is 10 μm, and phosphorus-doped silicon is used as a gate electrode in 0.1 μm.
2 μm, and molybdenum was formed thereon with a thickness of 0.3 μm. In FIG. 10C, a photoresist 57 is formed using a photomask, and a PTFT source 18 is formed.
1-5 × 10 ¹⁵ cm of boron is applied to the drain 20.
A dose of ^-2 was added by ion implantation. Next, as shown in FIG. 10D, a photoresist 61 was formed using a photomask. Phosphorus was added as a source 10 and a drain 12 for NTFT by an ion implantation method at a dose of 1 to 5 × 10 ¹⁵ cm ⁻² .

These operations were performed through the gate insulating film 54. However, in FIG. 10B, the gate electrode 21,
9 may be used as a mask to remove silicon oxide on the silicon film, and then boron and phosphorus may be directly ion-implanted into the silicon film.

Next, heat annealing was performed again at 600 ° C. for 10 to 50 hours. The source 18 and the drain 20 of the PTFT and the source 10 and the drain 12 of the NTFT were activated to form P ⁺ and N ⁺ by activating impurities. Channel formation regions 19 and 11 are formed below the gate electrodes 21 and 9 as semi-amorphous semiconductors.

In this way, a C / TFT can be manufactured without applying a temperature to 700 ° C. or more in all steps, even though it is a self-aligned system. Therefore, it is not necessary to use an expensive substrate such as quartz as a substrate material, and this is a process very suitable for the large pixel liquid crystal display device of the present invention.

In this embodiment, the thermal annealing is performed as shown in FIG.
(D) was performed twice. However, the annealing in FIG. 10A may be omitted depending on the required characteristics, and both may be combined by the annealing in FIG. 10D to shorten the manufacturing time. Figure 1
In FIG. 1A , an interlayer insulator 65 was formed as a silicon oxide film by the sputtering method described above. This silicon oxide film is formed by an LPCVD method, a photo CVD method, a normal pressure CVD method.
Method may be used. For example, it is formed to a thickness of 0.2 to 0.6 μm, and thereafter, a window 6 for an electrode is formed using a photomask.
6 was formed. Further, aluminum is formed on the entire surface by sputtering, and leads 71 and 72 and contacts 67 and 68 are formed using a photomask.
The surface was coated with a flattening organic resin 69, for example, a translucent polyimide resin, and the electrode drilling was performed again using a photomask.

[0035] Two TFT as shown in FIG. 11 (B) and complementary configuration, and for connecting thereto the output electrodes of one pixel of a liquid crystal device as a transparent electrode, ITO (indium-by sputtering (A tin oxide film). It is etched using a photomask and the electrode 1
7 was constructed. This ITO film was formed at room temperature to 150 ° C. and achieved by annealing at 200 to 400 ° C. in oxygen or atmosphere. Thus, PTFT 22 and NTF
T13 and the transparent conductive electrode 17 are made of the same glass substrate 50.
Made above. The electrical characteristics of the obtained TFT are PTF
At T, the mobility is 20 (cm ² / Vs), and Vth is −5.9.
(V), the mobility of NTFT is 40 (cm ² / Vs),
Vth was 5.0 (V).

A transparent electrode is provided on the entire surface of one of the substrates for the liquid crystal device and the other glass substrate manufactured according to the method described above, and these substrates are laminated to form a liquid crystal cell.
A TN liquid crystal material was injected therein. FIG. 7 shows the arrangement of the electrodes and the like of the liquid crystal display device. NTFT1
3 is provided at the intersection of the first signal line 5 and the third signal line 3, and the NTFTs for other pixels are similarly provided at the intersection of the first signal line 5 and the third signal line 4. Is provided. On the other hand PT
The FT is provided at the intersection of the second signal line 8 and the third signal line 3. A PTFT for another pixel is provided at the intersection of the adjacent first signal line 6 and third signal line 3, and similarly, the first signal line 6 is connected to the third signal line 3. PTFTs are provided at intersections with the signal lines 4. A matrix configuration using such a C / TFT is provided.
The NTFT 13 is connected to the first signal line 5 via a contact at the input end of the drain 10, and the gate 9 is connected to the signal line 3 on which a multilayer wiring is formed. The output terminal of the source 12 is connected to the pixel electrode 17 via a contact.

On the other hand, the PTFT 22 has an input terminal of the drain 20 connected to the second signal line 8 via a contact, a gate 21 connected to the signal line 3, and an output terminal of the source 18 connected to the pixel via a contact like the NTFT. It is connected to the electrode 17. Further, in the C / TFT connected to the same third signal line and provided next to it, the PTFT 22 is connected to the second signal line 6 and the NTFT 13 is connected to the first signal line 7 and is connected to the PTFT. The second signal lines are adjacent to each other. Thus, between the pair of signal lines 5 and 8 (inside)
Then, one pixel is constituted by the pixel 23 made of the transparent conductive film and the C / TFT. By repeating such a structure left, right, up and down, a liquid crystal display device having a large pixel of 640 × 480 or 1280 × 960 obtained by enlarging a 2 × 2 matrix can be obtained.

The feature here is that one pixel has two TFs.
Since T is provided in a complementary configuration, the pixel electrode 17 is fixed at three values of the liquid crystal potential _VLC .

Further, the PTFTs are adjacent to each other, and the potential difference applied between the signal lines connected to the PTFTs is the maximum _VSS , and the leakage is small.

As described above, the potential difference actually applied to the liquid crystal is determined by the voltage of the signal of the third signal line, in this embodiment, the pulse voltage of the signal line and the offset voltage of the counter electrode.
This is the potential obtained by subtracting th. That is, when the pulse voltage of the signal line is arbitrarily changed, the potential difference actually applied to the liquid crystal can be changed accordingly. Thus, gradation display can be performed. In particular, when the threshold value for driving the liquid crystal is not clear, that is, for a dispersion type liquid crystal having a gentle threshold, a sufficient gradation display can be performed by a driving method which is particularly well suited.

As another gradation method, when one screen is displayed by applying a plurality of frames of driving signals to the liquid crystal for one display screen, a selection signal to be applied to a specific pixel is set to the number of frames for all frames. By reducing the number, gradation display can be easily performed.

If TN liquid crystal is used as the liquid crystal material in this embodiment, it is necessary to set the distance between the substrates of the liquid crystal container to about 10 μm, provide an alignment film on both transparent conductive films, and rub it.

When an FLC (ferroelectric) liquid crystal is used as the liquid crystal material, the operating voltage is ± 20 V, the cell interval is 1.5 to 3.5 μm, for example, 2.3 μm, and the opposing electrode 1
It is sufficient to provide an alignment film only on 6 and perform a lapping process.

When a dispersion type liquid crystal or a polymer liquid crystal is used, an alignment film is unnecessary, and in order to increase the switching speed, the operating voltage is set to ± 10 ± 15V and the cell interval is set to be as thin as 1 to 10 μm.

In particular, when a dispersion type liquid crystal is used, since a polarizing plate is not necessary, the amount of light can be increased both in a reflection type and in a transmission type. Since the liquid crystal does not have a threshold, a C / TFT type in which a clear threshold voltage is defined as in the present invention eliminates large contrast and crosstalk (bad interference with adjacent pixels). I was able to.

Further, as the semiconductor of the TFT used in this embodiment, materials other than those used in this embodiment can be used.

[0047]

[Embodiment 2] In this embodiment, the present embodiment was carried out using a liquid crystal display having the structure of FIG. 3 and FIG. As is apparent from this drawing, the signal line 3 of the Y line is disposed at the center, and a portion of the pair of signal lines sandwiched between the first signal line 5 and the second signal line 8 is defined as one pixel 23. . One pixel is a pixel 17 of one transparent conductive film.
And two NTFTs 13 and 24 and two PTFTs 2
It is connected to two C / TFTs of 2, 25.
All the gate electrodes are connected to the third signal line 3, two NTFTs are connected to the second signal line 8, and two PTFTs are connected to the first signal line 5. Further, the NTFT of the C / TFT provided in the next pixel is connected to the second signal line 6 by the P signal.
The TFT is connected to the first signal line 7. Further, even if one of these two C / TFTs is defective due to leakage between the gate electrode and the channel formation region, it can be operated as a pixel.

The feature here is that one pixel has two C / Ts.
By providing the FT, the pixel electrode 17 is fixed at three values of the liquid crystal potential _VLC . In addition, the NTFTs overlap, and the potential difference applied between the signal lines connected to the NTFTs is the maximum _VSS and the leakage is small.

The driving method will be described with reference to FIG. As shown in FIG. 4, the ON signal waveform is applied to the third signal line 3 during the period in which the ON signal waveform is applied between the pair of the first signal line 5 and the second signal line 8. When applied, the liquid crystal potential (V _LC ) 14 becomes the voltage V applied to the first signal line.
_DD . Further, when the off signal waveform is applied to the third signal line 3 during the period when the off signal waveform is applied between the pair of the first signal line 5 and the second signal line 8, the liquid crystal potential (V
_LC ) 14 has no potential. Furthermore, a pair of first
When the ON signal waveform is not applied to the third signal line 3 while the OFF signal waveform is applied between the signal line 5 and the second signal line 8, the liquid crystal potential (V _LC ) 14 2 is applied to the signal line _Vss . The liquid crystal voltage _(V LC) 14 as write for capable of fixing to _{V DD} or _{V SS,} never become floating.

[0050]

Embodiment 3 In this embodiment, the present embodiment was carried out using a liquid crystal display having the structure shown in FIGS. As is apparent from this drawing, the signal line 3 of the Y line is disposed at the center, and a portion of the pair of signal lines sandwiched between the first signal line 5 and the second signal line 8 is defined as one pixel 23. . One pixel is composed of two transparent conductive pixel electrodes 17 and 26, and the pixel 17 is composed of NTFT 13 and P
The TFT 22 is connected, and the pixel 26 has an NTFT 24,
PTFTs 25 are each connected as a C / TFT configuration. All the gate electrodes are connected to a signal line 3, two NTFTs are connected to a first signal line 5, and two PTFTs are connected to a second signal line 8. The PTFT of the C / TFT provided in the next pixel is connected to the second signal line 6 and the NTFT is connected to the first signal line 7. These two
Even if one of the C / TFTs is defective due to leakage between the gate electrode and the channel formation region, it can operate as a pixel. So,
Even if one of the pixels only operates halfway, the other pixel operates normally, and when it is colorized, the degree of gray scale degradation can be reduced.

In the present embodiment, the two second signal lines 8 and 6 provided between adjacent pixels are first formed by patterning on the substrate as one wiring using the same material. Then, in a subsequent step, the wiring was divided into two by an excimer laser pattern. In this case, the interval between the two signal lines can be reduced, and the aperture ratio of the display device can be improved. In addition, the required accuracy of the mask used in the manufacturing process has been reduced, so that the manufacturing yield can be improved and the mask cost can be reduced.

[0052]

As described above, according to the driving method of the present invention, since the liquid crystal potential is not floated, stable display can be performed. Further, since the driving capability of the C / TFT as the active element is high, the operation margin can be expanded, and the peripheral driving circuit can be further simplified, which is effective in reducing the size of the display device and reducing the manufacturing cost. . In addition, high driving capability can be exhibited with very simple signals to the three signal lines and the counter electrode.

Even if some of the defective TFTs are in-phase output, it can be compensated to some extent.

Further, since no high potential difference is applied between the signal lines connected to the adjacent pixels, no leakage occurs. Further, the interval between the adjacent signal lines can be reduced, and the aperture ratio of the display device can be improved.

As a display medium in the present invention, a transmission type liquid crystal display device or a reflection type liquid crystal display device can be used. As a usable liquid crystal material, a TN liquid crystal, an FLC liquid crystal, a dispersion liquid crystal, or a polymer liquid crystal as described above can be used. In addition, by adding an ionic dopant to a guest-host type or dielectric anisotropic type nematic liquid crystal and applying an electric field, an electric field is applied to a mixture of the cholesteric liquid crystal and the nematic liquid crystal, and the nematic phase and the cholesteric phase are mixed. A phase change liquid crystal that causes a phase change between the two and realizes a transparent or opaque display can also be used. In addition to the liquid crystal, for example, a so-called electrophoretic display dispersion system in which pigment particles having different colors are dispersed in an organic solvent colored with a dye can be used.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an active display device using complementary TFTs.

FIG. 2 shows a driving waveform of the present invention.

FIG. 3 is a circuit diagram of an active display device using complementary TFTs.

FIG. 4 shows a driving waveform of the present invention.

FIG. 5 is a circuit diagram of an active display device using complementary TFTs.

FIG. 6 is a circuit diagram of a conventional active liquid crystal device.

FIG. 7 is a plan view of one substrate of the liquid crystal display device corresponding to FIG.

8 is a plan view of one substrate of the liquid crystal display device corresponding to FIG.

9 is a plan view of one substrate of the liquid crystal display device corresponding to FIG.

FIG. 10 shows a manufacturing process diagram of a C / TFT used in the present invention.

FIG. 11 shows a manufacturing process diagram of a C / TFT used in the present invention.

[Description of Signs]-Process using photomask 1, 2-Peripheral circuit 3, 4-Third signal line 5, 6, ... First signal line 7, 8, ... · Second signal line 13 ··· NTFT 16 ··· Counter electrode 17 ··· Pixel electrode 22 ··· PTFT 23 ··· Pixel

Claims (4)

(57) [Claims] 1. A first and a second substrate provided facing each other, a layer of a display medium inserted between the substrates, and a first N-channel thin film transistor provided on the first substrate. And a first transistor having a complementary transistor composed of a first P-channel thin film transistor and a first pixel electrode.
And a second transistor having a second pixel electrode and a complementary transistor including a second N-channel thin film transistor and a second P-channel thin film transistor provided on the first substrate.
Pixels, first, second, fourth, and fifth signal lines provided on the first substrate and parallel to the X direction; and pixels provided on the first substrate and parallel to the Y direction. And a third signal line, wherein one of a source and a drain of the first N-channel thin film transistor is connected to a first pixel electrode, and the other is connected to a first signal line, respectively. One of a source and a drain of the P-channel thin film transistor is connected to a first pixel electrode, and the other is connected to a second signal line, respectively, and gate electrodes of the first N-channel thin film transistor and the first P-channel thin film transistor Is connected to a third signal line, one of a source and a drain of the second N-channel thin film transistor is connected to a second pixel electrode, and the other is connected to a fourth signal line, One of a source and a drain of the second P-channel thin film transistor is connected to a second pixel electrode, and the other is connected to a fifth signal line, respectively, and the second N-channel thin film transistor and the second P-channel thin film transistor are connected to each other. The display device, wherein a gate electrode of the thin film transistor is connected to a third signal line, and the first signal line is adjacent to the fourth signal line. 2. A first and a second substrate provided to face each other, a layer of a display medium inserted between the substrates, and a first N-channel thin film transistor provided on the first substrate. And a first transistor having a complementary transistor composed of a first P-channel thin film transistor and a first pixel electrode.
And a second transistor having a second pixel electrode and a complementary transistor including a second N-channel thin film transistor and a second P-channel thin film transistor provided on the first substrate.
Pixels, first, second, fourth, and fifth signal lines provided on the first substrate and parallel to the X direction; and pixels provided on the first substrate and parallel to the Y direction. And a third signal line, wherein one of a source and a drain of the first N-channel thin film transistor is connected to a first pixel electrode, and the other is connected to a first signal line, respectively. One of a source and a drain of the P-channel thin film transistor is connected to a first pixel electrode, and the other is connected to a second signal line, respectively, and gate electrodes of the first N-channel thin film transistor and the first P-channel thin film transistor Is connected to a third signal line, one of a source and a drain of the second N-channel thin film transistor is connected to a second pixel electrode, and the other is connected to a fourth signal line, One of a source and a drain of the second P-channel thin film transistor is connected to a second pixel electrode, and the other is connected to a fifth signal line, respectively, and the second N-channel thin film transistor and the second P-channel thin film transistor are connected to each other. The display device, wherein a gate electrode of the thin film transistor is connected to a third signal line, and the second signal line is adjacent to the fifth signal line. 3. The liquid crystal display device according to claim 1, wherein the layer of the display medium is any one of an FLC liquid crystal, a polymer liquid crystal, a TN liquid crystal, a dispersion liquid crystal, a guest host liquid crystal, and a phase transition liquid crystal. 2. The display device according to 2. 4. The display device according to claim 1, wherein the first and second pixels are adjacent to each other.