JP2705092B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a semiconductor device, and more particularly to a semiconductor device with improved contact formation of an electrode wiring and a method of manufacturing the same. In order to improve the effect of the contact resistance of the silicon substrate (1) at the bottom of the contact hole (8), a single layer of metal silicide or metal silicide (4)
And a wiring layer having a two-layer structure of polysilicon (3) are connected in a self-aligned manner by platinum group silicide (7) in the contact hole.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device with improved contact formation of an electrode wiring and a method of manufacturing the same.

2. Description of the Related Art In recent years, with the increase in the degree of integration of semiconductor devices, multilayer wiring structures have been promoted along with scaling down. In particular, in the conventional aluminum wiring electrode, the stress and the electromigration characteristics are significantly deteriorated due to the miniaturization. As alternative electrode wiring materials, refractory metal silicides and silicide / polysilicon structures have come to be used. This structure is shown in FIG. This improves stress and electromigration characteristics, but degrades electrical contact characteristics. That is, the contact resistance between silicide and polysilicon or between silicide and substrate silicon becomes extremely high. This is because a high temperature heat treatment (800 ° C. or higher) necessary to reduce the wiring resistance of the silicide formed as the wiring electrode causes the contact portion (second
In the case of the figure, the interface between the silicide layer 4 and the polysilicon layer 3)
, Redistribution of impurities (arsenic, boron, phosphorus, etc.).

[Conventional technology]

In order to solve this problem, attention has recently been paid to short-time annealing using a tungsten halogen lamp or an arc lamp as means for suppressing the redistribution of impurities. By using this for heat treatment for lowering the resistance of silicide, the above-described deterioration of the electrical contact characteristics is suppressed.

[Problems to be solved by the invention]

As described above, an increase in contact resistance can be suppressed by using short-time annealing. However, if further heat treatment is required in the process, the contact resistance may increase. Also, tungsten silicide, which is usually selected as a wiring material,
Titanium silicide and the like have higher contact resistance with polysilicon or substrate silicon than conventional aluminum. For this reason, it is necessary to lower the contact resistance by increasing the carrier concentration between silicide and polysilicon or substrate silicon by supplementing impurities.

The present invention addresses these problems. Provided is a method of manufacturing a semiconductor device in which a contact resistance between a single-layer silicide layer or a silicide-polysilicon double-layer wiring electrode and a substrate silicon is made low ohmic without compensating impurities for n-type and p-type silicon substrates. With the goal.

[Means for solving the problem]

According to the present invention, after forming a contact hole in an insulating film on a silicon substrate (1), a single layer of a silicide of a refractory metal,
Alternatively, a wiring electrode having a two-layer structure of silicide (4) / polysilicon (3) is formed so as to cover about 1/2 of the contact hole (8), an insulating film is further formed on this structure, and the above-mentioned structure is formed again. Open a hole on the contact hole. Here, the wiring electrode in the contact hole and the exposed substrate silicon not covered therewith are selectively and selectively used as a platinum group silicide layer (7), and the wiring electrode and the substrate silicon are joined with the platinum group silicide. Since the platinum silicide group can make good contact with both the p-type silicon layer and the n-type silicon layer, it is not necessary to particularly compensate for impurities. Further, in this structure, even if a heat treatment is performed in a later step, the contact between the platinum group silicide and the substrate silicon is stable, so that the deterioration of the contact characteristics is extremely small.

(Operation)

Good contact between the wiring electrode having a high melting point metal silicide or a silicide / polysilicon structure and the substrate silicon can be obtained. Further, the deterioration of the contact due to the heat treatment is extremely small. When the present structure is connected with an aluminum wiring electrode, the platinum group silicide acts as a barrier between aluminum and the substrate silicon to prevent spikes of aluminum onto the substrate silicon and formation of a solid phase epitaxial layer of silicon.

〔Example〕

Next, an embodiment will be described with reference to FIG.
1 (a) to 1 (e) are process diagrams showing an embodiment of the present invention.

(Step 1) (FIG. 1A) First, a contact hole (8) is formed in a silicon oxide film (2) on a silicon substrate (1). Next, a polysilicon layer (3) by the CVD method and a silicide layer (4) are deposited on the entire surface by the CVD method or the sputtering method. As this silicide, titanium silicide, molybdenum silicide, tungsten silicide or the like is used.

(Step 2) (FIG. 1 (b)) By patterning, a silicide (4) / polysilicon (3) structure is obtained which only has a contact hole center.

(Step 3) (FIG. 1 (c)) After growing a silicon oxide film (5) as an insulating film by the CVD method, a contact hole is opened again in the silicon oxide film (5) on the contact hole formed in the step 1. Make a hole.

(Step 4) (FIG. 1 (d)) After a platinum layer (6) is deposited on the entire surface by sputtering, the temperature is 450 ° C.
Then, the surface of the silicide (4) / polysilicon (3) exposed in the contact hole and the substrate silicon are converted to platinum silicide (7) by the heat treatment. For the platinum layer (6), a platinum group element such as palladium is used.

(Step 5) (FIG. 1 (e)) The unreacted platinum layer other than the contact hole is removed by selective etching. Next, an aluminum metal layer 8 is deposited on the entire surface by a sputtering method, and is patterned to form a predetermined wiring.

〔The invention's effect〕

As described above, according to the present invention, the contact between the wiring electrode having the silicide or silicide / polysilicon structure and the substrate silicon is via the platinum silicide formed in the contact hole. A low ohmic contact can be obtained even when contact between the substrate and silicon is difficult. Further, since it is not necessary to compensate for impurities in the contact portion, it is useful for a CMOS process.

Further, even if the aluminum electrode and the present structure are connected by the platinum silicide in the contact hole, there is no spike of aluminum to the silicon substrate and no deterioration of the contact structure due to the solid phase epitaxial layer.

[Brief description of the drawings]

1 (a) to 1 (e) are views for explaining a method for manufacturing a semiconductor device shown as one embodiment of the present invention, and FIG. 2 is a view for explaining a conventional semiconductor manufacturing method. . DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2,5 ... Silicon oxide film 3 ... Polysilicon layer 4 ... High melting point metal silicide layer 6 ... Platinum group element layer 7 ... Platinum group silicide layer 8 ... Metal aluminum layer

 ────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-57-208169 (JP, A) JP-A-58-33833 (JP, A)

Claims (1)

(57) [Claims] After a contact hole is formed in a first insulating film on a silicon substrate, a metal silicide single layer or a wiring layer having a two-layer structure of a metal silicide and polysilicon contacting the silicon substrate at the bottom of the contact hole is formed. Process and
Etching the wiring layer in the contact hole to expose a silicon substrate surface; forming a second insulating film on the entire surface; etching the second insulating film on the contact hole and reopening the hole; Forming a platinum group silicide by applying a platinum group element to a region including the contact hole, and reacting the wiring layer and the silicon substrate in the contact hole with the platinum group element by heat treatment, Selectively removing a platinum group element that is not silicided, and connecting the wiring layer in the contact hole and the silicon substrate to a self-aligned wiring.