JP2703367B2 - Inverter parallel control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a parallel control device of an inverter that synchronizes with a frequency reference signal of a high-frequency power supply or the like and performs parallel operation of a plurality of inverters.

(Prior Art) In an uninterruptible power supply using an inverter, a parallel operation system of a plurality of inverters is often used in order to improve the reliability of the system. In addition, when the output of such a parallel operation inverter and the direct power commercial power supply are connected by a changeover switch, this changeover switch is used in the event that the system of the parallel operation inverter is down or when the entire inverter system is maintained. There is also widely used a method of switching to a direct power commercial power supply without instantaneous interruption and continuously supplying power to a load to further improve the reliability as a power supply system. In such a system, it is necessary that the output phases of the respective inverters coincide with each other and that the output phases of the inverters also coincide with the phase of the direct power commercial power supply.

FIG. 3 is a block diagram showing a conventional parallel operation inverter control device. FIG. 2 shows a case where two inverters are operated in parallel as a first unit and a second unit, and the first unit is denoted by a suffix a and the second unit is denoted by a suffix b. 1a and 1b are DC buses, and these buses 1a and 1b
Is supplied with a rectifier (not shown) for converting alternating current to direct current or a storage battery or a direct current voltage obtained by using both of them. 2a and 2b are inverters that convert the voltage supplied through the DC buses 1a and 1b into AC, 3a and 3b are AC filters that improve the inverter output into a sine wave, and 4a and 4
b is a circuit breaker for turning on or off each of the inverters 2a and 2b in parallel, 5 is a direct power commercial power supply, and 6 and 7 are inverters 2
A static changeover switch (semiconductor switch) 8 for switching between the a, 2b and the direct power commercial power supply 5 without instantaneous interruption, and 8 is a load.

On the other hand, the control circuit includes phase difference detectors (PHD) 111a and 111b, low-pass filters (LPF) 112a and 112b, and voltage-controlled oscillators (VC
O) phase locked loop (PLL) circuits 11a and 11b composed of 113a and 113b, ring counters 12a and 12b that divide the output of the PLL circuits 11a and 11b to generate gate pulses of the inverters 2a and 2b, Active power deviation (ΔP) detection circuits 13a, 13b and phase correction circuits 14a, 14b that provide a signal for correcting the deviation of the active power supplied by each inverter 2a, 2b to the low-pass filters 112a, 112b of the PLL circuits 11a, 11b. It is composed of

Actually, as control for operating the inverters in parallel, voltage control for correcting reactive power is also required, but the description thereof is omitted here.

The PLL circuit is a known technology, and the detailed operation of the above-described configuration in which the active power deviation of the output of each inverter is fed back to the PLL circuit to correct the deviation is described in Japanese Patent No. 1215332.
No. "Parallel operation device of inverter". That is, the output frequency of the voltage-controlled oscillators 113a and 113b, that is, the phase, is automatically controlled so that the deviation of the sharing of active power caused by the irregular operation of the control circuit of each inverter, the irregularity of the main circuit impedance, and the like becomes zero. It is.

By the way, in such an inverter parallel control device, a phase difference detector (PHD) 111a,
As can be seen from the example of the time chart shown in FIG. 4, 1b does not detect the phase difference continuously but detects it about once in one cycle, and the PLL circuit itself is originally a PHD. Voltage controlled oscillator (VCO) depending on the output of
The so-called integral control (Θ = ∫fdt, which controls the phase while maintaining the state where the output frequencies of 113a and 113b are changed)
Θ; phase, f; frequency).

Therefore, the response time of the PLL circuits 11a and 11b is set to be slower than that of the normal voltage control system or the like. In this case, the PLL circuits 11a, 1
The response of 1b is mainly determined by the characteristics of the low-pass filters (LPF) 112a and 112b.

(Problems to be Solved by the Invention) However, as described above, the phase correction control is performed by giving the active power deviation (ΔP) to the low-pass filters 112a and 112b of the PLL circuits 11a and 11b through the phase correction circuits 14a and 14b. Since the characteristics of the low-pass filters 112a and 112b and the PLL circuit are of integral control, a sufficiently high phase correction control response cannot be obtained. For this reason, for the transient cross current generated between the inverters due to the phase deviation at the time of parallel injection, etc., phase correction control for rapidly suppressing this cross current is not sufficiently performed. In this case, there is a problem that the inverter stops tripping due to excessive cross current.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an inverter parallel control device capable of suppressing a cross current with a sufficiently high phase correction control response to a transient cross current caused by a phase deviation at the time of parallel injection or the like.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a parallel control device for inverters, which synchronizes with a predetermined frequency reference signal and operates in parallel with a plurality of inverters. A phase lock loop circuit that controls the output frequency and phase of the frequency reference signal to steadily synchronize with the frequency and phase of the frequency reference signal, and an active power deviation detection circuit that detects an active power deviation between the units of the inverter, When an active power deviation is detected by the active power deviation detection circuit, a stationary phase correction circuit that supplies a phase correction signal to the phase locked loop circuit to correct a stationary phase, and the output from the phase locked loop circuit. A phase shifter that changes a phase of a frequency reference signal; and a phase shifter that detects the inverter detected by the active power deviation detection circuit. And a transient phase correction circuit for transiently changing the phase of the frequency reference signal by adjusting the gradient of the phase change with respect to the active power deviation detection signal between the units and applying the same to the phase shifter. is there.

(Operation) Therefore, in the inverter parallel control device having such a configuration, when the active power deviation ΔP is detected due to the occurrence of the cross current between the inverters, the steady phase correction for this ΔP is performed by the phase locked loop circuit. The transient phase correction is performed by adjusting the phase of the frequency reference signal output from the phase-locked loop circuit by the transient phase correction circuit with the gradient of the phase change with respect to the active power deviation detection signal between the units of the inverter. Since this is performed by the input phase shifter, the response of the phase correction control can be speeded up, and the transient cross current can be suppressed rapidly.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration example of a parallel control device for inverters according to the present invention. The same parts as those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted. Only different points will be described here. In the present embodiment, as shown in FIG. 1, the frequency reference signals output from the PLL circuits 11a and 11b are compared with the ΔP output from the active power deviation (ΔP) detection circuits 13a and 13b.
Phase shifters 21a and 21b are provided to provide a signal whose phase is changed according to the magnitude of the detection signal to the ring counters 12a and 12b. In this case, a ΔP detection signal output from the active power deviation (ΔP) detection circuits 13a and 13b is supplied to the transient phase correction circuits 22a and 22b, and ΔP input to the phase shifters 21a and 21b.
The inclination (gain) of the phase change with respect to the P detection signal is adjusted.

In addition, the phase correction circuits 14a and 14b are referred to as stationary phase correction circuits herein with respect to the transient phase correction circuits 22a and 22b.

Next, the operation of the thus configured inverter parallel control device will be described with reference to a time chart shown in FIG.

Now, the gain G of the transient phase correction circuits 22a and 22b and the gain K of the stationary phase correction circuits 14a and 14b are adjusted to adjust the phase shifters 21a and 21b.
, It is assumed that the transient phase correction operation due to the above does not affect the stability of the PLL circuits 11a and 11b as closed loop control.

First, when the active power distribution of the inverters 2a and 2b is equal and the active power deviation ΔP is zero, the output pulses of the phase shifters 21a and 21b are output from the voltage controlled oscillators (VCO) 113a and 1b as shown in FIG.
To the output pulse 13b, which operates as delayed by .DELTA..theta _0.

In such a state, a cross current transiently occurs between the inverters, for example, at the time of parallel injection, and the active power deviation ΔP detected by the active power deviation detection circuit 13a of the first unit.
Becomes a negative level, the phase delay of the output pulse of the phase shifter 21a with respect to the output pulse of the VCO 113a becomes ΔΘ ₁ (ΔΘ ₁ <
ΔΘ ₀ ), changes more rapidly in the advancing direction than when ΔP is zero, and the phase of the pulse applied to the ring counter 12a is corrected in a direction to suppress the cross current. Conversely, the active power deviation ΔP of the second unit becomes a positive level, and the phase delay of the output pulse of the phase shifter 21b with respect to the output pulse of the VCO 113b is ΔP
Changes in the delay direction as compared with the case where is zero.

Further, when the active power deviation ΔP becomes a positive level, the phase delay of the output pulse of the phase shifter 21a with respect to the output pulse of the VCO 113a becomes ΔΘ ₂ (ΔΘ ₂ > ΔΘ ₀ ), as compared with the case where ΔP is zero. , Changes rapidly in the delay direction, and the phase of the pulse applied to the ring counter 12a is corrected in a direction to suppress the cross current. Conversely, the active power deviation ΔP of the second unit becomes a negative level, and the phase shifter 21b for the output pulse of the VCO 113b
Of the output pulse changes in the leading direction as compared with the case where ΔP is zero.

Note that the steady phase correction for the active power deviation ΔP is
This is performed by the PLL circuits 11a and 11b.
It is determined by the characteristics of the circuit and the gain K.

As described above, in the present embodiment, the phase delay with respect to the output pulse phase of the PLL circuits 11a and 11b is rapidly changed by the phase shifters 21a and 21b provided on the output side of the PLL circuits 11a and 11b in accordance with the active power deviation ΔP. As a result, the transient cross-flow between the inverters, which occurs at the time of parallel connection, can be quickly suppressed. Also, since the inverter does not stop tripping due to excessive cross current, it is not necessary to perform precise phase adjustment.

In the above embodiment, the delay time of the characteristics of the phase shifters 21a and 21b is changed in accordance with ΔP. However, ΔP is set to zero when the delay is zero, and the phase shifts in the delay direction according to the polarity of ΔP. The same effect as described above can be obtained by using the phase shifter as described above.

Although FIG. 1 illustrates the case where two inverters are operated in parallel, the same operation can be performed as described above even when the number of parallel operated units is three or more.

[Effects of the Invention] As described above, according to the present invention, in a parallel control apparatus of an inverter that synchronizes with a frequency reference signal of a commercial power supply or the like and performs a parallel operation of a plurality of inverters, the inverter causes a phase deviation at the time of parallel connection or the like. It is possible to provide a parallel inverter control device that has a sufficiently high phase correction control response to a transient cross current and that can stably and stably perform phase control.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing one embodiment of a parallel control device for an inverter according to the present invention, FIG. 2 is a diagram showing a time chart for explaining the operation of the embodiment, and FIG. FIG. 4 is a block diagram showing an example of the parallel control device, and FIG. 4 is a time chart for explaining the operation of the conventional device. 1a, 1b: DC bus, 2a, 2b: Inverter, 3a, 3b AC filter, 4a, 4b: Circuit breaker, 5: Commercial power supply,
6,7 ... changeover switch, 11a, 11b ... PLL circuit, 111a, 111b
… Phase difference detection circuit, 112a, 112b… Low pass filter, 113a, 113b… Voltage controlled oscillator, 12a, 12b… Ring counter, 13a, 13b… Active power deviation detection circuit, 14a, 14b
…… Stationary phase correction circuit, 21a, 21b …… Phase shifter, 22a, 22b…
... Transient phase correction circuit.

Claims (1)

(57) [Claims] 1. A parallel control device for inverters synchronized with a predetermined frequency reference signal and operating in parallel with a plurality of inverters, wherein the output frequency and phase of each inverter are constantly synchronized with the frequency and phase of the frequency reference signal. And an active power deviation detecting circuit for detecting an active power deviation between the respective units of the inverter, and the phase locked loop circuit when an active power deviation is detected by the active power deviation detecting circuit. A phase correction circuit that provides a phase correction signal to correct the phase to a stationary phase, a phase shifter that changes the phase of the frequency reference signal output from the phase locked loop circuit, and the active power deviation detection circuit. By adjusting the gradient of the phase change with respect to the active power deviation detection signal between the respective units of the detected inverter, Parallel control device of an inverter, characterized in that a transient phase correcting circuit for changing the phase of said frequency reference signal transitionally by providing the phase vessel.