JP2793526B2 - Super scalar processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a superscalar processor, and more particularly to a superscalar processor capable of executing both an address operation and a data operation in respective pipelines.

[0002]

2. Description of the Related Art As a first prior art, Japanese Patent Laid-Open No.
There is a superscalar processor described in JP-A-67936.

In FIG. 3 showing this, a superscalar processor includes an instruction fetch stage 102 for fetching an instruction from an instruction memory 101, an instruction decode stage 103 for decoding the fetched instruction, and a pipeline control for executing an operation. Functional units 104, 1
05, 106, and 107, a register file 109 for storing data, and a bypass line 112, and perform pipeline processing in parallel.

[0004] The functional units 104 to 107 are:
An execution stage (EXC) 141, a memory access stage (MEM) 142, and a write back stage (W
B) 143.

In this technique, the function unit 104
To 107 do not multiplex and execute one instruction. That is, one instruction is executed by only one functional unit.

A second prior art is disclosed in "57
No.-98069, there is a "method for checking the operation of an arithmetic unit". This technology is a technology in which one vector operation is executed by a plurality of operation units and operation results are compared.

[0007]

In the first prior art superscalar processor described above, each of the pipeline control function units 104 to 107 has a configuration in which a memory access stage and a data operation stage are sequentially executed. Therefore, there is a disadvantage that the number of stages in the pipeline is large and the throughput of instruction processing is reduced. Further, since one instruction is executed only by one functional unit, there is a disadvantage that the normality of the device unit cannot be checked.

[0008] The above-mentioned second prior art “operation check method of arithmetic unit” uses an arithmetic unit that executes only vector operation, and has a drawback that it cannot be applied to scalar arithmetic processing. In addition, since the arithmetic unit cannot execute the address operation, there is a disadvantage that the normality of the address operation cannot be checked.

[0009]

A first superscalar processor according to the present invention comprises: (a) a first pipeline for processing a memory access instruction; and (b) a second pipeline for processing a data operation instruction. And (c) a first pipeline which is present in the first pipeline and can execute both an address operation and a data operation, and can simultaneously execute only one of the address operation and the data operation. An operation unit, (d) present in the second pipeline, capable of executing both address operation and data operation, and simultaneously executing only one of the address operation and the data operation. (E) decoding an instruction existing in the first pipeline
1st vacancy display indicating whether there is an instruction to execute and execute
A first instruction decoder including a flag; and (f) decoding an instruction present in the second pipeline.
Second empty display indicating whether there is an instruction to execute and execute
A second instruction decoder including a flag, and (g) the first and second empty indication flags
When it is detected that an instruction does not exist in one of the first and second pipelines, the operation unit of the pipeline in which the instruction does not exist is the same as the operation executed in the pipeline in which the instruction exists. And a pipeline control unit for performing the above calculation .

According to a second superscalar processor of the present invention, in addition to the first configuration, when the operation results output from the two operation units are compared with each other and a mismatch is detected, the operation of the pipeline is stopped and the mismatch is detected. Is provided with an error detection circuit for reporting that the is detected.

[0011]

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, "Pipeline A" 1 is a pipeline for processing a memory access instruction, and "Pipeline B" 2 is a pipeline for processing a data operation instruction. Each has instruction decoders 3 and 4, selectors 5 and 6, and operation units 7 and 8.

The instruction decoders 3 and 4 have empty display flags 31 and 41 for indicating the presence / absence of an instruction to be executed. When the instruction is issued, the instruction decoder decodes the instruction. The indicated pipeline empty signal is generated on the control signal lines 32 and 42. The instruction decoders 3 and 4 are connected to the error detection circuit 10 and stop decoding the instruction in response to an operation stop signal on the control signal line 94.

The operation units 7 and 8 are connected to the pipeline control unit 9 and have mode flags 71 and 81 indicating which of an address operation and a data operation can be executed.

The selectors 5 and 6 are provided between the instruction decoders 3 and 4 and the operation units 7 and 8, respectively.
According to 2, 42, either the address operation source output via the data line 33 or the data operation source output via the data line 43 is selected, and the operation source data is transmitted via the operation source data line 50. And outputs it to the operation units 7 and 8.

The pipeline control unit 9 is connected to the instruction decoders 3 and 4, and receives pipeline empty signals on the control signal lines 32 and 42. "2", the mode switching signal is output on the control signal lines 91 and 92, and the comparison valid signal is output to the error detection circuit 10 via the control signal line 93.

The error detection circuit 10 is connected to the pipeline control unit 9, and receives a comparison valid signal via a signal line 93, and outputs a check data line 7 output from the operation unit 7.
3 is compared with the calculation result data on the check data line 83 output from the calculation unit 8. When a mismatch is detected, an operation stop signal is output on a control signal line 94 and an error detection signal is output on a signal line 95.

Next, an operation when a memory access instruction and a data operation instruction are issued alternately will be described with reference to FIG.

The memory access instruction is issued to the instruction decoder 3 via the data line 30, and the data operation instruction is issued to the instruction decoder 4 via the data line 40.

Since these instructions are processed simultaneously in the "pipeline A" 1 and the "pipeline B" 2, there is no empty space in the two pipelines.

At this time, the pipeline empty signal transmitted on the control signal lines 32 and 42 is "0",
Then, the selector 6 selects the data transmitted via the data line 43, and the selector 6 selects the data transmitted via the data line 43.
Output to 0 and 60.

The mode switching signal transmitted via the control signal lines 91 and 92 is "0", and the mode flag 7
Numerals 1 and 81 indicate the normal mode “0”.

The operation unit 7 executes an address operation, and the operation unit 8 executes a data operation. The operation result from the operation unit 7 is used for memory access via the address data line 72. The operation result from the operation unit 8 is stored in the register via the write data line 82.

The operation result output via the check data lines 73 and 83 is sent to the error detection circuit 10, but the comparison valid signal sent via the control signal line 93 is "0". No data comparison is performed and no errors are detected.

Next, the operation when memory access instructions are successively issued will be described with reference to FIGS.

FIG. 2 is a time chart showing the operation.

In FIG. 2, N1, N2, and N3 are memory access instructions executed sequentially. This figure also shows
The case where an error is detected in the instruction N2 is shown.

Instructions are continuously issued to the "pipeline A" 1 via the data line 30, the empty display flag 31 in the instruction decoder 3 remains "0", and the pipeline empty signal is "0". As "" via the control signal line 32. The selector 5 selects data sent via the data line 33 and outputs the data to the data line 50 as operation source data.

Since no instruction is issued to the "pipeline B" 2, the empty display flag 41 in the instruction decoder 4 is updated from "0" to "1", and the pipeline transmitted through the control signal line 42 The empty signal becomes "1". The selector 6 selects the data sent via the data line 33 according to the pipeline empty signal and outputs the data to the data line 60 as operation source data.

In the pipeline control unit 9, the control signal line 4
Since the pipeline empty signal received through the control signal line 2 has been updated from “0” to “1”, the mode switching signal output to the arithmetic unit 8 via the control signal line 92 becomes “1”. Further, the comparison valid signal sent to the error detection circuit 10 via the control signal line 93 also becomes “1”.

In the pipeline control unit 9, the pipeline empty signal received via the control signal line 32 is "0", and the mode switching signal transmitted to the arithmetic unit 7 via the control signal line 91 is also "0". 0 ".

In the arithmetic unit 7, the mode flag 71 indicates the normal mode "0" by the mode switching signal from the control signal line 91, so that the address operation is executed, and the operation result is obtained by the address data line 72 and the check data line. 73 is output.

In the operation section 8, since the mode flag 81 is updated to the check mode "1" by the mode switching signal from the control signal line 92, the address operation becomes possible, and the mode flag 81 is received via the data line 60. Performs an address operation on the operation source data.

The calculation result is not output to the write data line 82 but is output only to the check data line 83.

Since the comparison valid signal from the control signal line 93 is "1", the error detection circuit 10 compares the calculation results received from the check data lines 73 and 83.

Here, when a mismatch is detected, an operation stop signal is sent to the instruction decoders 3 and 4 via the control signal line 94, and the pipeline processing after instruction decoding is stopped.
Further, an error detection is reported to an external diagnostic control unit via a signal line 95.

In FIG. 2, an error has been detected in the execution of the instruction N2.

When data operation instructions are issued successively, data operation is performed in both the operation unit 7 of the "pipeline A" 1 and the operation unit 8 of the "pipeline B" 2. . If the mismatch is detected by the error detection circuit 10, the error detection is reported as in the case of the address calculation.

[0040]

As described above, the superscalar processor of the present invention is configured such that an operation unit of a pipeline having no instruction to be processed can be used as a check circuit of an operation unit of another pipeline. There is an effect that the reliability can be improved without newly increasing the number of circuits for checking.

Also, since the address operation and the data operation are executed by separate operation units, the throughput of the instruction processing is reduced as compared with the case where the address operation and the data operation are sequentially executed by one operation unit. There is an effect of improving.

Further, since the comparison check of the address operation is also performed, an effect of improving the reliability can be achieved as compared with the case where only the data operation is compared and checked.

Also, by adopting a configuration in which the scalar operation can also be performed by the operation unit, there is an effect that improvement in reliability can be achieved as compared with the case where only vector operation is compared.

[0044]

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the embodiment of FIG. 1;

FIG. 3 is a block diagram of a conventional superscalar processor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Pipeline A 2 Pipeline B 3 Instruction decoder 4 Instruction decoder 5 Selector 6 Selector 7 Operation part 8 Operation part 9 Pipeline control part 10 Error detection circuit 30 Data line 31 Empty display flag 32 Control signal line 33 Data line 40 Data line 41 Empty display flag 42 Control signal line 43 Data line 50 Data line 60 Data line 71 Mode flag 72 Address data line 73 Check data line 81 Mode flag 82 Write data line 83 Check data line 91 Control signal line 92 Control signal line 93 Control signal Line 94 control signal line 95 signal line 101 instruction memory 102 instruction fetch stage 103 instruction decode stage 104 to 107 functional unit 108 data memory 109 register file 112 bypass line 141 execution stage Di 142 memory access stage 143 write back stage

Claims (2)

(57) [Claims] 1. A first method for processing a memory access instruction.
(B) a second pipeline for processing a data operation instruction, and (c) both an address operation and a data operation existing in the first pipeline and capable of executing both the address operation and the data operation. A first operation unit capable of executing only one of the address operation and the data operation; and (d) existing in the second pipeline and capable of executing both the address operation and the data operation and simultaneously. A second operation unit capable of executing only one of the address operation and the data operation; and (e) decoding an instruction existing in the first pipeline.
1st vacancy display indicating whether there is an instruction to execute and execute
A first instruction decoder including a flag; and (f) decoding an instruction present in the second pipeline.
Second empty display indicating whether there is an instruction to execute and execute
A second instruction decoder including a flag, and (g) the first and second empty indication flags
When it is detected that an instruction does not exist in one of the first and second pipelines, the operation unit of the pipeline in which the instruction does not exist is the same as the operation executed in the pipeline in which the instruction exists. And a pipeline control unit for performing the calculation of the super scalar processor. 2. An apparatus according to claim 1, further comprising an error detection circuit for comparing operation results output from said two operation units and detecting a mismatch when the mismatch is detected, for stopping a pipeline operation and reporting that the mismatch has been detected. The superscalar processor according to claim 1, wherein