JP2792087B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a nonvolatile semiconductor memory, in particular, a read-only memory that can be electrically written and erased, that is, E ²
It relates to a bit line circuit of a PROM.

[Conventional technology]

A read-only memory capable of electrically writing and erasing data is well known as an E ² PROM. Data writing and erasing are performed on the thin oxide film of the memory cell by Fowler-
The memory cell is turned on by generating a Nordheim tunnel current and injecting and discharging charge into the memory cell
It is common to set the state to an "off" state.

This tunnel current occurs not only at the time of writing and erasing data, but also slightly at the time of reading.When a long-term reading operation is considered, the charge amount of the memory cell is changed, and erroneous data may be read. Causes writing and erasing. Therefore, in order to prevent this, the bit line potential at the time of reading is generally set low so as to suppress the generation of tunnel current.

FIG. 7 shows an example of a conventional bit line circuit. 1 is a memory cell transistor, 2 is a selector transistor, 3 is an Nch transistor for controlling a bit line potential, 7 and 8 are Nch transistors, and 5 is a power supply voltage supply circuit comprising a Pch transistor 4. 6 is an inverter.

Control of the bit line potential V ₃ is as shown in FIG. 8, V _DD potential V ₂ to the power supply voltage V _DD by transistor 7 and 8
The lower potential, yet the transistors 3, made by a lower potential than the threshold potential partial potential V _2. Generally, when V _DD = 5V, the bit line potential V ₃
Is set to a potential of about 1.5 V to 2.0 V.

In the read operation, when the selector is at the H level and the selector transistor 2 is on, the word line is selected and the memory cell transistor 1 is selected, and when the memory cell transistor 1 is "on", the potential V ₁
The output of the inverter 6 for pulling the GND level is H level is outputted, whereas, the potential V ₁ was when the memory cell transistor 1 is "off" state is output at the L level of the temperature Ghali inverter 6 to V _DD level This is done by being output.

[Problems to be solved by the invention]

Writing incorrect data in the conventional bit line circuit, in order is set lower bit line potential V ₃ in order to prevent erasure, too low bit line potential V ₃ at the power supply voltage V _DD is low region, the bit line , The charging speed was slow, and the speed of the read operation was delayed. Although the bit line potential V ₃ becomes impossible read operation in the power supply voltage becomes close to 0V, the power supply voltage value is the bit line potential V ₃
Is set to a low value, the voltage is shifted to a high voltage value, so that it is difficult to perform a low power supply voltage operation. Also,
To increase the power supply potential V _DD bit line potential V ₃ to increase and accompanied also, since the V ₃ increases, there is a risk of exceeding the upper limit voltage for preventing writing of data to the V ₃ wrong, the erasure.

In order to solve such a problem, the present invention suppresses the speed of read operation even at a low power supply voltage, enables low power supply voltage operation, and furthermore, an upper limit for preventing writing or erasing of data in which the bit line potential is incorrect. An object of the present invention is to provide a bit line circuit that can be reliably maintained at a potential lower than a voltage.

[Means for solving the problem]

A semiconductor memory device according to the present invention includes a memory cell transistor that can be electrically written and erased, a bit line connected to the memory cell transistor, a power supply circuit for applying a potential to the bit line, and the power supply circuit. And a N-channel enhancement transistor connected between the bit line and the bit line for controlling the potential of the bit line, wherein a source is connected to a power supply potential, and a drain is a gate of the N-channel enhancement transistor. And an N-channel depletion type transistor having a gate connected to a predetermined fixed potential, and one terminal connected to a connection point between the gate of the N-channel enhancement type transistor and the drain of the N-channel depletion type transistor. Connected and the other Children are connected to the ground potential, further the N-channel depletion-type transistor current supply capability than the current supply capacity of which comprising the set formed by the load decreases. The fixed potential to which the gate terminal of the N-channel depletion type transistor is connected is a ground potential. Further, the load is an N-channel enhancement type transistor.

(Operation)

According to the above configuration of the present invention, the Nch depletion transistor supplies a potential substantially equal to the drain potential of the Nch depletion transistor to the gate of the Nch enhancement transistor that controls the bit line potential in the low power supply voltage region. A decrease in bit line potential can be suppressed. On the other hand, in the high power supply voltage region, the Nch depletion type transistor is turned off, and a constant potential lower than the drain potential is supplied to the gate of the Nch enhancement type transistor that controls the bit line potential, so that the bit line potential can be suppressed.

〔Example〕

FIG. 1 shows a first embodiment of the present invention. Here, the same symbols as those in FIG. 7 of the related art are the same. Reference numeral 9 denotes an Nch depletion type transistor whose drain is connected to the power supply potential and whose gate is connected to the ground potential. Reference numeral 10 denotes a load circuit connected to the ground potential, which is composed of an Nch transistor 11, and whose current supply capability is set to be sufficiently smaller than that of the transistor 9.

Illustrated by Figure 2 for the control of the bit line potential V _3. First, focusing on the potential V ₂ , when the power supply voltage V _DD is low, the potential V ₂ is set by the Nch depletion type transistor 9.
Is supplied with a potential substantially equal to V _DD . When the power supply voltage V _DD further increases, the potential V ₂ also increases at the same time, but the depletion threshold potential of the transistor 9 and
Since the transistor 9 is turned off at the potential V _DEP determined by the gate potential, the potential V ₂ is kept at a constant potential at V _DEP . In any case, the bit line potential V ₃ is the transistor 3
Accordingly, the threshold potential amount, a potential lower than the potential V _2. Potential V ₂ is the potential V ₂ of the conventional example shown by a broken line in FIG. 2 'to become a high potential with a low power supply voltage side of the bit line potential V ₃ is similarly conventional potential V ₃ of shown by the broken line' Higher potential. Therefore, in the low supply voltage region for a reduction in the bit line potential V ₃ is suppressed, a delay charge rate is not slow in read operation speed of the bit line potential is suppressed. Further, since the power supply voltage value V _C of the bit line potential V ₃ becomes close to 0V is shifted to a lower voltage value side (V _C <V _C '), it is possible to achieve low power supply voltage operation. On the other hand, in the high power supply voltage region, the transistor 9 has a constant potential V lower than the power supply voltage V _DD applied to the gate of the transistor 3.
For supplying _DEP, also the bit line potential V ₃ becomes constant potential, the writing of erroneous data that potential is set so as to be lower than the upper limit voltage to prevent erasure, the wrong ensured even up the V _DD Data writing and erasing can be prevented.

FIG. 3 shows a second embodiment of the present invention. Compared with the first embodiment, it is added Nch transistors 13 and 14, the divided voltage V ₄ is applied to the gate of the Nch depletion mode transistor 9. The load circuit 10 includes a resistor 12, and its current supply capability is set to be sufficiently smaller than that of the transistor 9.

Similarly to the first embodiment, as shown in FIG.
_{When DD} is low, the potential V ₂ becomes substantially equal to V _DD by the Nch depletion type transistor 9. Further V _DD is high potential V ₂ keeps the constant potential ▲ V _^'DEP ▼ remain. Since the gate potential V ₄ in this case the transistor 9 becomes the positive potential determined by transistors 13 and 14, the potential ▲ V ^'
The setting of _DEP ▼ makes it easier to set a higher potential than in the first embodiment. Also in this case, as in the first embodiment, to a low power supply voltage region can be sufficiently high potential prior art example of a bit line potential V ₃ than the potential V ₃ 'indicated by a broken line in FIG. 4 may V ₃ is shifted to the power supply voltage V _C lower voltage value side which is near _{0V (V C <V C '} ). Further, the data reliably wrong V ₃ at the high supply voltage region write,
The potential can be kept lower than the upper limit voltage for preventing erasing.

FIG. 5 shows a third embodiment of the present invention. Compared with the first embodiment, the circuit has an Nch transistor 15 added.

Similarly to the first embodiment the power supply voltage V _DD as shown in Figure 6
Is low, the potential V ₂ becomes substantially equal to V _DD by the Nch depletion type transistor 9. When V _DD rises, the potential V ₂ remains constant at V _DEP for one period.
When V _DD rises, the transistor 15 is turned on, so that the potential continues to increase at a potential determined by the transistors 15 and 10. Thus compared with the conventional example as shown in Figure 6 (shown in dashed lines), the characteristics of a high supply voltage region while keeping intact, to a sufficiently high potential bit line potential V ₃ in low supply voltage region And the power supply voltage V _{C at} which V ₃ becomes close to 0 V
Can be shifted to a lower voltage value side (V _C <V _C ′).

As described above, in this embodiment, the drain potential of the Nch depletion type transistor has been described as being equal to the power supply potential.
Even if they are not necessarily the same, the same effect as that of the present embodiment can be obtained by considering that the bit line potential increases and decreases accordingly.

〔The invention's effect〕

As described above, according to the present invention, a decrease in bit line potential in a low power supply voltage region can be suppressed, so that a delay in read operation speed at a low power supply voltage can be suppressed. The power supply voltage can be reduced.

Further, since the bit line voltage can be maintained at a constant potential even at a high power supply voltage, it has been possible to reliably prevent writing and erasing of erroneous data. Furthermore, since this constant bit line potential is determined by setting the threshold potential of the Nch depletion type transistor, the influence of process variations and the influence of power supply voltage fluctuations are small, and a very stable potential is obtained. There is also an advantage that the bit line potential can be maintained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. FIG. 2 is a characteristic diagram showing a potential in the first embodiment of the present invention. FIG. 3 is a circuit diagram showing a second embodiment of the present invention. FIG. 4 is a characteristic diagram showing a potential in the second embodiment of the present invention. FIG. 5 is a circuit diagram showing a third embodiment of the present invention. FIG. 6 is a characteristic diagram showing a potential in the third embodiment of the present invention. FIG. 7 is a circuit diagram showing a conventional bit line circuit. FIG. 8 is a characteristic diagram showing a potential in a conventional bit line circuit. DESCRIPTION OF SYMBOLS 1 ... Memory cell transistor 2 ... Selector transistor 3 ... Nch enhancement type transistor 5 ... Power supply voltage supply circuit 9 ... Nch depletion type transistor 10 ... Load circuit

Claims (3)

(57) [Claims] An electrical writable and erasable memory cell transistor, a bit line connected to the memory cell transistor, a power supply circuit for applying a potential to the bit line, the power supply circuit and the bit. A source connected to a power supply potential, and a drain connected to a gate of the N-channel enhancement type transistor. ,
An N-channel depletion type transistor having a gate connected to a predetermined fixed potential; one terminal connected to a connection point between a gate of the N-channel enhancement type transistor and a drain of the N-channel depletion type transistor; Is connected to the ground potential, and further provided with a load having a current supply capability set to be smaller than the current supply capability of the N-channel depletion type transistor. 2. The semiconductor memory device according to claim 1, wherein the fixed potential to which the gate terminal of said N-channel depletion type transistor is connected is a ground potential. 3. The semiconductor memory device according to claim 1, wherein said load is an N-channel enhancement type transistor.