JP2773663B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as a mask ROM in which data is stored in a nonvolatile manner.

[0002]

2. Description of the Related Art A mask ROM is a memory cell array in which data is stored in a nonvolatile manner, an address buffer for receiving an external address for selecting data of the memory cell array, and a bit line selection and a word line selection of the memory cell array are performed by the captured address. And a sense amplifier that reads out bit line data. The memory cell array stores data by setting a large number of memory MOS transistors arranged in a buried (D) type or an enhanced (E) type according to data, for example. The format of the memory cell array includes
There are a NOR type and a NAND type.

In a mask ROM, while reading out certain bit line data, unselected bit lines are disconnected from a sense amplifier. At this time, if the non-selected bit line is discharged and the potential drops to the ground level, it takes time to raise the bit line to a predetermined level when it is next selected. This delay in bit line charging prevents high speed access of the mask ROM. In order to enable high-speed access to the mask ROM, a precharge method of charging an unselected bit line to a predetermined level in preparation for the next access is effective (for example, see Japanese Patent Application Laid-Open No. HEI 5-14428).
No. 4).

There is a similar problem in word line selection. For example, in the case of a NAND memory cell, data reading is performed with the selected word line set to 0 V and the remaining unselected word lines set to VDD. Since the word line is connected to the gates of a large number of memory cells, the load is large.
It takes time to drop to V. Actually, the threshold value is about 0.8 V in the case of the E-type memory transistor, and therefore, there is a delay until the selected word line drops from VDD to 0.8 V. In order to solve the delay in the word line, for example, it has been proposed that only the drive power supply for the word line is set to a low power supply of 3 V, for example.

[0005]

The method of precharging all the non-selected bit lines in order to realize high-speed access to the mask ROM has a problem that current consumption increases due to the precharge. Also, the method of lowering the word line drive power supply with respect to the delay of the potential transition of the word line is as follows.
Not very effective in reducing access time. Further NAND
When the word line power supply is lowered in the case of the type ROM, a large number of unselected memories MO connected to the selected memory MOS transistor are connected.
As a result, the ON resistance of the S-transistor increases, so that the data read performance deteriorates.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of high-speed access by an improved word line bias system.

[0007]

According to the present invention, there is provided a memory cell array in which data is stored in a nonvolatile manner, an address buffer for receiving an external address for selecting data of the memory cell array, and a bit of the memory cell array based on the received address. In a semiconductor memory device having a decoder for selecting a line and a word line, and a sense amplifier for reading bit line data, the address buffer has at least two clocks which are commonly connected to an input terminal and take in addresses in a time-division manner. Determining means for determining whether or not address data at consecutive timings held in two address registers of the address buffer have a synchronous address register, and an address based on the determination result of the determining means; While reading data from Next is characterized in that a word line precharge means for selectively precharging only the word line address to be accessed.

In the present invention, preferably, the determination means detects a mismatch between address data held by the two address registers and generates a precharge enable signal, and a logic gate means;
And transfer means for passing the next address data out of the address data held by the two address registers under the control of an enable signal. The word line precharge means includes a precharge row decoder controlled by the precharge enable signal to decode the next address data, and a word line selected by a decode output thereof to apply a predetermined bias to the selected word line. And a precharge row selector that provides

[0009]

According to the present invention, of the many unselected word lines, only the word line selected by the next address is precharged. In such a selective word line precharge, in a semiconductor memory device in which an address buffer has two clock synchronous address registers, it is determined whether address data at successive timings held in these address registers are different. It becomes possible by doing. According to the present invention, especially in the case of the NAND type, high-speed access is possible without deteriorating the data read characteristics as compared with the conventional method of applying a low power supply potential to all the unselected word lines.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an overall configuration of a clock synchronous mask ROM according to an embodiment of the present invention. Mask ROM
As a basic configuration, a memory cell array 1 for storing data in a nonvolatile manner, an address buffer 2 for taking in an external address for reading out the data, a row decoder 3 for selecting a word line of the memory cell array 1, and a column decoder for selecting a bit line 4, a column selector 5, a sense amplifier 6 for detecting data read from the memory cell array 1, and an output buffer 7. In this embodiment, the memory cell array 1 is of a NAND type.

The address buffer 2, which will be described later in detail, is of a clock synchronous type having two address registers and taking in external addresses A0, A1,..., A15 by clock synchronization. In this embodiment, a case where A0 to A8 are used as column addresses and A9 to A15 are used as row addresses will be described for convenience. In order to control the operation of the address buffer 2, there is provided a clock generation circuit 8 for generating necessary internal clocks CKA, CKB, A, B (these waveforms are shown in FIG. 10) from the external clock CK. .

In this embodiment, in order to selectively precharge only the next accessed bit line among the non-selected bit lines, the memory cell array 1 and the column decoder 4 and the column selector 5 are separately provided. , A precharge column decoder 11 and a precharge column selector 12 are provided, and a precharge bias circuit 13 for applying a bias to a bit line selected by the precharge column selector 12 is provided. Similarly, in order to selectively precharge only the next selected word line among the unselected word lines to a predetermined level, separately from the row decoder 3, a precharge row decoder 14 and a precharge row selector 15 Is provided.

In order to select and precharge one of the unselected bit lines and unselected word lines, it is necessary to know the address to be accessed next. Therefore, there is provided a next address determination circuit 10 which compares address data at consecutive timings held by two systems of address registers in the address buffer 2, determines the difference, and outputs the next address. Based on the result of the determination by the next address determination circuit 10, the precharge column decoder 11 and the precharge row decoder 1
4 selects one bit line and one word line, respectively.

FIG. 2 shows a specific configuration of the address buffer 2. As shown in the figure, two clock synchronous address registers 21a,
An input terminal 21b is connected to the input circuit 2 in common. Selectors 23 and 24 are provided to select the address data AD of the preceding timing and the next address data NAD of the next timing from the address data of the continuous timing held in the address registers 21a and 21b, respectively. Have been. From the two address registers 21a and 21b, determination address data ADA and ADB are extracted in order to determine the difference between the held address data. Usually, complementary data is output as a pair as the address data AD, but here, they are simply represented by one.

FIG. 3 shows address registers 21a and 21b.
And the parts of the selectors 23 and 24 are shown more specifically. The address registers 21a and 21b are CMOS latch circuits combining clocked CMOS inverters. One address register 21a is driven by an internal clock CKA and its inverted clock / CKA, and the other address register 21b is driven by an internal clock CKA.
KA and / CKA are driven by internal clocks CKB and / CKB which are 180 ° out of phase with each other. Therefore, these address registers 21a and 21b alternately fetch and hold the external address.

The selector 23 is provided with two clocks driven by clocks A and B having phases opposite to each other, which are 1/2 frequency clocks of the external clock CK, in order to alternately extract the data of the two address registers 21a and 21b. And an inverter. The selector 23 alternately extracts the data held in the address registers 21a and 21b, so that the address data AD of the preceding timing is always selected from the consecutive timings. Another selector 24 is similarly constituted by two clocked inverters driven by clocks A and B, and the address data (next address data) of the timing that always follows after the continuous timing.
NAD will be selected.

The address data AD (AD0, AD1,..., AD15) obtained from the address buffer 2 described above.
Means that the column addresses AD0 to AD8 are
Then, the row addresses AD9 to AD15 are sent to the row decoder 3, respectively, and the bit line selection and the word line selection are performed according to the normal operation.

Along with the selected address data AD, the address data ADA and ADB for determination, which are the two systems of address data held in the address buffer 2, and the next address data NAD are sent to the next address determination circuit 10. The next address determination circuit 10 determines whether the address data at successive timings is different or not and the next address data N
It performs AD transfer control and is configured as shown in FIGS.

FIG. 4 shows an EOR column 41 and a sum of outputs of the EOR column 41 as a logic gate means for detecting a mismatch between the determination address data ADA and ADB for each bit of the column address. OR gate 42 is provided. As a result, a precharge enable signal PE (BL) for a bit line which becomes "H" only when addresses at successive timings are different is output. Also, the precharge enable signal PE
A transfer circuit 43 is provided for passing the next address data NAD output from the address buffer 2 and transferring it to the precharge column decoder 11 only when the addresses at successive timings controlled by (BL) are different. I have.

The transfer circuit 43 transmits the next address data NAD
, And a precharge enable signal PE (BL) is set to "H"
And an AND gate 45 that passes only when. Delay circuit 4
Numeral 4 is provided to allow the next address data NAD to pass through after the precharge enable signal PE (BL) is determined.

FIG. 5 shows a judgment circuit on the row address side.
Its basic configuration is the same as that of FIG. 4. An EOR column 51, an OR gate 52 for summing the outputs of the EOR column 51 and generating a precharge enable signal PE (WL) for a word line, and the precharge enable signal It has a transfer circuit 53 for passing the next address data NAD by PE (WL).

As shown in FIG. 6, a precharge column decoder 11 for precharging the bit line of the next address based on the output of the next address determination circuit 10 has the same structure as that of the ordinary column decoder 4. 61
, And a CMOS gate 62 for extracting the decoded outputs PS0, PS1,... Only when the precharge enable signal PE (BL) is "H".

Similarly, the precharge row decoder 14 for precharging the next address word line based on the output of the next address determination circuit 10 is the same as the ordinary row decoder 3 as shown in FIG. Decoder body 71
And a CMOS gate 72 which takes out the decoded output only when the precharge enable signal PE (WL) is "H". Further, a delay circuit 73 is provided in a portion for receiving the precharge enable signal PE (WL). This is to slightly delay the timing of the word line precharge by the precharge row decoder 14 with respect to the word line selection by the row decoder 3, thereby speeding up the precharge while securing the data read characteristics. The specific operation will be described later.

FIG. 8 shows a specific circuit configuration around the bit line selection unit. The column selector 5 selects the bit line BL of the memory cell array 1 based on the output of the column decoder 4 and connects it to the sense amplifier 6, and includes a select transistor for selecting a group of bit lines as shown in FIG. And a select transistor for selecting one bit line. The configuration of the precharge column selector 12 is the same, and a bit line selected by the next address among the non-selected bit lines is selected based on the output of the precharge column decoder 14. Then, the precharge bias circuit 13 precharges the bit line selected by the next address.
The precharge bias circuit 13 has the same configuration as the sense amplifier 6.

FIG. 9 shows a specific circuit configuration around the word line selection unit. One NAND cell of the memory cell array 1 has, for example, eight NMOS transistors M as shown in FIG.
, M7, which are connected to the bit line BL via select transistors S1, S2. The memory MOS transistors M0, M1,... Are set to D type or E type by a mask program. Similarly, the gates of a large number of NAND type cells are commonly used as word lines WL, and select transistors S1, S1
Gates 2 are also commonly connected in the horizontal direction, and the select line SL
1, SL2, and these word lines and select lines are selected by the row decoder 3.

The output portion of the row decoder 3 has different buffer circuits 91 and 91 between the select line selection portion and the word line selection portion.
92 are provided. The buffer circuit 91 of the select line selection unit has a delay circuit 94 and an NMOS transistor 95 for lowering the output level by the delay output thereof in parallel with the buffer main body 93. this is,
The potential of the selected select line is raised by the buffer main body 93 in the initial stage.
This is to keep it at about V. The buffer circuit 92 of the word line selection section is composed of only a buffer body in order to set an unselected word line to VDD.

The precharge row selector 15 driven by the output of the precharge row decoder 14 has an N level for lowering the potential of the word line WL to a predetermined level.
It is constituted by a MOS transistor 96. That is, N
In the case of an AND ROM, when reading data, the selected word line is set to 0 V and the remaining unselected word lines are set to VDD. Of the unselected word lines, the potential of the next accessed word line is set to about 3 V in advance. This is the word line precharge in this embodiment. This precharge potential is supplied to the buffer circuit 92 connected to one end of the word line,
N of the precharge row selector 15 connected to the other end
It is determined by the voltage divided by the on-resistance of the MOS transistor 96, and may be set to a value as low as possible within a range in which an unselected memory MOS transistor can be kept in an on-state required for data reading.

The operation of the NAND type mask ROM having the above configuration will be described below. FIG. 10 is a timing chart of the basic operation. As shown, the external address,
Are supplied to the two address registers 21a and 21b of the address buffer 2 alternately by the internal clocks CKA and CKB having phases opposite to each other. The fetched address data is alternately selected by the selector 23, sent to the column decoder 4 and the row decoder 3 according to a normal operation, and the data is sequentially read.

As described above, address data at two consecutive timings exist in the address buffer 2, and as described with reference to FIG. 2, the address data AD to be accessed now is accessed by the selector 24 next. The next address data NAD to be selected is selected and taken out. When the next address determination circuit 10 determines that the address to be accessed now and the next address are different, the bit line precharge enable signal PE (BL) and the word line precharge enable signal PE (WL ) Is output, and the next address data N
The AD is passed through and sent to the precharge column decoder 11 and the precharge row decoder 14, respectively.

While a certain bit line and a word line are selected and data is read, only the bit line of the next address among the non-selected bit lines is precharged by the bias circuit 13, and similarly, the non-selected word line is read. Of the lines, only the word line of the next address is selected by the precharge row selector 15 and precharged. The bit line precharge is set to a potential of about 3 V where normally the voltage should be 0 V in a non-selected state. The precharging of the word line lowers the normal power supply VDD level to 3V.

Here, the precharge of the word line of the next address is delayed by a predetermined time from the selection of the word line by the row decoder 3 by the delay circuit 73 shown in FIG. The meaning will be described with reference to FIG. As shown in FIG. 11A, it is assumed that the selected word line falls and the remaining unselected word lines rise at timing t0 when the row decoder 3 operates. If the precharge of the word of the next address is started at the same timing t0, as is apparent from the description of FIG.
At the same time, it is selected by the precharge row selector 15.

That is, at this time, the word line of the next address is charged from one end by the row decoder 3 and discharged from the other end by the row selector 15 at the same time. Therefore, as shown by the broken line in FIG. 11B, the rise is delayed, and it takes time to reach 3V. On the other hand, if the start of the precharge is delayed to the timing t1 by the delay circuit 73, as shown by the solid line in FIG. 11B, initially, only the charging by the row decoder 3 at VDD is performed, and therefore, FIG. 5 shows the same rising characteristics as the other unselected word lines. As a result, the high-speed readout characteristics are not hindered despite the fact that the potential of the VDD non-selected word line is set to 3 V. Further, the time until the final precharge potential becomes 3 V is also reduced.

When a word line precharged to 3V is selected next, it is discharged to 0V. At this time, the timing of turning off the transistor 96 of the precharge row selector 15 is delayed by the delay circuit 73, as is apparent from FIG. Therefore,
Since the discharge from the other end continues for the time of the delay circuit 73 at the same time as the discharge of the selected word line by the row decoder 3, the time until the voltage becomes 0 V is shorter than when the precharge operation is stopped simultaneously with the word line selection. Will be shortened.

As described above, according to this embodiment, only the bit line to be accessed next is precharged without precharging all of the many unselected bit lines. Therefore, wasteful power consumption is reduced and high-speed access is enabled, as compared with the method of precharging all non-selected bit lines. Further, according to this embodiment, of the many unselected word lines, only the word line to be accessed next is precharged, thereby enabling high-speed access. Moreover, unlike the conventional method in which a low power supply potential is applied to all the unselected word lines, the unselected word lines except for the next address are driven by VDD, so that the data read characteristics do not deteriorate. Further, among the unselected word lines, the timing for biasing only the unselected word line of the next address to 3 V is delayed with respect to the word line selection, and initially the power supply VDD is used similarly to other unselected word lines. By driving, high-speed access is possible while ensuring excellent read performance.

In the embodiment, the mask ROM having the NAND type memory cells has been described. However, the present invention is not limited to this, and can be similarly applied to the type having the NOR type memory cells. For bit line precharge,
The case of the NOR type memory cell is the same as that of the NAND type memory cell. The word line precharge is slightly different. In the NOR type, VDD is usually applied to the selected word line and 0 V is applied to the unselected word line. , A bias higher than 0 V may be applied. Further, the present invention relates to a mask ROM, an EPROM and an EEPROM.
The same can be applied to.

[0036]

As described above, according to the present invention, in a semiconductor memory device in which an address buffer has two systems of clock synchronous address registers, address data of consecutive timings held in these address registers are provided. And the read performance is degraded by precharging only a word line selected by the next address among a large number of unselected word lines based on the result of the judgment. Without
High-speed access can be realized.

[Brief description of the drawings]

FIG. 1 shows a configuration of a mask ROM according to an embodiment of the present invention.

FIG. 2 shows a specific configuration of an address buffer according to the embodiment.

FIG. 3 shows a more specific configuration of the address buffer.

FIG. 4 shows a configuration of a column address section in the next address determination circuit of the embodiment.

FIG. 5 shows a configuration of a row address section in the next address determination circuit of the embodiment.

FIG. 6 shows a specific configuration of a column decoder of the embodiment.

FIG. 7 shows a specific configuration of a row decoder of the embodiment.

FIG. 8 shows a specific configuration around a bit line selection unit of the embodiment.

FIG. 9 shows a specific configuration around a word line selection unit of the embodiment.

FIG. 10 shows an operation timing of the embodiment.

FIG. 11 shows a state of a word line potential transition in the embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Address buffer, 3 ... Row decoder, 4 ... Column decoder, 5 ... Column selector, 6 ... Sense amplifier, 7 ... Output buffer, 8 ... Clock generation circuit, 10 ... Next address determination circuit, 11 ... Precharge column decoder, 12 ... Precharge column selector, 13 ... Precharge bias circuit, 14 ... Precharge row decoder, 15 ... Precharge row selector, 21a, 21b ... Address register, 23,
24 ... selector.

Claims (2)

(57) [Claims] 1. A memory cell array in which data is stored in a nonvolatile manner, an address buffer for fetching an external address for selecting data of the memory cell array, and a bit line selection and a word line selection of the memory cell array are performed by the fetched address. In a semiconductor memory device having a decoder and a sense amplifier that reads out bit line data, the address buffer has at least two clock-synchronized address registers having input terminals connected in common and taking in addresses in a time-division manner. Determining means for determining whether or not address data at successive timings held in two address registers of the address buffer are different; and performing data reading of an address based on the determination result of the determining means. Address to be accessed next The semiconductor memory device according to claim only the word line selectively, further comprising a word line precharge unit for precharging. 2. The control circuit according to claim 1, wherein said determining means detects a mismatch between address data held by said two sets of address registers and generates a precharge enable signal, and is controlled by said precharge enable signal. Transfer means for passing the next address data out of the address data held by the two systems of address registers; and the word line precharge means comprises:
A precharge row decoder controlled by an enable signal to decode the next address data; and a precharge row selector for selecting one word line based on the decoded output and applying a predetermined bias thereto. 2. The semiconductor memory device according to claim 1, wherein: